Mauro Rossi [Thu, 15 Apr 2021 19:34:12 +0000 (21:34 +0200)]
egl/android: include "util/compiler.h" for FALLTHROUGH macro
Fixes the following building error:
external/mesa/src/egl/drivers/dri2/platform_android.c:1263:10: error: use of undeclared identifier 'FALLTHROUGH'
FALLTHROUGH; /* for pbuffers */
^
1 error generated.
Fixes:
2928c21eb73b ("Convert most remaining free-form fall-through comments to FALLTHROUGH")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10264>
Axel Davy [Thu, 15 Apr 2021 19:59:18 +0000 (21:59 +0200)]
st/nine: Fix compilation error on non-x86 platforms
The unused variable was improperly declared.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4647
Fixes:
d9e79bfe4f ("st/nine: Disable fpu exceptions during init")
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10263>
Michel Dänzer [Fri, 16 Apr 2021 08:49:34 +0000 (10:49 +0200)]
ci: Add test which occasionally times out to lavapipe-vk skips
E.g. https://gitlab.freedesktop.org/mesa/mesa/-/jobs/8912925 .
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10279>
Simon Ser [Thu, 8 Apr 2021 12:10:55 +0000 (14:10 +0200)]
frontends/va: improve surface attribs processing
Instead of checking whether the attribute is settable for each
attrib type, check that once at the beginning of the loop.
Instead of having an if for each attrib type, use a switch.
Return an error if we encounter an unknown attribute. This allows
the caller to make sure settable attributes aren't ignored. The
intel media driver seems to just assert [1] that it doesn't encounter
unknown attributes.
[1]: https://github.com/intel/media-driver/blob/
95d413e519a980f6a7178880ccbfedace092316c/media_driver/linux/common/ddi/media_libva.cpp#L2530
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10104>
Iago Toral Quiroga [Fri, 16 Apr 2021 10:50:00 +0000 (12:50 +0200)]
v3dv: better tracking of dirty push constant state
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10283>
Iago Toral Quiroga [Fri, 16 Apr 2021 10:25:29 +0000 (12:25 +0200)]
v3dv: dirty viewport doesn't affect fragment shaders
The uniform state for the viewport is only used with geometry stages.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10283>
Iago Toral Quiroga [Fri, 16 Apr 2021 08:14:23 +0000 (10:14 +0200)]
v3dv: improve dirty descriptor set state tracking
We were using the pipeline layout to discard uniform updates for
stages that don't use descriptors, but we can do better by keeping
track of the stages used by the specific dirty descriptor sets and
only update uniforms for stages that are included in those.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10283>
Lionel Landwerlin [Tue, 13 Apr 2021 14:53:18 +0000 (17:53 +0300)]
anv: disable baked in pipeline bits from dynamic emission path
In
27ee40f4c9d86e ("anv: Add support for sample locations") we
introduced the ability to emit sample locations baked in as part of
the pipeline or dynamically.
This is different from the previous dynamic states that were always
removed from the pipeline batch and instead emitted dynamically all
the time.
The mistake in
27ee40f4c9d86e is that sample locations are now emitted
all the time, leading to bigger command buffers for unnecessary
reasons.
This change introduces a bit fields of what is baked in the pipeline
and doesn't need to be dynamically emitted.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
4ad4cd89069bfc ("anv: Enabled the VK_EXT_sample_locations extension")
Cc: <mesa-stable>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10282>
Lionel Landwerlin [Fri, 16 Apr 2021 08:08:46 +0000 (11:08 +0300)]
anv: fix 3DSTATE_MULTISAMPLE emission on gen8+
When pipeline->dynamic_state.sample_locations.samples is not set
because the state is dynamic, we're currently calling
genX(emit_multisample) with a 0 samples value which is incorrect.
Found when using renderdoc with the drawing overlay.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
4ad4cd89069bfc ("anv: Enabled the VK_EXT_sample_locations extension")
Cc: <mesa-stable>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10282>
Juan A. Suarez Romero [Fri, 16 Apr 2021 08:21:20 +0000 (10:21 +0200)]
v3dv: avoid dereferencing null value
Fixes CID#1468079 "Dereference null return value (NULL_RETURNS)"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10280>
Rhys Perry [Fri, 9 Apr 2021 15:14:50 +0000 (16:14 +0100)]
radv: fix clearing DCC-compressed e5b9g9r9 images
Fixes
dEQP-VK.api.image_clearing.core.clear_color_image.2d.optimal.single_layer.e5b9g9r9_ufloat_pack32_33x128
with RADV_DEBUG=forcecompress on GFX10.3.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 21.1 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10176>
Adam Jackson [Tue, 13 Apr 2021 22:58:54 +0000 (18:58 -0400)]
glx: Remove some ancient backwards-compatibility typedefs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 22:54:00 +0000 (18:54 -0400)]
glx: Fold client_gl_only array into its one real user
The initialization we're doing for it in __glXExtensionsCtr is trivial,
and this is only to make glGetString(GL_EXTENSIONS) work in indirect
contexts anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 22:40:51 +0000 (18:40 -0400)]
glx: Enable pure-client-library extensions explicitly
These are rare enough to not be worth tracking separately. Especially
since after this change all the known_gl_extensions have N for both
direct_support and direct_only (unsurprising, since that's only used to
compute usable indirect extensions).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 21:12:09 +0000 (17:12 -0400)]
glx: Remove redundant client_support field from extension table
It's always true, simplify accordingly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 21:35:49 +0000 (17:35 -0400)]
glx: Generalize __glXGetStringFromTable a little
Make the second argument optional, and treat its absence as if the
filter always matches.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 21:06:50 +0000 (17:06 -0400)]
glx: Remove some non-functional GL extension from the table
We don't actually have GLX protocol for these in Mesa, hence the initial
N column.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 20:54:31 +0000 (16:54 -0400)]
glx: Mark GLX_{ATI_pixel_format_float,NV_float_buffer} as supported
... at least as far as libGL is concerned, because they'd work just fine
if you tried. The only thing the ATI extension seems to add (I can't
find an official spec, this is inferred from the registry XML) is
selecting the GLX_RENDER_TYPE, which we don't validate before putting on
the wire. The only thing the NV extension adds is an additional fbconfig
attribute, and that only known by glXGetFBConfigAttrib; our
implementation of that just reads the value the server sends, if any,
and doesn't try to filter out unknown attributes.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 20:31:24 +0000 (16:31 -0400)]
glx: Remove major/minor version tracking from extension table
With the previous ancient dead code removed, there's no longer anything
using these values.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 20:21:09 +0000 (16:21 -0400)]
glx: Remove some truly ancient unused code
The "left here but disabled" comment dates to 2004! The idea here is to
add extensions implied by a particular GL version to the GL extension
string, but nothing useful is accomplished by doing so, and this is all
only used in the case of indirect rendering anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 20:01:38 +0000 (16:01 -0400)]
glx: Remove silly __glXGetGLVersion() indirection
Hardcode the values at the one caller that uses them.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Samuel Pitoiset [Mon, 12 Apr 2021 07:24:46 +0000 (09:24 +0200)]
radv: keep DCC compressed for clears on compute with image stores
Without image stores, DCC is always decompressed on compute.
Cc: 21.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10168>
Marek Olšák [Wed, 14 Apr 2021 01:37:40 +0000 (21:37 -0400)]
amd: remove some references to older LLVM versions in comments
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Marek Olšák [Sat, 27 Mar 2021 09:38:57 +0000 (05:38 -0400)]
amd: drop support for LLVM 10
It doesn't support RDNA 2.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Marek Olšák [Sat, 27 Mar 2021 09:34:16 +0000 (05:34 -0400)]
amd: drop support for LLVM 9
This would be easy to support except that it doesn't support RDNA 2.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Samuel Pitoiset [Thu, 30 Jan 2020 10:02:00 +0000 (11:02 +0100)]
amd: drop support for LLVM 8
It doesn't support Navi1x and the removal enables this nice code cleanup.
v2: rebase - mareko
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Marek Olšák [Wed, 14 Apr 2021 19:46:15 +0000 (15:46 -0400)]
ci: don't build clover with LLVM 9 on radeonsi because it's unsupported
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Matt Turner [Tue, 6 Apr 2021 20:14:26 +0000 (13:14 -0700)]
intel/eu: Add instruction compaction support on XeHP.
This patch includes a number of reworks and fixes squashed in by
Nanley Chery, Sagar Ghuge, Jordan Justen and Francisco Jerez.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Tue, 6 Apr 2021 20:11:33 +0000 (13:11 -0700)]
intel/fs: Add more efficient fragment coordinate calculation.
The PIXEL_X/Y opcodes used by the current implementation are broken on
XeHP due to the new regioning restrictions of the floating-point pipe.
We could have the regioning lowering pass fix it in theory by lowering
the conversions into separate MOV instructions, but that would be more
costly than this implementation that only needs a pair of pipelined
ADDs and a pair of pipelined MOVs.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 11 Jan 2019 04:23:53 +0000 (20:23 -0800)]
intel/fs: Introduce lowering pass to implement derivatives in terms of quad swizzles.
Unfortunately the funky Align1 regions used by the code generator in
order to implement derivatives efficiently aren't available to the
floating-point pipeline on XeHP. We need to lower them into a number
of pipelined integer shuffle instructions followed by the
floating-point difference computation.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Fri, 21 Dec 2018 10:21:57 +0000 (02:21 -0800)]
intel/compiler: Lower txd for 3D samplers on XeHP.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Mon, 6 Jan 2020 10:16:57 +0000 (02:16 -0800)]
intel/fs: End computer shader with message gateway on XeHP.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Tue, 6 Apr 2021 20:11:09 +0000 (13:11 -0700)]
intel/fs: Disable 3-src immediates on XeHP.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
[ Francisco Jerez: Add TODO comment explaining why this is helpful and
how we could better fix it. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Tue, 6 Apr 2021 20:10:29 +0000 (13:10 -0700)]
intel/eu: Allow 64-bit registers on XeHP.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Mon, 19 Nov 2018 22:54:43 +0000 (14:54 -0800)]
intel/compiler: Lower integer division on XeHP.
It has been removed from the hardware.
[jordan.l.justen@intel.com: Move to brw_postprocess_nir]
v2: Switch to nir_lower_idiv_precise (Rhys).
v3: Fix for interface changes of nir_lower_idiv.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Rafael Antognolli [Wed, 30 Jan 2019 00:34:30 +0000 (16:34 -0800)]
intel/fs: Lower dword integer multiplies on XeHP.
From the BSpec:
"When multiplying DW X DW, resulting dst can only be QW precision. If
DW precision is required at output than MUL/MACH macro must be used."
So for now simply lower it. We might want to revisit it later.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Tue, 6 Apr 2021 20:05:30 +0000 (13:05 -0700)]
intel/eu: Teach EU validator about FP/DP pipeline regioning restrictions.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Tue, 6 Apr 2021 20:04:26 +0000 (13:04 -0700)]
intel/fs: Handle regioning restrictions of split FP/DP pipelines.
The floating-point and double-precision FPU pipelines of XeHP
platforms don't support arbitrary regioning modes, corresponding
channels of sources and destination are required to be aligned to the
same sub-register offset, similar to the restriction FP64 instructions
had on CHV/BXT platforms.
Most violations of this restriction can be fixed easily by teaching
has_dst_aligned_region_restriction() about the change so the regioning
lowering pass gets rid of any unsupported regioning. For cases where
this is not sufficient (e.g. because a virtual instruction internally
uses some regioning mode not supported by the floating-point pipeline)
the regioning lowering pass is extended with an additional
lower_exec_type() codepath that bit-casts sources and destination to
an integer type whenever the execution type is not supported by the
instruction.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 7 Dec 2018 22:15:03 +0000 (14:15 -0800)]
intel/fs: Fix repclear assembly for XeHP+ regioning restrictions.
The regioning mode used here is no longer supported by the
floating-point pipeline. We could run the regioning lowering pass in
order to fix it with some extra copies, but it's more efficient to
change the instruction to use integer types.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 7 Dec 2018 22:27:24 +0000 (14:27 -0800)]
intel/fs: Use CHV/BXT implementation of 64-bit MOV_INDIRECT on XeHP+.
According to the hardware spec "Vx1 and VxH indirect addressing for
Float, Half-Float, Double-Float and Quad-Word data must not be used."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 19 Feb 2021 07:45:13 +0000 (23:45 -0800)]
intel/fs: Calculate SWSB cross-pipeline synchronization information.
In combination with the previous changes we can just check whether an
instruction has any potentially unsatisfied dependencies on more than
one pipeline, and if so use TGL_PIPE_ALL synchronization with an
appropriate RegDist counter, otherwise synchronize with the single
pipeline it has a dependency on, if any.
Only minor difficulty is caused by the fact that the hardware doesn't
have any way to encode pipeline information when a RegDist and an SBID
dependency need to be provided simultaneously, in which case the
synchronization pipeline is inferred by the hardware. We need to
verify that the hardware's inference will give the correct result
(which may not be the case if e.g. some data was bit-cast from a
different type), and if not emit separate SYNC instructions instead of
baking the RegDist dependency into the instruction (Note that SET SBID
dependencies must always be baked into the corresponding out-of-order
instruction).
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 19 Feb 2021 07:26:57 +0000 (23:26 -0800)]
intel/fs: Represent SWSB in-order dependency addresses as vectors.
This extends the current ordered_address instruction counter to a
vector with one component per asynchronous ALU pipeline, allowing us
to track the last instruction that accessed a register separately for
each ALU pipeline of the XeHP EU, making it straightforward to
infer the right cross-pipeline synchronization annotations.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
v2: Make unit tests happy (with ubsan as run by GitLab automation).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Fri, 17 Apr 2020 22:31:18 +0000 (15:31 -0700)]
Revert "intel/compiler: Silence unused parameter warning in update_inst_scoreboard"
This was a placeholder for the XeHP cross-pipeline synchronization
code, bring it back.
This reverts commit
a80e44902f66244d257c523afe77558cf334d624.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 19 Feb 2021 07:10:38 +0000 (23:10 -0800)]
intel/fs: Add helper functions inferring sync and exec pipeline of an instruction.
Define two helper functions local to the software scoreboard lowering
pass describing the behavior of the hardware and code generator:
inferred_sync_pipe() calculates the ALU pipeline the hardware will
implicitly synchronize with when a RegDist SWSB annotation is used
without providing explicit pipeline synchronization information,
inferred_exec_pipe() infers the ALU pipeline that will execute the
instruction.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Tue, 6 Apr 2021 20:03:45 +0000 (13:03 -0700)]
intel/fs: Implement representation of SWSB cross-pipeline synchronization annotations.
The execution units of XeHP platforms have multiple asynchronous ALU
pipelines instead of (as far as software is concerned) the single
in-order pipeline that handled most ALU instructions except for
extended math in the original Xe. It's now the compiler's
responsibility to identify cross-pipeline dependencies and insert
synchronization annotations whenever necessary, which are encoded as
some additional bits of the SWSB instruction field.
This commit represents the cross-pipeline synchronization annotations
as part of the existing tgl_swsb structure used for codegen. The
existing tgl_swsb_*() helpers used by hand-crafted assembly are
extended to default to TGL_PIPE_ALL big-hammer synchronization in
order to ensure backwards compatibility with the existing assembly.
The following commits will extend the software scoreboard lowering
pass in order to keep track of cross-pipeline dependencies across IR
instructions, and insert more specific pipeline annotations in the
SWSB field.
The disassembler is also extended here to print out any existing
pipeline sync annotations.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Adam Jackson [Tue, 23 Feb 2021 20:28:40 +0000 (15:28 -0500)]
glx/drisw: Enable GLX_ARB_create_context_no_error
Detect this the same way as we do for drihw.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9233>
Iago Toral Quiroga [Thu, 15 Apr 2021 11:47:58 +0000 (13:47 +0200)]
v3dv: fix sRGB blending workaround
This workaround needs to set a flag in the current job but it was
implemented at pipeline binding time, which can happen outside a
render pass. Move it to the pre-draw handler, where it belongs.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4645
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10255>
Christian Gmeiner [Sun, 4 Apr 2021 10:30:16 +0000 (12:30 +0200)]
ci: disable initrd support
For baremetal CI we are using a 'dummy' rootfs as it is required by
abootimg. This causes NFS boot problems when using u-boot as bootloader.
[ 13.230968] RAMDISK: gzip image found at block 0
[ 13.235645] using deprecated initrd support, will be removed in 2021.
[ 13.243106] List of all partitions:
If we disable CONFIG_BLK_DEV_INITRD nfsroot works.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10024>
Yiwei Zhang [Thu, 15 Apr 2021 23:41:49 +0000 (23:41 +0000)]
venus: fix virtgpu_bo_init_dmabuf for classic resource
1. only do size check if the input size is not 0
2. blob_mem can be 0 because guest minigbm uses RESOURCE_CREATE_3D
3. set bo->blob_flags to 0 for classic resource to fail virtgpu_bo_map
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10273>
Eric Anholt [Fri, 16 Apr 2021 00:16:33 +0000 (17:16 -0700)]
ci/freedreno: Skip some precision tests on a530.
These have flaked as Timeouts in CI in the last month. .precision.* is
generally very slow (some in the 15s-30s range), but it's unclear to me
why they sometimes spike up to 60 seconds (thermal throttling?).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10274>
Eric Anholt [Thu, 15 Apr 2021 23:48:57 +0000 (16:48 -0700)]
ci/virgl: Mark a couple of new Crash tests as flakes.
These have shown up in CI runs since the deqp uprev. Also, link the bug
report I made for one of the failing tests.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10274>
Alexander Shi [Wed, 14 Apr 2021 02:22:57 +0000 (19:22 -0700)]
mesa: texparam: Add a clamping macro to handle out-of-range floats returned as integers.
The parameters GL_TEXTURE_MIN_LOD, GL_TEXTURE_MAX_LOD,
GL_TEXTURE_MAX_ANISOTROPY_EXT, GL_TEXTURE_LOD_BIAS are stored as floats but
returned as integers. Setting their values outside of the integer range results
has undefined behaviour when the c-runtime method lroundf converts the value
back to an integer.
Fixes:
53c36dfc('replace IROUND with util functions')
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10244>
Adam Jackson [Thu, 1 Apr 2021 17:44:52 +0000 (13:44 -0400)]
gallium/xlib: Fix for recent gl_config changes
This mirrors the changes needed elsewhere for parts of !9817:
Fixes:
4daef7ffe37 mesa: Remove redundant gl_config::sampleBuffers
Fixes:
4fbe1cbe4cc mesa: Stop tracking visual rating in gl_config
Fixes:
d21b8afa3de mesa: Remove the pretense of aux buffer support
Fixes:
78dfab95b80 mesa: Remove unused gl_config::level
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4544
Acked-by: Eric Anholt <eric@anholt.net>
Tested-by: Jan Zielinski <jan.zielinski@intel.com>
Acked-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10050>
Icecream95 [Thu, 15 Apr 2021 21:45:48 +0000 (09:45 +1200)]
panfrost: Unset shared/scanout binding flags for staging resources
Fixes Xwayland crashes when starting non-GL applications.
Fixes:
e00d94f14f7 ("panfrost: Enable AFBC buffer sharing")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10266>
Icecream95 [Thu, 15 Apr 2021 21:48:58 +0000 (09:48 +1200)]
panfrost: Assert staging resource allocation was successful
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10266>
Adam Jackson [Thu, 15 Apr 2021 18:25:09 +0000 (14:25 -0400)]
Revert "glx: Lift sending the MakeCurrent request to top-level code"
This provokes crashes in Cinnamon for some reason that I haven't
diagnosed yet.
This reverts commit
80b67a3b444f31462890a8e390650fa77c4d2010.
Fixes:
80b67a3b444 glx: Lift sending the MakeCurrent request to top-level code
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4639
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10260>
Yiwei Zhang [Thu, 15 Apr 2021 17:14:11 +0000 (17:14 +0000)]
venus: cap api version to 1.1 for Android
Android hasn't officially adopted 1.2 yet, so we just cap it to avoid
troubles(e.g. vkjson doesn't like 1.2 atm).
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10258>
Eric Anholt [Wed, 14 Apr 2021 22:09:18 +0000 (15:09 -0700)]
freedreno: Fix YUV sampler regression.
We have to keep sampler uniforms around for later YUV lowering, and we
only need to remove uniforms that take up storage space. Code comes from
radeonsi.
Closes: #4644.
Fixes:
de17b4aab568 ("freedreno: Remove uniform variables after finalizing NIR.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10246>
Michel Dänzer [Tue, 13 Apr 2021 16:11:54 +0000 (18:11 +0200)]
ci: Move -Werror enabling from job definitions to meson build script
It was enabled in all jobs.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Sun, 11 Apr 2021 10:50:36 +0000 (12:50 +0200)]
ci: Enable -Werror for the remaining GCC build jobs
Same principle as for clang, with much fewer exceptions left.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Thu, 15 Apr 2021 08:44:33 +0000 (10:44 +0200)]
osmesa: Replace default case FALLTHROUGH annotation by following return
Avoids warning about the annotation with GCC 10:
../src/gallium/frontends/osmesa/osmesa.c: In function ‘osmesa_choose_format’:
../src/util/compiler.h:84:21: warning: attribute ‘fallthrough’ not preceding a case label or default label
84 | #define FALLTHROUGH __attribute__((fallthrough))
| ^~~~~~~~~~~~~
../src/gallium/frontends/osmesa/osmesa.c:316:7: note: in expansion of macro ‘FALLTHROUGH’
316 | FALLTHROUGH;
| ^~~~~~~~~~~
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Sun, 11 Apr 2021 10:45:46 +0000 (12:45 +0200)]
ci: Enable -Werror in clang jobs
They're not warning-clean yet, but we can enable -Werror in general and
just allow the existing types of warnings as exceptions with
-Wno-error=[...]. This way, new warnings of all other types will be
prevented from entering the code base.
Once all warnings of a certain type have been eliminated in a job, the
exception for that type can be dropped from that job. This provides a
realistic path to a fully warning-clean CI build in the future.
v2:
* Use echo -n (Juan A. Suarez)
Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Tue, 13 Apr 2021 15:21:56 +0000 (17:21 +0200)]
Use explicit break instead of fall-through to break-only case
clang generates a warning if there's no explicit break or fall-through
annotation. The latter would be kind of silly in this case, and not
robust against any future changes turning the fall-through invalid.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Tue, 13 Apr 2021 15:12:50 +0000 (17:12 +0200)]
iris: Drop unneeded default switch case
Avoids clang warning about the fall-through annotation.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Tue, 13 Apr 2021 15:44:50 +0000 (17:44 +0200)]
llvmpipe: Drop switch with only default case
Replace it with the default case contents.
Avoids clang warning about the fall-through annotation.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Tue, 13 Apr 2021 15:40:15 +0000 (17:40 +0200)]
Guard FALLTHROUGH annotations after assert()
clang warns if it can determine that the assert() never returns and
there's a fall-through annotation below.
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Sat, 10 Apr 2021 15:11:58 +0000 (17:11 +0200)]
Convert most remaining free-form fall-through comments to FALLTHROUGH
One exception is src/amd/addrlib/, for which -Wimplicit-fallthrough is
explicitly disabled.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Tue, 13 Apr 2021 15:04:49 +0000 (17:04 +0200)]
util: Remove unused Android options_tbl_lock
Avoids warning:
../src/util/os_misc.c:132:21: error: unused variable 'options_tbl_lock' [-Werror,-Wunused-variable]
static simple_mtx_t options_tbl_lock = _SIMPLE_MTX_INITIALIZER_NP;
^
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Michel Dänzer [Tue, 13 Apr 2021 15:04:02 +0000 (17:04 +0200)]
lima/ppir: Cast pointer to uintptr_t instead of uint64_t
Avoids warnings on armhf:
./src/gallium/drivers/lima/ir/pp/nir.c: In function 'ppir_get_block':
../src/gallium/drivers/lima/ir/pp/nir.c:554:66: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
ppir_block *block = _mesa_hash_table_u64_search(comp->blocks, (uint64_t)nblock);
^
../src/gallium/drivers/lima/ir/pp/nir.c: In function 'ppir_compile_nir':
../src/gallium/drivers/lima/ir/pp/nir.c:899:52: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
_mesa_hash_table_u64_insert(comp->blocks, (uint64_t)nblock, block);
^
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10220>
Connor Abbott [Tue, 10 Nov 2020 16:43:47 +0000 (17:43 +0100)]
tu: Expose VK_EXT_robustness2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
Connor Abbott [Tue, 10 Nov 2020 16:41:55 +0000 (17:41 +0100)]
tu: Handle null descriptors
Writing all 0's, including for the format, seems to work. Actually
setting the format seems to break textureSize() (getsize returns 1 for
some reason).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
Connor Abbott [Tue, 10 Nov 2020 16:33:54 +0000 (17:33 +0100)]
tu: Handle robust UBO behavior for pushed UBO ranges
If we push a UBO range but then find out at draw-time that part of the
pushed range is out of range of the UBO descriptor, then we have to fill
in the rest of the range with 0's to mimic the bounds-checking that ldc
would've done.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
Connor Abbott [Tue, 10 Nov 2020 15:54:07 +0000 (16:54 +0100)]
tu: Correctly preserve old push descriptor contents
We were never setting set->size, so we were always copying 0 bytes. But
as we only copy the contents when the layout and therefore the size is
the same, we don't have to take the old size into account anyway.
This fixes some VK_EXT_robustness2 tests that use push descriptors.
Fixes: 6d4f33e ("turnip: initial implementation of VK_KHR_push_descriptor")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
Connor Abbott [Tue, 10 Nov 2020 16:59:03 +0000 (17:59 +0100)]
ir3, tu: Add compiler flag for robust UBO behavior
This needs to be part of the compiler because it's the only piece that
we always have access to in all the places ir3_optimize_loop() is
called, and it's only enabled for the whole Vulkan device. Right now
it's just used for constraining vectorization, but the next commit adds
another use.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
Connor Abbott [Thu, 3 Dec 2020 12:38:42 +0000 (13:38 +0100)]
ir3: Reduce max const file indirect offset base to 9 bits
This fixes
dEQP-VK.robustness.robustness2.bind.notemplate.r32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.len_260.samples_1.1d.frag,
which accesses the shader UBO with c<a0.x + 512> due to the constant
data UBO coming before it in the const file. The len_256 variant has a
smaller constant data UBO, so it uses c<a0.x + 256> instead, and that
works, so 512 seems to be the real limit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
Connor Abbott [Tue, 10 Nov 2020 10:50:29 +0000 (11:50 +0100)]
ir3: Fix list corruption in legalize_block()
We forgot to remove the instruction under consideration from instr_list
before inserting it into the block's list, which caused instr_list to
become corrupted. This happened to work but caused further corruption in
some rare scenarios.
Fixes: adf1659 ("freedreno/ir3: use standard list implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7573>
Gustavo Padovan [Tue, 13 Apr 2021 17:16:18 +0000 (14:16 -0300)]
gitlab-ci: enable Intel AML-Y as experimental
The LAVA lab has been running well with the rammus chromebook for some
time now. Let's add it to MesaCI as experimental to get more testing,
and later enable it in production.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10238>
Gustavo Padovan [Tue, 13 Apr 2021 16:56:02 +0000 (13:56 -0300)]
traces-iris: fix expectation for Intel GLK
glmark2/buffer-columns=200:interleave=true:update-dispersion=0.9:upd...
was missing the expectation checksum.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10238>
Iago Toral Quiroga [Wed, 14 Apr 2021 11:34:00 +0000 (13:34 +0200)]
v3dv: don't use a dedicated BO for each occlusion query
Dedicated BOs waste memory and are also a significant cause of CPU
overhead when applications use hundreds of them per frame due to
all the work the kernel has to do to page in all these BOs for a job.
The UE4 Vehicle demo was hitting this causing it to freeze and stutter
under 1fps.
The hardware allows us to setup groups of 16 queries in consecutive
4-byte addresses, requiring only that each group of 16 queries is
aligned to a 1024 byte boundary. With this change, we allocate all
the queries in a pool in a single BO and we assign them different
offsets based on the above restriction. This eliminates the freezes
and stutters in the Vehicle sample.
One caveat of this solution is that we can only wait or test for
completion of a query by testing if the GPU is still using its BO,
which basically means that we can only wait for all active queries
in a pool to complete and not just the ones being requested by the
API. Since the Vulkan recommendation is to use a different query
pool per frame this should not be a big issue though.
If this ever becomes a problem (for example if an application does't
follow the recommendation and instead allocates a single pool and
splits its queries between frames), we could try to group queries
in a pool into a number of BOs to try and find a balance, but for
now this should work fine in most cases.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10253>
Mike Blumenkrantz [Thu, 15 Apr 2021 12:02:29 +0000 (08:02 -0400)]
docs: update GL_ARB_texture_filter_minmax for zink
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
Mike Blumenkrantz [Sun, 4 Apr 2021 22:44:52 +0000 (18:44 -0400)]
zink: export PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
Mike Blumenkrantz [Sun, 4 Apr 2021 22:44:34 +0000 (18:44 -0400)]
zink: handle minmax sampler creation for VK_EXT_sampler_filter_minmax
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
Mike Blumenkrantz [Sun, 4 Apr 2021 22:44:18 +0000 (18:44 -0400)]
zink: support format queries for VK_EXT_sampler_filter_minmax
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
Mike Blumenkrantz [Sun, 4 Apr 2021 22:44:01 +0000 (18:44 -0400)]
zink: hook up VK_EXT_sampler_filter_minmax
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10248>
Rhys Perry [Wed, 10 Mar 2021 10:42:15 +0000 (10:42 +0000)]
radv: fix barrier in radv_decompress_dcc_compute shader
ACO doesn't create a waitcnt for barriers between texture samples and
image stores because texture samples are supposed to use read-only
memory. It could also schedule the barrier to above the texture sample.
We also have use a larger memory scope to avoid an ACO optimization.
Tested on GFX8 with Sachsa Willems deferred sample. With some DCC
decompressions and the compute path forced.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 21.1 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9496>
Hans-Kristian Arntzen [Mon, 12 Apr 2021 10:15:47 +0000 (12:15 +0200)]
radv: Allocate buffer list for MUTABLE descriptor types as well.
Fixes:
86644b84b94 ("radv: Implement VK_VALVE_mutable_descriptor_type.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10132>
Hans-Kristian Arntzen [Fri, 9 Apr 2021 09:57:06 +0000 (11:57 +0200)]
radv: Take image alignment into account when allocating MUTABLE pool.
Allocating a descriptor set is aligned to 32 bytes, so just like the
other buffer types, bump the descriptor size to 32 bytes when allocating
MUTABLE descriptor types from a pool.
Fixes:
86644b84b94 ("radv: Implement VK_VALVE_mutable_descriptor_type.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10132>
Karol Herbst [Thu, 1 Apr 2021 10:47:05 +0000 (12:47 +0200)]
clover/llvm: handle Fixed vs Scalable vectors explicitly starting with llvm-11
This fixes compilation with llvm-13.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4200
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9973>
Iago Toral Quiroga [Thu, 15 Apr 2021 10:00:40 +0000 (12:00 +0200)]
v3dv: fix array sizes when tracking BOs during uniform setup
The resource indices we get point to descriptor map entries that include
all shader stages, so we need to size the arrays to account for more than
just one stage.
For now we only support up to 2 stages in a pipeline, so we use that.
Fixes:
002304482ce ('v3dv: avoid redundant BO job additions for UBO/SSBO')
Fixes:
fa170dab4c5 ('v3dv: avoid redundant BO job additions for textures and samplers')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10252>
Iago Toral Quiroga [Thu, 15 Apr 2021 09:59:34 +0000 (11:59 +0200)]
v3dv: fix descriptor set limits
There were various issues here:
- MAX_DYNAMIC_UNIFORM_BUFFERS was larger than MAX_UNIFORM_BUFFERS.
- In some cases we were exposing more than the minimums required.
While that is not incorrect, it is not following what we have
been doing in general.
- The Vulkan spec states that some of the MaxDescriptorSet limits
need to be multipled by 6 to include all shader stages, even
if the implementation doesn't support all shader stages.
Fixes:
cbd299b051 ('v3dv/device: do not compute per-pipeline limits multiplying per-stage')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10252>
Alejandro Piñeiro [Wed, 14 Apr 2021 10:49:10 +0000 (12:49 +0200)]
v3dv/debug: use gl stage when checking debug flag
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10229>
Alejandro Piñeiro [Wed, 14 Apr 2021 10:35:03 +0000 (12:35 +0200)]
v3dv/debug: print correct stage name
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10229>
Eric Anholt [Wed, 14 Apr 2021 19:32:58 +0000 (12:32 -0700)]
ci/freedreno: Merge a630 piglit to a single job.
piglit_gl clocked in at 6:12 end-to-end runtime, and piglit_shader spent
2:53 in deqp-runner, so merging them together should be about 9 minutes.
Removing a boot should save us a minute or two of runner time per
pipeline.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10243>
Simon Ser [Fri, 9 Apr 2021 12:07:29 +0000 (14:07 +0200)]
ac/surface: allow non-DCC modifiers for YUV on GFX9+
Accept non-linear tiling for multi-planar formats on GFX9+, as long
as DCC is disabled. DCC support is possible in theory, but untested
for now.
GFX8 is still restricted to linear tiling because it's not yet clear
how modifiers should be handled on these chips for multi-planar
formats. Each plane may need a different modifier.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
Simon Ser [Fri, 9 Apr 2021 12:03:53 +0000 (14:03 +0200)]
radeonsi: stop special-casing YUV formats in si_query_dmabuf_modifiers
Instead of having a special case for YUV formats in
si_query_dmabuf_modifiers, let ac_get_supported_modifiers handle
them. Keep setting external_only = 1 for YUV formats, since we
can only sample from such formats (we can't use them as render
targets).
This shouldn't change si_query_dmabuf_modifiers's behavior, because
for YUV formats ac_get_supported_modifiers will return a single
LINEAR modifier.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
Simon Ser [Fri, 9 Apr 2021 11:58:40 +0000 (13:58 +0200)]
ac/surface: use blocksizebits instead of blocksize
util_format_get_blocksize asserts that the blocksize isn't zero.
However the blocksize will be zero if the format's channel encoding
is unspecified. The channel encoding is only meaningful for the
plain u_format layout, so util_format_get_blocksize can't be used
for formats with another layout. For example, YUV formats don't have
the channel encoding specified.
Use util_format_get_blocksizebits, which just returns zero without
an assertion for formats which don't have a channel encoding.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
Simon Ser [Fri, 9 Apr 2021 11:54:28 +0000 (13:54 +0200)]
util/format: document block depth field
After the pixel block width and height, a third field is used to
store the pixel block depth. Document this field.
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
Simon Ser [Fri, 9 Apr 2021 08:18:44 +0000 (10:18 +0200)]
radeon/vcn: handle tiled buffers when decoding
Set the swizzle mode when decoding.
Add a safe-guard to make sure the provided surface isn't DCC, because
we don't handle this situation.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10134>
Samuel Iglesias Gonsálvez [Thu, 21 Jan 2021 09:23:51 +0000 (10:23 +0100)]
turnip: fix typo in tu_CmdBeginRenderPass2()
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>
Samuel Iglesias Gonsálvez [Wed, 20 Jan 2021 15:22:53 +0000 (16:22 +0100)]
turnip/lrz: added support for depth bounds test enable
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>