Erik Faye-Lund [Thu, 17 Nov 2022 11:15:54 +0000 (12:15 +0100)]
zink: process non-optimal-key passes first
Right now, it's only the vertex-shader that needs special handling for
non-optimal keys. That makes it possible to use fallthrough to always
end up in the last-vertex-stage conditional.
But we're about to add special handling for the geometry stage as well,
so let's prepare by splitting the switch-statement in two; one that only
happens for non-optimal keys, and does all the needed processing there,
and one that deals with the rest.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Tue, 27 Sep 2022 07:43:11 +0000 (09:43 +0200)]
zink: give gs its own shader-key
Line-stipple lowering is going to need some geometry-shader specific
lowering, so lets give the GS its own shader-key struct.
The GS variant only needs a non-optimal variant, so let's assert that to
be sure.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Wed, 26 Oct 2022 13:38:03 +0000 (15:38 +0200)]
zink: emit vars with nir_var_shader_temp mode
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Tue, 27 Sep 2022 07:35:54 +0000 (09:35 +0200)]
zink: add line-stippling lowering passes
There's two notable limitations here:
- This will viewport-map to viewport #0 only. This is because we need
the viewport-scale factors, which we'll be uploading using
push-constants. And we don't want to waste too many of those...
- It's missing a "global" stipple-counter. It doesn't seem like there's
a portable way of implementing this, so this is going to require a VK
extension that can be implemented in a hardware-specific way in the
long run. For now, let's just ignore the global stipple counter.
These two limitations don't seem viable to overcome for now, so but this
is better than nothing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
Erik Faye-Lund [Tue, 27 Sep 2022 10:53:03 +0000 (12:53 +0200)]
zink: setup driver-workaround for missing linestipple
This is not ideal, but at least it should work. In the long run, we
might want to store a bit per mode we're missing, so we can do this
conditionally. But that's quite a bit more complicated, so let's go with
this for now.
The line-stippling logic needs non-optimal shader-keys. So let's drop
some perf on the floor here.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19117>
David Heidelberg [Wed, 30 Nov 2022 09:55:08 +0000 (10:55 +0100)]
ci/alpine: disable the job, still occasionally flakes
See: https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
32689466
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20076>
Emma Anholt [Mon, 28 Nov 2022 19:27:09 +0000 (11:27 -0800)]
glx: Require __DRI_SWRAST >= 4 for doing swrast.
The only implementer in tree is v4.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:25:01 +0000 (11:25 -0800)]
egl: Refactor common error handling for context creation.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:24:15 +0000 (11:24 -0800)]
egl: Bump minimum version of __DRI_SWRAST to 4.
The only implementer in tree is v4. This simplifies some bits now that we
always have CreateContextAttribs.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:22:23 +0000 (11:22 -0800)]
glx: Require __DRI_DRI2 v2 for doing X11 DRI2.
The only implementer in tree is v4.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:20:57 +0000 (11:20 -0800)]
egl: Require __DRI_DRI2 v4 if we're to do DRI2.
The only in-tree implementers are v4.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:19:07 +0000 (11:19 -0800)]
egl: Bump __DRI_CONFIG_OPTIONS min version to 2.
The only implementer in tree is v2.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:12:44 +0000 (11:12 -0800)]
egl: Bump minimum version of __DRI_IMAGE to 6 and drop version checks.
All __DRI_IMAGEs in tree are v6+ (lowest being drisw) and implement
createImageFromTexture.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:08:56 +0000 (11:08 -0800)]
egl: Bump required version of optional __DRI2_FENCE to 2.
The only implementer of it in tree is v2, so no need for checks.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Mon, 28 Nov 2022 19:34:58 +0000 (11:34 -0800)]
gbm: Bump required __DRI_IMAGE version to 6.
That's the minimum implemented in tree (gallium swrast). Drops a few more
version checks.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Wed, 23 Nov 2022 00:58:08 +0000 (16:58 -0800)]
gbm: Drop support for __DRI_DRI2 < 4 and __DRI_SWRAST < 4.
We're always loading a gallium driver built from this tree, so it's always
v4.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Emma Anholt [Sat, 26 Nov 2022 05:44:18 +0000 (21:44 -0800)]
dri: Add notes on what part of the loader interface are used by Xorg.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20044>
Connor Abbott [Tue, 29 Nov 2022 14:56:39 +0000 (15:56 +0100)]
freedreno/fdl: Set sRGB bit for storage images
This probably wasn't noticed earlier because tests using sRGB storage
images didn't exist, and we didn't know whether this works, but this
fixes dEQP-VK.image.store.without_format.2d.*_srgb which also proves
that the bit works.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20060>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:57:25 +0000 (19:57 -0500)]
agx: Clamp point sizes
Fixes vs-point_size-zero.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:46:15 +0000 (19:46 -0500)]
agx: Handle 32-bit gl_FragCoord.zw
The coefficient register is 16-bit so our builder will make the iter 16-bit too
(maybe not the best design...), force fp32 to match the NIR intrinsic.
Fixes glsl-fs-fragcoord-zw-ortho
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:37:25 +0000 (19:37 -0500)]
agx: Handle large varying indices
Fixes glsl-max-varyings.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Fri, 25 Nov 2022 22:06:40 +0000 (17:06 -0500)]
asahi: Support one-sided polygon modes
We can implement glPolygonMode(GL_FRONT_AND_BACK, ...) natively. What we can't
implement natively are two-sided polygon modes. For that Apple has a nontrivial
lowering which I don't feel the need to implement unless someone actually hits a
workload other than Piglit that uses it.
Vulkan requires only one-sided polygon modes (so this is sufficient there), and
GLES doesn't have polygon modes at all. If an app hits the unimplemented case,
throw a warning like Zink does.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 03:19:12 +0000 (22:19 -0500)]
asahi: Handle NULL sampler views
Fixes fp-fragment-position (crash->pass).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 03:08:23 +0000 (22:08 -0500)]
asahi: Unset GL_CLAMP
Use the Zink lowering for the legacy mode, it's not too many instructions on AGX
anyway. Fixes texwrap tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:27:20 +0000 (19:27 -0500)]
asahi: Set frag coord caps correctly
Fixes ./glsl-arb-fragment-coord-conventions, c.f.
12facf23b1f ("panfrost: Don't set CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER").
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Sat, 26 Nov 2022 00:10:54 +0000 (19:10 -0500)]
asahi: Set PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
Fixes arb-provoking-vertex-render.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Alyssa Rosenzweig [Fri, 25 Nov 2022 23:53:17 +0000 (18:53 -0500)]
asahi: Set PIPE_CAP_SUPPORTED_PRIM_MODES
To lower GL_POLYGONS which we don't do natively. Fixes a pile of crashes in
Piglit.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
Jason Ekstrand [Tue, 29 Nov 2022 20:08:50 +0000 (14:08 -0600)]
hasvk: Drop anv_nir_add_base_work_group_id()
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 20:08:22 +0000 (14:08 -0600)]
anv: Drop anv_nir_add_base_work_group_id()
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 20:05:19 +0000 (14:05 -0600)]
intel/nir: Set has_base_workgroup_id for lower_compute_system_values
This option didn't exist half a decade ago when I first implemented base
workgroup support in ANV. It's cleaner to just have split system values
like all the other zero_base+base things do.
We currently only do this for COMPUTE and not KERNEL because it lets us
avoid changing intel_clc for now. We can add KERNEL later if needed.
We also don't do this lowering for task/mesh.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 20:04:50 +0000 (14:04 -0600)]
hasvk: Implement lower_base_workgroup_id
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 20:03:54 +0000 (14:03 -0600)]
anv: Implement lower_base_workgroup_id
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 19:58:29 +0000 (13:58 -0600)]
crocus: Lower load_base_workgroup_id to zero
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 19:58:20 +0000 (13:58 -0600)]
iris: Lower load_base_workgroup_id to zero
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 19:54:55 +0000 (13:54 -0600)]
intel/fs: Support load_workgroup_id_zero_base
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Jason Ekstrand [Tue, 29 Nov 2022 19:52:43 +0000 (13:52 -0600)]
nir/divergence: Handle base_workgroup_id and workgrpu_id_zero_base
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Bas Nieuwenhuizen [Mon, 21 Nov 2022 00:27:49 +0000 (01:27 +0100)]
radv: Remove the old LBVH shader.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>
Bas Nieuwenhuizen [Mon, 21 Nov 2022 00:26:22 +0000 (01:26 +0100)]
radv: Switch to new LBVH implementation.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>
Bas Nieuwenhuizen [Mon, 21 Nov 2022 00:11:36 +0000 (01:11 +0100)]
radv: Add new LBVH shaders.
Contrary to the previous implementation, this actually implements an LBVH builder.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>
Bas Nieuwenhuizen [Tue, 29 Nov 2022 01:28:08 +0000 (02:28 +0100)]
radv: Handle nodes with 2 invalid children in internal node converter.
Fixes:
682dc5c28e4 ("radv: Add conversion shader for internal nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>
Alyssa Rosenzweig [Sat, 29 Oct 2022 19:58:28 +0000 (15:58 -0400)]
panfrost: Enable AFBC of more formats
Enable AFBC for all RGBA UNORM formats possible in v5. This does not
cover the AFBC rules for newer gens, nor for YUV.
Noticed with an uncompressed R8 UNORM texture in SuperTuxKart.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19758>
Alyssa Rosenzweig [Thu, 27 Oct 2022 21:31:08 +0000 (17:31 -0400)]
panfrost: Enable AFBC of sRGB formats
AFBC of sRGB formats should just work. We just need to flip it on and enjoy
the improved performance.
In particular, this means that RGBA8 UNORM and RGBA8 sRGB UNORM are now
considered compatible formats for AFBC. That's a bug fix, because
GALLIUM_HUD use will act like a texture view between sRGB and linear
views. For FBOs, that will "just" result in a decompression, hurting
performance. For window system rendering with AFBC, that will cause an
assertion failure, as we cannot decompress SHARED resources.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19758>
Alyssa Rosenzweig [Sat, 29 Oct 2022 19:38:26 +0000 (15:38 -0400)]
panfrost: Enable AFBC of cube maps
Missed by mistake. This is not the same as 3D AFBC, it's just like a 2D
array. Noted in a supertuxkart pandecode.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19758>
Alyssa Rosenzweig [Wed, 30 Nov 2022 20:33:05 +0000 (15:33 -0500)]
panfrost: Handle all RGB AFBC modes on v9
We're about to enable AFBC on more formats in the core AFBC code. The plane
descriptor packing needs to be aware of these new formats.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19758>
Georg Lehmann [Mon, 28 Nov 2022 16:20:10 +0000 (17:20 +0100)]
aco: Use wave size specific opcode for s_or in cube map coord code.
Cc: mesa-stable
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20041>
Jason Ekstrand [Tue, 29 Nov 2022 19:28:12 +0000 (13:28 -0600)]
nir/builder: Also short-circuit for auto-generated nir_t2t<N>()
This makes nir_i2i32(b, x) behave exactly like nir_i2iN(b, x, 32) etc.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7787
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>
Jason Ekstrand [Tue, 29 Nov 2022 19:10:42 +0000 (13:10 -0600)]
nir/builder: Rework the boolean conversion helpers
Move them up to where the other conversion helpers. For nir_b2<T>(),
suffix them with N like all the others and make them use
nir_type_convert() as well.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>
Jason Ekstrand [Tue, 29 Nov 2022 18:54:21 +0000 (12:54 -0600)]
nir/builder: Drop nir_i2i and nir_u2u in favor of nir_x2xN
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>
Jason Ekstrand [Tue, 29 Nov 2022 18:56:37 +0000 (12:56 -0600)]
nir/builder: Move conversions higher in nir_builder.h
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>
Jason Ekstrand [Tue, 29 Nov 2022 18:48:38 +0000 (12:48 -0600)]
nir/builder: Short-circuit in nir_type_convert if no conversion happens
If both types are the same or both are integer types with the same bit
size, no actual conversion happens and nir_type_conversion_op() will
return nir_op_mov. In this case, there's no point in emitting the move
and we can just return src instead.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>
Jason Ekstrand [Tue, 29 Nov 2022 18:50:33 +0000 (12:50 -0600)]
nir/builder: Fix indentation of nir_type_convert
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>
Jason Ekstrand [Tue, 29 Nov 2022 20:26:44 +0000 (14:26 -0600)]
nir: Fix builder usage in lower_mediump_vars()
In our handling of load_deref, we were calling builder helpers to create
conversions and then adjusting the destination bit size of the load. We
should adjust the bit size first because the builder sometimes looks at
the bit sizes of SSA values passed in as arguments.
Even though it's not strictly necessary, adjust the store_deref case as
well to make it fully symmetric with the load_deref case.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>
Alyssa Rosenzweig [Fri, 28 Oct 2022 01:28:34 +0000 (21:28 -0400)]
pan/mdg: Emulate 8-bit with the 16-bit pipe
We don't care to support i8vec16, we just need a bit of 8-bit support to
implement format packing/unpacking in blend shaders. We're already doing
this by using the 16-bit pipe, we just need to commit to it all the way
-- reporting the correct sizes in max_bitsize_for_alu so the mask
packing logic works as intended -- and dropping the imov-specific hack
that was introduced to workaround a similar class of bugs.
With the previous patch, fixes:
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1
Fixes:
39e4b7279dc ("pan/midg: Fix swizzling on 8-bit sources")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19763>
Alyssa Rosenzweig [Fri, 28 Oct 2022 02:15:24 +0000 (22:15 -0400)]
pan/mdg: Refuse to schedule CSEL.vector to SMUL
Even if we only mask a single component from the result of CSEL.vector,
in our IR we treat its semantics as vector which causes trouble with
when scheduled to a scalar unit.
The problematic bundle looks like this:
vmul.MOV.i32 R31, TMP0.xxxx, R0.yzww
sadd.MAX.i32 TMP0.y, R0.y, #65408
smul.CSEL.vector.i32 R0.y, TMP0.y, #127
As the comment in midgard.h illuminates, these CSEL instructions are
actually operating per-bit, lining up with the all-1's booleans in
Midgard. The Bifrost analogue is MUX.i32.bit, not CSEL.i32. We should
probably rename the Midgard instruction to make that clear.
Anyhoo, on the scalar unit, CSEL/MUX operates on the bottom 32-bits of
its source. That's ok for the usual r31.w case, because that's secretly
replicating to its nonexistent register, I think? But that doesn't work
with the CSEL.vector (MUX.vector) form, because the condition it's
actually muxing on is r31.x, which here is R0.y, not the intended R0.x.
Rather than adding more special cases to the already overcomplicated
scheduler (for the dubious benefit of avoiding a small shaderdb
regression), just avoid scheduling CSEL.vector to smul.
With the next patch, fixes:
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19763>
Daniel Stone [Wed, 30 Nov 2022 15:06:55 +0000 (15:06 +0000)]
ci: Rebalance radv/grunt testing
We've recently rebalanced our lab devices to get a fewer number of
grunts. Switch to scheduling only on the newer shinier ones, running
fewer tests. We'll evaluate the runtime, and if they're quick enough
then we can increase the amount of testing we do.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20081>
Rajnesh Kanwal [Fri, 7 Oct 2022 07:40:11 +0000 (12:40 +0500)]
pvr: Add support to submit occlusion query sub cmds.
Co-authored-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Fri, 7 Oct 2022 07:38:51 +0000 (12:38 +0500)]
pvr: Create a separate compute context for queries.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Thu, 6 Oct 2022 13:10:10 +0000 (18:10 +0500)]
pvr: Set isp userpass to dirty for secondary command buffers.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Thu, 6 Oct 2022 12:13:27 +0000 (17:13 +0500)]
pvr: Process queries and emit write program when ending sub_cmd.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Thu, 6 Oct 2022 12:11:32 +0000 (17:11 +0500)]
pvr: Kick job and end sub_cmd if barrier_store is set in vkCmdExecuteCommands.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Thu, 6 Oct 2022 12:07:08 +0000 (17:07 +0500)]
pvr: Process secondary buffer queries in vkCmdExecuteCommands.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Thu, 6 Oct 2022 12:00:36 +0000 (17:00 +0500)]
pvr: Save error result in cmd_buffer state.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 20:58:16 +0000 (01:58 +0500)]
pvr: Implement vkCmdCopyQueryPoolResults API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 20:57:52 +0000 (01:57 +0500)]
pvr: Implement vkCmdResetQueryPool API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 15:40:44 +0000 (20:40 +0500)]
pvr: Add support to generate query programs.
This commit adds support to generate three types of query related
programs. PVR_QUERY_TYPE_AVAILABILITY_WRITE allows to submit the
queries, PVR_QUERY_TYPE_RESET_QUERY_POOL allows to reset the pool
and PVR_QUERY_TYPE_COPY_QUERY_RESULTS is to copy the results.
Co-authored-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 13:48:24 +0000 (18:48 +0500)]
pvr: Add PVR_SUB_CMD_TYPE_OCCLUSION_QUERY type sub cmd.
Co-authored-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 13:41:46 +0000 (18:41 +0500)]
pvr: Create device specific compute query programs.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 12:19:18 +0000 (17:19 +0500)]
pvr: Implement vkCmdEndQuery API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 12:18:33 +0000 (17:18 +0500)]
pvr: Implement vkCmdBeginQuery API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 11:55:20 +0000 (16:55 +0500)]
pvr: Sequential dependency should be NONE for 0 constant shared regs.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 11:49:08 +0000 (16:49 +0500)]
pvr: Implement vkGetQueryPoolResults API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 11:45:51 +0000 (16:45 +0500)]
pvr: Add support to generate update compute kernel.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 11:43:35 +0000 (16:43 +0500)]
pvr: Add support to generate compute kernel to update shared regs.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Rajnesh Kanwal [Wed, 5 Oct 2022 11:34:24 +0000 (16:34 +0500)]
pvr: Change CDM to compute, TA to geometry and 3D to fragment.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>
Gert Wollny [Tue, 29 Nov 2022 14:53:41 +0000 (15:53 +0100)]
r600: Store nir shaders serialized to save memory
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7247
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20061>
Georg Lehmann [Mon, 28 Nov 2022 16:10:22 +0000 (17:10 +0100)]
aco: Don't prematurely emit s_andn2.
Split s_not + s_and allows more inverse comparision and s_cbranch_vccz
optimizations.
Foz-DB Navi21:
Totals from 516 (0.38% of 134913) affected shaders:
CodeSize: 7273724 -> 7273720 (-0.00%)
Instrs: 1364408 -> 1364407 (-0.00%)
Latency:
14604862 ->
14604858 (-0.00%)
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19143>
Yonggang Luo [Thu, 24 Nov 2022 01:48:40 +0000 (09:48 +0800)]
Revert "radeonsi/ci: update stoney fail -> flakes"
This is partial reverts commit
5ed2265fbf7971800df5fdcf025886f5554f8598.
As the xfail should not be removed from radeonsi-stoney-fails.txt
that point out by Emma Anholt
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>
Yonggang Luo [Fri, 18 Nov 2022 22:07:57 +0000 (06:07 +0800)]
ci: Update radeonsi-raven xfail to flake
Partial revert "ci/amd: add raven flakes which was previously failing"
This reverts commit
fbf93ef82145978858779e95385364b53e2385a4.
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7738
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>
Yonggang Luo [Fri, 18 Nov 2022 20:32:29 +0000 (04:32 +0800)]
ci: Add intel kbl xfail to flake
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7738
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>
Iago Toral Quiroga [Tue, 29 Nov 2022 09:52:33 +0000 (10:52 +0100)]
v3dv: pre-allocate actual events instead of event descriptors
Instead of keeping a free list of "event descriptors" which are
just the offsets in the BO state that are available, pre-allocate
the events. This is simpler as it doesn't require to allocate these
event descriptors at all.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20053>
Eric Engestrom [Thu, 24 Nov 2022 15:59:51 +0000 (15:59 +0000)]
commit_in_branch.py: variables cleanup
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>
Eric Engestrom [Thu, 24 Nov 2022 15:59:51 +0000 (15:59 +0000)]
commit_in_branch.py: add support for checking staging branches
Or any branch that contains a `/` slash.
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>
Eric Engestrom [Thu, 24 Nov 2022 16:29:54 +0000 (16:29 +0000)]
commit_in_branch.py: fix tests
Apparently these were backported since I wrote these tests ^^
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>
Connor Abbott [Tue, 29 Nov 2022 13:30:00 +0000 (14:30 +0100)]
ir3: Don't save/restore disasm string pointer
It's not in the key, so it randomly may or may not be present, and if it
is present then we don't actually save/restore the contents, so we will
save/restore random pointer values from the last run. Turnip already
disables searching the shader cache when assembly is requested, but
still wrote the final ir3_shader_variant which resulted in trying to
save random stale pointers when saving off the executable if a
subsequent compile hit that cache entry.
This fixes flakes in
dEQP-VK.pipeline.pipeline_library.shader_module_identifier.pipeline_from_id.*
for me.
Fixes:
56909868cd1 ("turnip: implement VK_KHR_pipeline_executable_properties")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20056>
Connor Abbott [Tue, 29 Nov 2022 14:00:04 +0000 (15:00 +0100)]
tu: Fix binding NULL descriptor sets
This fixes the new test
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.other.null_descriptor_set_in_monolithic_pipeline.
Fixes:
e9f5de11d40 ("tu: Initial implementation of VK_EXT_graphics_pipeline_library")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20057>
Lionel Landwerlin [Tue, 29 Nov 2022 23:00:38 +0000 (01:00 +0200)]
radv: enable lower shader call vectorizing
Totals from 5 (71.43% of 7) affected shaders:
MaxWaves: 48 -> 50 (+4.17%)
Instrs: 32012 -> 32070 (+0.18%)
CodeSize: 172672 -> 172932 (+0.15%)
VGPRs: 512 -> 496 (-3.12%)
Latency: 715333 -> 715279 (-0.01%); split: -0.03%, +0.02%
InvThroughput: 149540 -> 146150 (-2.27%); split: -2.29%, +0.02%
VClause: 900 -> 897 (-0.33%)
Copies: 4173 -> 4199 (+0.62%); split: -0.12%, +0.74%
Branches: 1512 -> 1511 (-0.07%)
PreVGPRs: 475 -> 469 (-1.26%)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20075>
Samuel Pitoiset [Tue, 29 Nov 2022 09:05:48 +0000 (10:05 +0100)]
radv: stop emitting R_00B8A0_COMPUTE_PGM_RSRC3 from the CS preamble
It will be always emitted as part of the compute pipeline.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
Samuel Pitoiset [Tue, 29 Nov 2022 11:00:41 +0000 (12:00 +0100)]
radv: disable VRS entirely on GFX11
Based on registers, VRS changed a lot and it's unclear how to program
it. This disable VK_KHR_fragment_shading_rate, VRS flat shading and
RADV_FORCE_VRS.
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
Samuel Pitoiset [Tue, 29 Nov 2022 07:41:14 +0000 (08:41 +0100)]
radv: do not enable NGG culling on GFX11
RadeonSI disables it as well. It's really unclear if it will help or
not (eg. NGG culling never helped on GFX10).
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
Samuel Pitoiset [Tue, 29 Nov 2022 07:34:24 +0000 (08:34 +0100)]
radv: do not enable DCC for MSAA images without FMASK
I don't know how this is supposed to work, especially for fast clears
because CMASK should be cleared to 0xC but FMASK implies CMASK.
This fixes a bunch of MSAA test failures on GFX10.3 with
RADV_DEBUG=nofmask.
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
Samuel Pitoiset [Tue, 29 Nov 2022 09:22:04 +0000 (10:22 +0100)]
radv: set INTERPOLATE_COMP_Z to 0 on GFX11
Ported from RadeonSI to fix a EQAA bug.
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
Samuel Pitoiset [Tue, 29 Nov 2022 07:59:23 +0000 (08:59 +0100)]
radv: set missing SPI_SHADER_PGM_xxx registers on GFX11
Found by inspection.
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
Erik Faye-Lund [Mon, 29 Aug 2022 12:36:09 +0000 (14:36 +0200)]
nir: Add helper to create passthrough GS shader
Based on nir_create_passthrough_tcs and d3d12_make_passthrough_gs, this
creates a passthrough geometry shader that can be used by drivers that
needs to emulate some graphics features in the geometry shader.
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19987>
Lionel Landwerlin [Tue, 29 Nov 2022 11:42:12 +0000 (13:42 +0200)]
anv: enable lower_shader_calls vectorizing
On Q2RTX RT shaders :
Totals from 7 (22.58% of 31) affected shaders:
Instrs: 15453 -> 14418 (-6.70%)
Cycles: 232647 -> 224959 (-3.30%)
Send messages: 574 -> 481 (-16.20%)
Spill count: 118 -> 106 (-10.17%)
Fill count: 156 -> 140 (-10.26%)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
Lionel Landwerlin [Tue, 29 Nov 2022 10:36:44 +0000 (12:36 +0200)]
nir/lower_shader_calls: enable vectorizer
We cannot fully use the vectorizer outside of this pass because once
stack load/store operations have been lower to global load/store, the
robustness rule applies to those as they would to application
load/store.
But this is all internal and we know it doesn't require out of bound
checking. So doing the vectorizing here is the best solution. We just
have to teach the vectorizer about our intrinsics.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
Lionel Landwerlin [Tue, 29 Nov 2022 18:13:15 +0000 (20:13 +0200)]
nir/lower_shader_calls: add a pass to split load/store into scalars
We'll run this pass prior to opt_load_store_vectorize to maximize the
effect of the optimization.
At the moment opt_load_store_vectorize is unable to pack this :
store vec3
store vec3
store vec2
into this :
store vec4
store vec3
If your backend can only do vec4 stores max.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
Lionel Landwerlin [Mon, 28 Nov 2022 12:31:55 +0000 (14:31 +0200)]
nir/lower_shader_calls: avoid moving loads into loops
This is similar to what opt_gcm is doing. Moving a load inside a loop
will increase memory bandwidth.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
Jessica Clarke [Wed, 30 Nov 2022 00:11:45 +0000 (00:11 +0000)]
panfrost/blend: Fix invalid const values leading to NIR validation errors
Using a designated initializer like this leaves padding bits, which form
part of the aliasing u64/f64 member of the union, uninitialised, but a
nir_const_value must always have the unused bits zeroed out. Thus, use
the nir_const_value_for_float helper instead like everywhere else which
will do a memset 0 for us first.
Without this, using the pan_blend shader in a build with validation
enabled fails with:
NIR validation failed after nir_lower_vars_to_ssa
...
vec4 32 ssa_58 = load_const (0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f800000 /* 1.000000 */)
error: memcmp(val, &cmp_val, sizeof(cmp_val)) == 0 (../src/compiler/nir/nir_validate.c:976)
Fixes:
1378c67bcf9e ("panfrost/blend: Inline blend constants")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20071>
Yiwei Zhang [Mon, 28 Nov 2022 22:29:11 +0000 (22:29 +0000)]
venus: fix android wsi with global fencing disabled
Fixes:
b21e4a7990c ("venus: put android wsi on the sub-optimal path")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20049>
Sajeesh Sidharthan [Thu, 24 Nov 2022 21:59:46 +0000 (13:59 -0800)]
radeonsi/vcn: set current pic index correctly
video corruption observed while running decode test for av1
content in chromeos.
solution is when target buffer is found in render pic list and when
target codec is null, set curr_pic_indx as index to the
pic in render pic list.
Cc: mesa-stable
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20000>