Christian König [Wed, 15 Aug 2018 12:04:47 +0000 (14:04 +0200)]
drm/amdgpu: fix VM size reporting on Raven
Raven doesn't have an VCE block and so also no buggy VCE firmware.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 14 Aug 2018 09:28:46 +0000 (17:28 +0800)]
drm/amdgpu: Set clock ungate state when suspend/fini
After set power ungate state, set clock ungate state
before when suspend or fini.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 14 Aug 2018 08:54:15 +0000 (16:54 +0800)]
drm/amdgpu: Set power ungate state when suspend/fini
Unify to set power ungate state at the begin of suspend/fini.
Remove the workaround code for gfx off feature in
amdgpu_device.c.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 14 Aug 2018 05:32:30 +0000 (13:32 +0800)]
drm/amdgpu: Refine function name and function args
There are no any logical changes here.
1. change function names:
amdgpu_device_ip_late_set_pg/cg_state to
amdgpu_device_set_pg/cg_state.
2. add a function argument cg/pg_state, so
we can enable/disable cg/pg through those functions
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
SivapiriyanKumarasamy [Thu, 26 Jul 2018 18:58:35 +0000 (14:58 -0400)]
drm/amd/display: Program gamut remap as part of stream update
Add gamut remap to dc_stream_update struct, and program if set when updating
streams.
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Krunoslav Kovac [Fri, 20 Jul 2018 19:44:08 +0000 (15:44 -0400)]
drm/amd/display: HDR dynamic meta should be treated as stream update
[Why]
Recently we fixed HDR static meta using AFMT registers to be treated as
fast stream update.
Dynamic meta is still being treated as (full) surface update because it
touches HUBP and it travels with pipe data.
Here we change it to be (fast) stream update.
Note, originally we also wanted to redesign here a bit, but without OS
level support for true dynamic meta, it's left the same. We are simply
using HW that can do dynamic meta to send HDR static meta, I still prefer
keeping it in one static meta type then defining dynamic meta types to
hold the same info. Once we know how OS interfaces look like, we can
do proper design.
[How]
Move dyn meta update from update_hubp_dpp to commit_planes_do_stream_update
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Krunoslav Kovac [Thu, 5 Jul 2018 23:23:17 +0000 (19:23 -0400)]
drm/amd/display: Handle HDR meta update as fast update
[Why]
Vesa DPMS tool sends different HDR meta in OS flips without changing output
parameters. We don't properly update HDR info frame:
- we label HDR meta update as fast update
- when updating HW info frame, we only do it if full update
[How]
It should still be fast update, so when doing HW infoframe update,
do it always no matter the update type.
Also, don't request passive flip for HDR meta update only without output
transfer function or color space changed.
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin lee [Fri, 8 Jun 2018 17:58:36 +0000 (13:58 -0400)]
drm/amd/display: Program vsc_infopacket in commit_planes_for_stream
Signed-off-by: Alvin lee <alvin.lee3@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin lee [Mon, 4 Jun 2018 21:31:25 +0000 (17:31 -0400)]
drm/amd/display: Enable Stereo in Dal3
- program infoframe for Stereo
- program stereo flip control registers properly
v2: Add missing license headers
Signed-off-by: Alvin lee <alvin.lee3@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
SivapiriyanKumarasamy [Fri, 18 May 2018 21:05:52 +0000 (17:05 -0400)]
drm/amd/display: Program vline interrupt on FAST update
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Tue, 1 May 2018 14:39:26 +0000 (10:39 -0400)]
drm/amd/display: decouple front and backend pgm using dpms_off as backend enable flag
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Tue, 8 May 2018 21:09:49 +0000 (17:09 -0400)]
drm/amd/display: add config for sending VSIF
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Sun, 25 Mar 2018 20:28:33 +0000 (16:28 -0400)]
drm/amd/display: Don't force UPDATE_TYPE_FULL if stream_update has hdr_static_metadata
This was missed when pushing public patch for
3e3a40b03847 (drm/amd/display:
Updated HDR Static Metadata to directly take info packet raw)
This is currently no problem yet since we're not doing HDR on Linux yet.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Tue, 17 Apr 2018 15:40:31 +0000 (11:40 -0400)]
drm/amd/display: Correct rounding calcs in mod_freesync_is_valid_range
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Fri, 6 Apr 2018 17:55:39 +0000 (13:55 -0400)]
drm/amd/display: refactor vupdate interrupt registration
We only need to register once OS calls the interrupt control.
Also, if we are entering static screen mode, disable after ramping is done.
Disable shall be done via timer of 2 seconds regardless of ramping
complete or not, just to simplify.
Also, ramp to mid instead of min, due to better flicker performance...
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Fri, 6 Apr 2018 16:12:06 +0000 (12:12 -0400)]
drm/amd/display: fix LFC tearing at top of screen
Tearing occurred because new VTOTAL MIN/MAX was being programmed
too early.
The flip can happen within the VUPDATE high region, and the new min/max
would take effect immediately. But this means that frame is not variable
anymore, and tearing would occur when the flip actually happens.
The fixed insert duration should be programmed on the first VUPDATE
interrupt instead.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Thu, 5 Apr 2018 19:20:15 +0000 (15:20 -0400)]
drm/amd/display: Add back code to allow for rounding error
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Thu, 5 Apr 2018 01:04:42 +0000 (21:04 -0400)]
drm/amd/display: Fix bug that causes black screen
Ignore MSA bit on DP display is usually set during SetTimings, but
there was a case where the module thought refresh rate was not valid
and ignore MSA bit was not set.
Later, a valid refresh rate range was requested but since ignore MSA bit
not set, it caused black screen.
Issue if with how the module checked for VRR support. Fix up that logic.
DM should call new valid_range function to determine if timing is supported.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Thu, 5 Apr 2018 01:01:21 +0000 (21:01 -0400)]
drm/amd/display: Fix bug where refresh rate becomes fixed
This issue occurs if refresh rate range is very small and lfc is not used.
When frame spikes occur, refresh rate becomes fixed and will not restore properly
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Thu, 5 Apr 2018 00:59:43 +0000 (20:59 -0400)]
drm/amd/display: add method to check for supported range
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Tue, 21 Aug 2018 19:40:28 +0000 (14:40 -0500)]
drm/amd/display: Refactor FreeSync module
Remove dependency on internal sink map and instead
use existing stream and plane state
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Wed, 15 Aug 2018 21:49:27 +0000 (16:49 -0500)]
drm/amdgpu: fill in amdgpu_dm_remove_sink_from_freesync_module
Add code to tear down freesync modules when disabled.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Tue, 14 Aug 2018 18:53:53 +0000 (14:53 -0400)]
drm/amdgpu:change VEGA booting with firmware loaded by PSP
With PSP firmware loading, TMR mc address is supposed to be used.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 14 Aug 2018 18:53:52 +0000 (14:53 -0400)]
drm/amdgpu: added support 2nd UVD instance
Added psp fw loading support for vega20 2nd UVD instance.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Wed, 15 Aug 2018 10:58:13 +0000 (12:58 +0200)]
drm/doc: Adapt GPU scheduler references for renamed C file
Fixes: "drm/scheduler: rename gpu_scheduler.c to sched_main.c"
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 19 Jul 2018 12:22:25 +0000 (14:22 +0200)]
drm/amdgpu: use entity instead of ring for CS
Further demangle ring from entity handling.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 18 Jul 2018 14:34:49 +0000 (16:34 +0200)]
drm/amdgpu: move context related stuff to amdgpu_ctx.h
Further unmangle amdgpu.h.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 16 Jul 2018 13:23:15 +0000 (15:23 +0200)]
drm/amdgpu: remove ring lru handling
Not needed any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 16 Jul 2018 13:19:20 +0000 (15:19 +0200)]
drm/amdgpu: remove the queue manager
Not needed any more since that is now done by the scheduler.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 16 Jul 2018 12:59:26 +0000 (14:59 +0200)]
drm/amdgpu: use scheduler load balancing for compute CS
Start to use the scheduler load balancing for userspace compute
command submissions.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 13 Jul 2018 07:12:44 +0000 (09:12 +0200)]
drm/amdgpu: use scheduler load balancing for SDMA CS
Start to use the scheduler load balancing for userspace SDMA
command submissions.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 12 Jul 2018 13:15:21 +0000 (15:15 +0200)]
drm/amdgpu: use new scheduler load balancing for VMs
Instead of the fixed round robin use let the scheduler balance the load
of page table updates.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 14 Aug 2018 18:53:51 +0000 (14:53 -0400)]
drm/amdgpu: Change VCE booting with firmware loaded by PSP
With PSP firmware loading, TMR mc address is supposed to be used.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 6 Aug 2018 13:01:45 +0000 (15:01 +0200)]
drm/scheduler: rename gpu_scheduler.c to sched_main.c
Better match the naming of the other components.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 6 Aug 2018 12:58:56 +0000 (14:58 +0200)]
drm/scheduler: cleanup entity coding style
Cleanup coding style in sched_entity.c
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 6 Aug 2018 12:25:32 +0000 (14:25 +0200)]
drm/scheduler: move entity handling into separate file
This is complex enough on it's own. Move it into a separate C file.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 14 Aug 2018 07:41:12 +0000 (09:41 +0200)]
drm/scheduler: trivial error handling fix
Return -ENOMEM when allocating the rq_list fails.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Fri, 10 Aug 2018 10:50:32 +0000 (18:50 +0800)]
drm/amdgpu: fix integer overflow test in amdgpu_bo_list_create()
We accidentally left out the size of the amdgpu_bo_list struct. It
could lead to memory corruption on 32 bit systems. You'd have to
pick the absolute maximum and set "num_entries ==
59652323" then size
would wrap to 16 bytes.
Fixes:
920990cb080a ("drm/amdgpu: allocate the bo_list array after the list")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Bas Nieuwenhuizen <basni@chromium.org>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 13 Aug 2018 10:37:39 +0000 (18:37 +0800)]
drm/amd/pp: OverDrive gfx domain voltage on Tonga
Also ajust the gfx domain voltage on Tonga when user overdriver
the voltage.
For Tonga, Driver do not update user's setting to voltage table
in smu, we only pick up a minimum value from voltage table that
not less than the user's setting.
v2: fix a typo
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 14 Aug 2018 09:31:09 +0000 (17:31 +0800)]
drm/amdgpu: Cancel the delay work when suspend
Cancel the delay work to avoid the corner case that
ib test was not running when suspend
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 14 Aug 2018 16:44:44 +0000 (11:44 -0500)]
drm/amdgpu: remove experimental flag for vega20
Now that PSP and SMU support is in place.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Tue, 14 Aug 2018 02:33:25 +0000 (10:33 +0800)]
drm/amdgpu/psp: Enlarge PSP TMR SIZE from 3M to 4M.
Enlarge the PSP TMR SIZE to 4M for dual UVD fw front-door loading.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 18 Jul 2018 08:00:03 +0000 (16:00 +0800)]
drm/amdgpu: update vega20 sdma golden settings
Updated vega20 SDMA0 and SDMA1 golden settings.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Thu, 26 Jul 2018 04:31:34 +0000 (12:31 +0800)]
drm/amdgpu/gfx9: Update gfx9 golden settings.
Update the goldensettings for vega20.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 10 Aug 2018 06:27:56 +0000 (14:27 +0800)]
drm/amd/powerplay: added voltage boot time calibration
Run AFLL BTC after upload pptable and before enabling
all smu features.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 30 Jul 2018 06:01:00 +0000 (14:01 +0800)]
drm/amd/powerplay: remove max DCEFCLK limitation
The latest SMU fw removes the limitation that required
UCLK >= DCEFCLK.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 20 Jul 2018 02:56:21 +0000 (10:56 +0800)]
drm/amd/powerplay: allow slow switch only if NBPState enabled
Otherwise there may be potential SMU performance issues.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 20 Jul 2018 02:53:31 +0000 (10:53 +0800)]
drm/amd/powerplay: correct the argument for PPSMC_MSG_SetUclkFastSwitch
The argument was set wrongly. Fast/slow switch was asked when there is
actually a slow/fast switch needed.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 19 Jul 2018 10:40:25 +0000 (18:40 +0800)]
drm/amd/powerplay: avoid enabling/disabling uvd/vce dpm twice
For vega20, there are two UVD rings which share one powerplay instance.
Under some case(two rings used parallel), the uvd dpm is disabled twice
which causes the SMC hang.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 18 Jul 2018 02:59:02 +0000 (10:59 +0800)]
drm/amd/powerplay: remove setting soc floor voltage before sending pptable
SOC voltage is not able to switch and forced to low 0.8V when running HEVC.
Thus the test failed.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 17 Jul 2018 02:22:37 +0000 (10:22 +0800)]
drm/amd/powerplay: enable fclk ss by default
Set fclk ss as enabled on default.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 9 Jul 2018 18:47:04 +0000 (13:47 -0500)]
drm/amdgpu/vg20: Change the load type of vega20 to psp (v2)
Modified the vega20 load type to psp now that psp
support is implemented.
v2: squash in fixes history (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Fri, 11 May 2018 06:54:50 +0000 (14:54 +0800)]
drm/amdgpu: Add psp 11.0 support for vega20. (v2)
Add psp 11.0 code for vega20 and enable it. PSP is the
security processor for the GPU. It handles firmware
loading and GPU resets among other things.
v2: whitespace fix, enable support, adjust reg includes (Alex)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 2 May 2018 07:45:54 +0000 (15:45 +0800)]
drm/amdgpu: enable vega20 powerplay support
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 21 May 2018 02:43:31 +0000 (10:43 +0800)]
drm/amd/powerplay: update vega20 clocks threshold settings on power state adjust
UVD, VCE and SOC clocks need to be taken into consideration. Also, the
thresholds need be updated correspondingly when stable power state is selected.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 21 May 2018 02:24:57 +0000 (10:24 +0800)]
drm/amd/powerplay: revise vega20 PPSMC_MSG_SetSoftMin/[Max]ByFreq settings
UVD, VCE and Socclk also need to be taken into consideration when
setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 21 May 2018 02:19:06 +0000 (10:19 +0800)]
drm/amd/powerplay: new interfaces for overdrive vega20 sclk and mclk
Add support for the new SMU firmware interface for clock adjustment.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 21 May 2018 02:16:41 +0000 (10:16 +0800)]
drm/amd/powerplay: initialize vega20 overdrive settings
The initialized overdrive settings are taken from vbios and SMU(
by PPSMC_MSG_TransferTableSmu2Dram).
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 11 May 2018 08:10:51 +0000 (16:10 +0800)]
drm/amd/powerplay: conv the vega20 pstate sclk/mclk into necessary 10KHz unit
Powerplay uses 10KHz units.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 9 May 2018 03:14:06 +0000 (11:14 +0800)]
drm/amd/powerplay: add vega20 pre_display_config_changed callback
fix possible handshake hang and video playback crash
Corner cases:
- Handshake between SMU and DCE causes hangs when CRTC is not
enabled
- System crash occurs when starting 4K playback with Movies and TV
in an SLS configuration
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 8 May 2018 10:23:16 +0000 (18:23 +0800)]
drm/amd/powerplay: export vega20 stable pstate clocks
Needed for querying the stable pstate clocks.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 8 May 2018 10:27:03 +0000 (18:27 +0800)]
drm/amd/powerplay: correct force clock level related settings for vega20 (v2)
1. The min/max level is determined by soft_min_level/soft_max_level.
2. Vega20 comes with pptable v3 which has no vdd related
table(vdd_dep_on_socclk, vdd_dep_on_mclk) support.
3. Vega20 does not support separate fan feature control(enable or
disable).
v2: squash in fixes:
- bug fix for force dpm level settings
- fix wrong data type
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 4 May 2018 07:20:15 +0000 (15:20 +0800)]
drm/amd/powerplay: init vega20 uvd/vce powergate status on dpm setup
This is essentially necessary when uvd/vce dpm is not enabled yet.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 6 Jul 2018 19:00:37 +0000 (14:00 -0500)]
drm/amd/powerplay: support workload profile query and setup for vega20
Support the power profile API.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Aug 2018 20:55:33 +0000 (15:55 -0500)]
drm/amd/powerplay: add the hw manager for vega20 (v3)
hwmgr is the interface for the driver to setup state
structures which are used by the smu for managing the
power state.
v2: squash in fixes:
- update set_watermarks_for_clocks_ranges to use common code
- drop unsupported apis
- correct MAX_REGULAR_DPM_NUMBER value
- multimonitor fixes
- add check for vbios pptable version
- revise dpm table setup
- init fclk dpm state
- Remove unused definition in vega20_hwmgr
- support power limit setup
- enable vega20 to honour DAL clock limits
- comment out dump_table debugging
v3: switch to SOC15 register access macros
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 11 May 2018 02:56:25 +0000 (10:56 +0800)]
drm/amd/powerplay: new interfaces for ActivityMonitor table with SMU
Vega20 has a new activity monitor table that is stored in memory. Add
API to get and set the new table.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Aug 2018 20:52:41 +0000 (15:52 -0500)]
drm/amd/powerplay: add the smu manager for vega20 (v2)
The SMU manager handles the driver interaction with the SMU
which handles clock and voltage controls.
v2: switch to SOC15 register access macros
reserve space for ActivityMonitor table
enable SMU fw loading
Drop dead code from bringup
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 21 Mar 2018 08:36:08 +0000 (16:36 +0800)]
drm/amd/powerplay: add vega20_pptable.h (v2)
v2: squash in table size fixes
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 21 Mar 2018 08:21:51 +0000 (16:21 +0800)]
drm/amd/powerplay: add vega20_ppsmc.h (v2)
v2: update to latest.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 21 Mar 2018 08:16:41 +0000 (16:16 +0800)]
drm/amd/powerplay: add smu11_driver_if.h (v4)
v2: cleanup
v3: fit the latest 40.6 smc fw
v4: update to latest.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 21 Mar 2018 06:10:21 +0000 (14:10 +0800)]
drm/amd/powerplay: add vega20_inc.h (v2)
v2: use thm 11.0.2 headers
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 2 May 2018 07:50:10 +0000 (15:50 +0800)]
drm/amdgpu: update atomfirmware.h
Add struct atom_smc_dpm_info_v4_3
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Fri, 23 Mar 2018 19:44:28 +0000 (14:44 -0500)]
drm/amdgpu: Add nbio 7.4 support for vega20 (v3)
Some register offset in nbio v7.4 are different with v7.0.
We need a seperate nbio_v7_4.c for vega20.
v2: fix doorbell range for sdma (Alex)
v3: squash in static fix (kbuild test robot)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 3 Apr 2018 20:49:56 +0000 (15:49 -0500)]
Revert "drm/amdgpu: Add nbio support for vega20 (v2)"
Revert this to add proper nbio 7.4 support.
This reverts commit
f5b2e1fa321eff20a9418ebd497d8a466f024a85.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Thu, 10 May 2018 13:23:58 +0000 (21:23 +0800)]
drm/amdgpu/include: Add mp 11.0 header files. (v2)
Add the system management controller v11.0 header files.
v2: cleanup
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 26 Mar 2018 07:29:48 +0000 (15:29 +0800)]
drm/amdgpu/include: add thm 11.0.2 headers
Headers for thermal controller.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Wed, 17 Jan 2018 11:42:33 +0000 (19:42 +0800)]
drm/amdgpu/include: Add sdma0/1 4.2 register headerfiles. (v3)
These are the System DMA register headers for vega20.
v2: cleanups (Alex)
v3: add missing licenses (Alex)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Wed, 17 Jan 2018 12:05:19 +0000 (20:05 +0800)]
drm/amdgpu/include: Add nbio 7.4 header files (v4)
v2: Cleanups (Alex)
v3: More updates (Alex)
v4: more cleanups (Alex)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Rossi [Sun, 12 Aug 2018 19:43:03 +0000 (21:43 +0200)]
drm/radeon: enable ABGR and XBGR formats (v2)
Add support for DRM_FORMAT_{A,X}BGR8888 in atombios_crtc
Swapping of red and blue channels is implemented for radeon chipsets:
DCE2/R6xx and later - crossbar registers defined where needed and used
DCE1/R5xx - AVIVO_D1GRPH_SWAP_RB bit is used
(v2) Set AVIVO_D1GRPH_SWAP_RB bit in fb_format, using bitwise OR for DCE1 path
Use bitwise OR where required for big endian settings in fb_swap
Use existing code style CHIP_R600 condition, fix typo in R600 blue crossbar
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Rossi [Sun, 12 Aug 2018 19:43:02 +0000 (21:43 +0200)]
drm/amdgpu: enable ABGR and XBGR formats (v2)
Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled
(v2) Crossbar registers are defined and used to swap red and blue channels,
keeping the existing coding style in each of the dce modules.
After setting crossbar bits in fb_swap, use bitwise OR for big endian
where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Rossi [Sun, 12 Aug 2018 19:43:01 +0000 (21:43 +0200)]
drm/amd/display: enable ABGR and XBGR formats (v4)
SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 is supported in amd/display/dc/dc_hw_types.h
and the necessary crossbars register controls to swap red and blue channels
are already implemented in drm/amd/display/dc/dce/dce_mem_input.c
(v4) Logic to handle new formats is added only in amdgpu_dm module.
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 10 Aug 2018 18:21:09 +0000 (13:21 -0500)]
drm/amdgpu/powerplay/vega10: enable AVFS control via ppfeaturemask
Allow the user to disable AFVS via ppfeaturemask for debugging.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 10 Aug 2018 18:19:26 +0000 (13:19 -0500)]
drm/amdgpu/powerplay/smu7: enable AVFS control via ppfeaturemask
Allow the user to disable AFVS via ppfeaturemask for debugging.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 10 Aug 2018 18:09:43 +0000 (13:09 -0500)]
drm/amdgpu: add AVFS control to PP_FEATURE_MASK
Add a ppfeaturemask flag to disable AVFS control.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Thu, 19 Jul 2018 00:29:13 +0000 (20:29 -0400)]
drm/amd/display: dc 3.1.62
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Steven Chiu <Steven.Chiu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Sunpeng) Li [Wed, 1 Aug 2018 14:20:53 +0000 (10:20 -0400)]
drm/amd/display: Remove redundant non-zero and overflow check
[Why]
Unsigned int is guaranteed to be >= 0, and read_channel_reply checks for
overflows. read_channel_reply also returns -1 on error, which is what
dc_link_aux_transfer is expected to return on error.
[How]
Remove the if-statement. Return result of read_channel_reply directly.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Wed, 1 Aug 2018 00:14:26 +0000 (20:14 -0400)]
drm/amd/display: add retimer log for HWQ tuning use.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Tue, 17 Jul 2018 21:15:48 +0000 (17:15 -0400)]
drm/amd/display: fix dml handling of mono8/16 pixel formats
mono formats are treated exactly the same as equivallent bpp
444 formats. Dml validation however lacks 444 8 bit format
while dml perf param calculation lacks mono format support
This change makes them equivallent as far as the enum is concerned
to avoid having to update dml
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Mon, 30 Jul 2018 18:41:01 +0000 (14:41 -0400)]
drm/amd/display: Add dprefclk value to dce_dccg
This allows us to avoid any vbios bugs when initializing clocks
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Gloria Li [Thu, 26 Jul 2018 15:32:14 +0000 (11:32 -0400)]
drm/amd/display: fix PIP bugs on Dal3
[Why]
There are outstanding bugs for PIP in Dal3:
-Crash when toggling PIP visibility
-Global Alpha is not working, Adjusting global alpha
doesn’t have an effect
-Cursor is not working with pip plane and pipe splits
-One flash occurs when cursor enters PIP plane from
top/bottom
-Crash when moving PIP plane off the screen
[How]
Resolve divide by 0 error
Implement global alpha
Program cursor on all pipes
Add dst rects' x and y offests into cursor position
Disable cursor when it is beyond bottom/top edge
Signed-off-by: Gloria Li <geling.li@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Thu, 19 Jul 2018 00:28:54 +0000 (20:28 -0400)]
drm/amd/display: dc 3.1.61
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Steven Chiu <Steven.Chiu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 9 Aug 2018 07:26:06 +0000 (15:26 +0800)]
drm/amdgpu: Cancel gfx off delay work when driver fini/suspend
there may be gfx off delay work pending when suspend/driver
unload, need to cancel them first.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 9 Aug 2018 19:24:08 +0000 (14:24 -0500)]
drm/amdgpu/powerplay: check vrefresh when when changing displays
Compare the current vrefresh in addition to the number of displays
when determining whether or not the smu needs updates when changing
modes. The SMU needs to be updated if the vbi timeout changes due
to a different refresh rate. Fixes flickering around mode changes
in some cases on polaris parts.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:29:29 +0000 (16:29 -0400)]
drm/amdgpu: fix emit frame size and comments for jpeg
Fix vcn jpeg ring emit fence size in dword, and fix the naming in comments.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:26:28 +0000 (16:26 -0400)]
drm/amdgpu: add emit trap for vcn jpeg
Add emit trap command in jpeg emit fence call.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:25:42 +0000 (16:25 -0400)]
drm/amdgpu: enable system interrupt for jrbc
Enable system interrupt for jrbc during engine starting time.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:24:18 +0000 (16:24 -0400)]
drm/amdgpu: add system interrupt mask for jrbc
Add new mask for enabling system interrupt for jrbc.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:13:29 +0000 (16:13 -0400)]
drm/amdgpu: add system interrupt register offset header
Add new register offset for enabling system interrupt.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 11 Jul 2018 18:40:18 +0000 (14:40 -0400)]
drm/amdgpu: add emit reg write reg wait for vcn jpeg
The emit_reg_write_reg_wait function was not assigned for vcn jpeg.
This patch adds it back.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 7 Aug 2018 21:30:50 +0000 (16:30 -0500)]
drm/amdgpu/pp: endian fixes for processpptables.c
Properly swap when reading from the vbios.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>