Hou Zhiqiang [Mon, 16 Jan 2017 09:31:47 +0000 (17:31 +0800)]
kconfig: armv8: move armv8 sec_firmware CONFIG_* to Kconfig
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York S: clean up scripts/config_whitelist.txt]
Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Tue, 17 Jan 2017 01:39:17 +0000 (09:39 +0800)]
armv8: aarch64: Fix the warning about x1-x3 nonzero issue
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Wenbin Song [Tue, 17 Jan 2017 10:31:16 +0000 (18:31 +0800)]
armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node
The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if
rev1.1 silicon used, need to fixup the MSI node to match it.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Wenbin Song [Tue, 17 Jan 2017 10:31:15 +0000 (18:31 +0800)]
armv8/ls1043a: fixup GIC offset for ls1043a rev1
The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.
The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.
If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.
Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.
The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Tang Yuantian [Thu, 1 Dec 2016 09:06:58 +0000 (17:06 +0800)]
armv8: fsl-lsch3: enable snoopable sata read and write
By default the SATA IP on the ls208Xa SoCs does not generating
coherent/snoopable transactions. This patch enable it in the
sata axicc register.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 9 Dec 2016 08:09:01 +0000 (16:09 +0800)]
ls1046ardb: Add support power initialization
Add the chip power supply voltage initialization on LS1046ARDB.
Add function power_init_board(), and it will initialize the
PMIC and call the chip power initialization function.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 9 Dec 2016 08:09:00 +0000 (16:09 +0800)]
armv8/fsl_lsch2: Add chip power supply voltage setup
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 9 Dec 2016 08:08:59 +0000 (16:08 +0800)]
ls1046ardb: cpld: add API for selecting core volt
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 9 Dec 2016 08:08:58 +0000 (16:08 +0800)]
pmic: pmic_mc34vr500: Add APIs to set/get SWx volt
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 9 Dec 2016 08:08:57 +0000 (16:08 +0800)]
pmic: pmic_mc34vr500: Add a driver for the mc34vr500 pmic
This patch adds a simple pmic driver for the mc34vr500 pmic which
is used in conjunction with the fsl T1 and LS1 series SoC.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 4 Jan 2017 18:32:08 +0000 (10:32 -0800)]
armv8: fsl-layerscape: Fix SECURE_BOOT config
Without a prompt in Kconfig, SECURE_BOOT cannot be selected by
defconfig. The option was dropped unintentionally when defconfig
files were cleaned up. Three targets were impacted
ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT,
ls2080aqds_SECURE_BOOT.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Udit Agarwal [Fri, 6 Jan 2017 10:28:57 +0000 (15:58 +0530)]
LS2080A: Add validation of MC & DPC images.
Add secure boot validation of MC, DPC images using
esbc_validate command.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Udit Agarwal [Fri, 6 Jan 2017 10:28:56 +0000 (15:58 +0530)]
SECURE_BOOT: Update bootscript and its hdr addresses
Update bootscript and its hdr addresses for Layerscape Chasis 3
based platforms instead of individual SoCs.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Yangbo Lu [Wed, 7 Dec 2016 03:54:33 +0000 (11:54 +0800)]
configs: ls1012a: enable driver model for eSDHC
Enable driver model for eSDHC on ls1012a rdb and qds boards.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Yangbo Lu [Wed, 7 Dec 2016 03:54:32 +0000 (11:54 +0800)]
armv8: ls1012a: add eSDHC nodes
This patch is to add eSDHC nodes for ls1012a.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Yangbo Lu [Wed, 7 Dec 2016 03:54:31 +0000 (11:54 +0800)]
mmc: fsl_esdhc: add 'fsl, esdhc' into of_match table
This patch is to add 'fsl,esdhc' into of_match table to support
driver model for QorIQ eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Yangbo Lu [Wed, 7 Dec 2016 03:54:30 +0000 (11:54 +0800)]
mmc: fsl_esdhc: make GPIO support optional
There would be compiling error as below when enable driver model for esdhc.
undefined reference to `dm_gpio_get_value'
undefined reference to `gpio_request_by_name_nodev'
This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because
all boards of QorIQ platform don't need it and they just check register for
CD/WP status, only some boards of i.MX platform require this.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Tue, 10 Jan 2017 08:44:16 +0000 (16:44 +0800)]
armv8/fsl-lsch3: consolidate the clock system initialization
This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Tue, 10 Jan 2017 08:44:15 +0000 (16:44 +0800)]
armv8/fsl-lsch2: refactor the clock system initialization
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.
This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 6 Jan 2017 09:41:11 +0000 (17:41 +0800)]
ARMv8/fsl-layerscape: Enable data coherency between cores in cluster
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Mingkai Hu [Fri, 6 Jan 2017 09:41:10 +0000 (17:41 +0800)]
armv8: Enable CPUECTLR.SMPEN for coherency
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Prabhakar Kushwaha [Mon, 26 Dec 2016 06:45:08 +0000 (12:15 +0530)]
arm: layerscape: Enable UUID & GPT partition for NXP's ARM SoC
Enable UUID and GPT partition support for NXP's ARM based SoCs
i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A.
Also enable DOS partition for LS1012AFRDM boards.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Tang Yuantian [Tue, 27 Dec 2016 02:24:45 +0000 (10:24 +0800)]
armv8: ls1012: Enable CONFIG_DM_USB in defconfigs
Enables driver model flag CONFIG_DM_USB for LS1012A platform
in defconfigs.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Tang Yuantian [Tue, 27 Dec 2016 02:24:44 +0000 (10:24 +0800)]
armv8: ls1012: added usb nodes in dts
The LS1012A processor has two integrated USB controllers.
One is USB2.0 controller, the other is USB3.0 controller that
allow direct connection to the USB ports with appropriate
protection circuitry and power supplies.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 16 Dec 2016 09:15:46 +0000 (17:15 +0800)]
armv8/fsl_lsch2: Add the OCRAM initialization
Clear the content to zero and the ECC error bit of OCRAM1/2.
The OCRAM must be initialized to ZERO by the unit of 8-Byte before
accessing it, or else it will generate ECC error. And the IBR has
accessed the OCRAM before this initialization, so the ECC error
status bit should to be cleared.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 16 Dec 2016 09:15:45 +0000 (17:15 +0800)]
ARMv8/fsl-layerscape: Correct the OCRAM size
The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU setup.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Tue, 13 Dec 2016 06:54:24 +0000 (14:54 +0800)]
kconfig: move FSL_PCIE_COMPAT to platform Kconfig
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:23 +0000 (14:54 +0800)]
pci: layerscape: remove unnecessary legacy code
All Layerscape SoCs have supported new PCIe driver based on DM.
The lagecy PCIe driver code is unused and can be removed.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:22 +0000 (14:54 +0800)]
armv8: ls2080a: Enable PCIe in defconfigs
The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:21 +0000 (14:54 +0800)]
armv8: ls1046a: Enable PCIe and E1000 in defconfigs
The patch enables PCIe and E1000 in ls1046a related defconfigs.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:20 +0000 (14:54 +0800)]
armv8: ls1043a: Enable PCIe and E1000 in defconfigs
The patch enables PCIe and E1000 in ls1043a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:19 +0000 (14:54 +0800)]
arm: ls1012a: Enable PCIe and E1000 in defconfigs
The patch enables PCIe and E1000 in ls1012a defconfigs and
removes unused PCIe related macro defines
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:18 +0000 (14:54 +0800)]
arm: ls1021a: Enable PCIe in defconfigs
The patch enables PCIe in ls1021a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:17 +0000 (14:54 +0800)]
pci: layerscape: add pci driver based on DM
There are more than five kinds of Layerscape SoCs. unfortunately,
PCIe controller of each SoC is a little bit different. In order
to avoid too many macro definitions, the patch addes a new
implementation of PCIe driver based on DM. PCIe dts node is
used to describe the difference.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Tue, 13 Dec 2016 06:54:16 +0000 (14:54 +0800)]
pci: layerscape: move kernel DT fixup to a separate file
To make the layerscape pcie driver clear, move the kernel DT fixup
code from pcie_layerscape.c to pcie_layerscape_fixup.c.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:15 +0000 (14:54 +0800)]
armv8: ls2080a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:14 +0000 (14:54 +0800)]
armv8: ls1046a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:13 +0000 (14:54 +0800)]
armv8: ls1043a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:12 +0000 (14:54 +0800)]
arm: ls1012a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:11 +0000 (14:54 +0800)]
arm: ls1021a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:10 +0000 (14:54 +0800)]
dm: pci: remove pci_bus_to_hose(0) calling
There may be multiple PCIe controllers in a SoC.
It is not correct that always calling pci_bus_to_hose(0) to get
the first PCIe controller for the PCIe device connected other
controllers. We just remove this calling because hose always point
the correct PCIe controller.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 13 Dec 2016 06:54:09 +0000 (14:54 +0800)]
dm: pci: return the real controller in pci_bus_to_hose()
for the legacy PCI driver, the function pci_bus_to_hose() returns
the real PCIe controller. To keep consistency, this function is
changed to return the PCIe controller pointer of the root bus
instead of the current PCIe bus.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Tue, 13 Dec 2016 06:54:08 +0000 (14:54 +0800)]
configs: ls1021a: enable DT and DM support
Enable DT to support Driver Model.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Minghuan Lian [Tue, 15 Nov 2016 09:35:24 +0000 (17:35 +0800)]
armv8/layerscape: remove unnecessary function declares
For the function alloc_stream_ids() append_mmu_masters() and
fdt_fixup_smmu_pcie() there are no related definitions and they
are never called. So the patch removes the unnecessary declares.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Priyanka Jain [Wed, 9 Nov 2016 06:57:54 +0000 (12:27 +0530)]
armv8: fsl-layerscape, ccn504: Set forced-order mode in RNI-6, RNI-20
It is recommended to set forced-order mode in RNI-6,
RNI-20 for performance optimization in LS2088A.
Both LS2080A, LS2088A families has CONFIG_LS2080A define.
As above update is required only for LS2088A, skip this
for LS2080A SoC family.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
jerry.huang@nxp.com [Tue, 15 Nov 2016 02:47:52 +0000 (10:47 +0800)]
fsl/usb: enable usb feature for ls1046ardb
Enable usb feature for ls1046ardb
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Tom Rini [Mon, 9 Jan 2017 16:57:05 +0000 (11:57 -0500)]
Prepare v2017.01
Signed-off-by: Tom Rini <trini@konsulko.com>
Ladislav Michl [Mon, 9 Jan 2017 10:33:28 +0000 (11:33 +0100)]
lib: gitignore *.elf and *.so generated by efi_loader
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tom Rini [Mon, 9 Jan 2017 01:16:00 +0000 (20:16 -0500)]
scripts/config_whitelist.txt: Resync
Signed-off-by: Tom Rini <trini@konsulko.com>
Jagan Teki [Thu, 5 Jan 2017 14:32:50 +0000 (15:32 +0100)]
mx6ullevk: Add missing MAINTAINERS for mx6ull_14x14_evk_plugin_defconfig
Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig
which is missing in below commit
"imx: mx6ull_14x14_evk: add plugin defconfig"
(sha1:
b90ebf49bb8f74afe68f696f59a0e24cc79f2031)
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Andrew F. Davis [Fri, 6 Jan 2017 22:32:12 +0000 (16:32 -0600)]
am335x: configs: Use ISW_ENTRY_ADDR to set SPL_TEXT_BASE
The SPL load address changes based on boot type in HS devices,
ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs
for similar reasons. Add this same logic for AM33xx devices.
Also make the default value for ISW_ENTRY_ADDR correct for GP
devices based on SoC, HS devices already pick the correct
value in their defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Andrew F. Davis [Fri, 6 Jan 2017 22:20:02 +0000 (16:20 -0600)]
arm: mach-omap2: Fix secure file generation
When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was
not generated but generate an unsigned one anyway, first fix this
warning to say that it was generated but not secured.
When the user then exports TI_SECURE_DEV_PKG after getting this warning,
and tries to re-build, 'make' will detect the build artifacts as
unchanged and so assume they do not need to be re-generated. This causes
it to fail to sign the files and it will pack unsigned files into the
final image, even though TI_SECURE_DEV_PKG is now correctly defined and
working.
Fix this by using FORCE on the targets causes them to be re-run even if
the dependent files have not changed.
This then causes another issue. We currently rename the signed dtb files
to overwrite the non-signed ones. We do this so the 'mkimage' tool gives
the packaged dtb sections the correct name. If we do not rename the files
then SPL will not find them during boot.
Fix this by renaming the dtb files by appending _HS to the end of the
filename, after the ".dtb", this causes them to still be named correctly
in the FIT blob.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Tom Rini [Thu, 5 Jan 2017 00:41:50 +0000 (19:41 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra
Tom Rini [Thu, 5 Jan 2017 00:41:23 +0000 (19:41 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-spi
York Sun [Wed, 28 Dec 2016 16:43:50 +0000 (08:43 -0800)]
powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 to Kconfig
Use Kconfig option SYS_PPC64 instead.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:49 +0000 (08:43 -0800)]
powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig
Use Kconfig option to select chassis version.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:48 +0000 (08:43 -0800)]
powerpc: E6500: Move macro CONFIG_E6500 to Kconfig
Use Kconfig option E6500 and clean up existing usage.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:47 +0000 (08:43 -0800)]
powerpc: mpc85xx: Remove unused ifdef in config header
After most config options are moved to Kconfig, the unused ifdef
or elif can be removed.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:46 +0000 (08:43 -0800)]
ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig
Use Kconfig to select DDR version instead of using config header.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:45 +0000 (08:43 -0800)]
ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:44 +0000 (08:43 -0800)]
ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:43 +0000 (08:43 -0800)]
powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
Use Kconfig to select errata workaround.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:42 +0000 (08:43 -0800)]
mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13,
SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig.
Move existing macros to related Kconfig.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate bk4r1]
Signed-off-by: Tom Rini <trini@konsulko.com>
York Sun [Wed, 28 Dec 2016 16:43:41 +0000 (08:43 -0800)]
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
Use Kconfig to select errata workaround.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:40 +0000 (08:43 -0800)]
fsl_ddr: Move DDR config options to driver Kconfig
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
York Sun [Wed, 28 Dec 2016 16:43:39 +0000 (08:43 -0800)]
powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS
Remove this macro. It was added by
e622d9ed but actually wasn't used.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:38 +0000 (08:43 -0800)]
powerpc: T2081QDS: Remove macro T2081QDS
Use TARGET_T2081QDS from Kconfig instead.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:37 +0000 (08:43 -0800)]
powerpc: T2080RDB: Remove macro CONFIG_T2080RDB
Use TARGET_T2080RDB from Kconfig instead.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:36 +0000 (08:43 -0800)]
powerpc: T2080QDS: Remove macro T2080QDS
Use TARGET_T2080QDS from Kconfig instead.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:35 +0000 (08:43 -0800)]
powerpc: T1040QDS: Remove macro CONFIG_T1040QDS
Use TARGET_T1040QDS from Kconfig instead.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:34 +0000 (08:43 -0800)]
powerpc: T1024RDB: Remove macro CONFIG_T1024RDB
Use TARGET_T1024RDB from Kconfig instead.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Get missing hunk in board/freescale/t102xrdb/ddr.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
York Sun [Wed, 28 Dec 2016 16:43:33 +0000 (08:43 -0800)]
powerpc: T1023RDB: Remove macro CONFIG_T1023RDB
Use TARGET_T1023RDB from Kconfig instead.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:32 +0000 (08:43 -0800)]
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014
Remove these SoCs from Kconfig because they don't have individual
configuration. Clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:31 +0000 (08:43 -0800)]
crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig
Use Kconfig option to set little- or big-endian access to secure
boot and trust architecture.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:30 +0000 (08:43 -0800)]
crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:29 +0000 (08:43 -0800)]
powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate 8572]
Signed-off-by: Tom Rini <trini@konsulko.com>
York Sun [Wed, 28 Dec 2016 16:43:28 +0000 (08:43 -0800)]
powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS to Kconfig
Use Kconfig option for SYS_NUM_TLBCAMS and clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Wed, 28 Dec 2016 16:43:27 +0000 (08:43 -0800)]
powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC to Kconfig
Use Kconfig option for E500 and E500MC macros.
Signed-off-by: York Sun <york.sun@nxp.com>
Jagan Teki [Mon, 2 Jan 2017 23:24:36 +0000 (00:24 +0100)]
mtd: nand: mxs_nand_spl: Fix to remove twise 'NAND' print
SPL from nand will print 'NAND' in boot_from_devices based on
the image_loader name, remove the extra 'NAND ' in mxs_nand_spl driver.
Original behaviour:
-------------------
U-Boot SPL 2017.01-rc2-gf84dd8b (Jan 02 2017 - 22:24:19)
Trying to boot from NANDNAND : 512 MiB
After the fix:
-------------
U-Boot SPL 2017.01-rc2-gf84dd8b-dirty (Jan 02 2017 - 23:17:00)
Trying to boot from NAND: 512 MiB
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Vignesh R [Wed, 21 Dec 2016 05:12:33 +0000 (10:42 +0530)]
spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible
According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Vignesh R [Wed, 21 Dec 2016 05:12:32 +0000 (10:42 +0530)]
spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Misha Komarovskiy [Sun, 11 Dec 2016 19:28:12 +0000 (22:28 +0300)]
ARM: dts: tegra: Sync paz00 with Linux 4.8
Sync with Linux 4.8 dts plus vdd_bl regulator
to fix backlight start, display timings and USB
controller aliases fix.
Signed-off-by: Misha Komarovskiy <zombah@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Marcel Ziswiler [Mon, 19 Dec 2016 14:38:07 +0000 (15:38 +0100)]
colibri_t20: fix ulpi reset polarity
Fix ULPI reset polarity which caused a hard hang on Colibri T20 upon
attempting to start the USB subsystem:
This fixes my late commit
d5a24d8b53d350364bd429b7104ec369b817e4b8
(colibri_t20: fix usb operation and controller order) inadvertently
having overwritten Stephen's previous commit
2f6a7e8ce5df8b99d84bfd486c6f99d92322ce04 (ARM: tegra: fix USB ULPI PHY
reset signal inversion confusion).
While at it also fix comment about on-module USB port.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Marcel Ziswiler [Mon, 19 Dec 2016 14:38:06 +0000 (15:38 +0100)]
apalis_t30: comment about disabled pcie nodes
Add a comment about the disabled PCIe port nodes.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Marcel Ziswiler [Mon, 19 Dec 2016 14:38:05 +0000 (15:38 +0100)]
pci: kconfig: fix spelling in description
Fix 'driver model' rather than 'driver mode' in description.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Marcel Ziswiler [Mon, 19 Dec 2016 14:38:04 +0000 (15:38 +0100)]
video: tegra: fix spelling in comment
Get rid of spurious 'are' in the comment.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Fri, 2 Dec 2016 19:26:42 +0000 (12:26 -0700)]
ARM: tegra: allow passing cboot DTB to the kernel
Some users may wish to pass the cboot-supplied DTB to the booted kernel
rather than having U-Boot load the DTB itself. To allow this, expose the
address of the cboot-supplied DTB in environment variable $fdt_addr. At
least when using extlinux.conf, if the user doesn't explicitly specify
which DTB to pass to the kernel, U-Boot passes the DTB referred to by
this variable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Rini [Tue, 3 Jan 2017 01:00:55 +0000 (20:00 -0500)]
Prepare v2017.01-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 2 Jan 2017 21:32:05 +0000 (16:32 -0500)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Fabio Estevam [Mon, 2 Jan 2017 10:44:04 +0000 (08:44 -0200)]
udoo: neo: Fix indentation
The standard way is to put ifdef/endif in the very first column.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Jagan Teki [Wed, 21 Dec 2016 21:14:46 +0000 (22:14 +0100)]
imx6ul: geam6ul: Enable I2C support
Enable I2C support for Engicam GEAM6UL NAND module.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:02:13 +0000 (12:02 +0100)]
imx6ul: geam6ul: Add MAINTAINERS for nand_defconfig
Add Jagan as MAINTAINERS of configs/imx6ul_geam_nand_defconfig
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:29 +0000 (12:00 +0100)]
configs: engicam: Add fitboot env support
Add FIT image booting from MMC device, during MMC bootcmd
u-boot env script look for bootscript, else fit image or else
finally look for legacy image uImage.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:28 +0000 (12:00 +0100)]
configs: engicam: Cleanup on mmcboot env
- Add tab space
- remove exctra 'mmc dev ${mmcdev}'
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:27 +0000 (12:00 +0100)]
configs: engicam: Enable CONFIG_IMAGE_FORMAT_LEGACY
Enabling FIT along with Signature will make bootm to
not-understanding u-boot legacy image formats like uImage, etc.
So this patch enabling legacy image format for backward compatibility.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:26 +0000 (12:00 +0100)]
defconfigs: imx6: engicam: Enable FIT
Enable Flattened Image Tree support for all Engicam boards.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:25 +0000 (12:00 +0100)]
imx6: engicam: Add nandboot env support
Add config options for booting Linux from NAND in UBI format.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:24 +0000 (12:00 +0100)]
defconfigs: engicam: Enable UBI commands
Create ubifs.img:
$ mkfs.ubifs -q -r /rootfs -m 4096 -e 253952 -c 7936 -o ubifs.img
Write ubifs.img:
---------------
icorem6qdl> nand erase.part rootfs
icorem6qdl> ubi part rootfs
icorem6qdl> ubi create rootfs
icorem6qdl> ext4load mmc 0:2 ${loadaddr} ubifs.img
166592512 bytes read in 8091 ms (19.6 MiB/s)
icorem6qdl> ubi write ${loadaddr} rootfs ${filesize}
166592512 bytes written to volume rootfs
icorem6qdl> ubifsmount ubi0:rootfs
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:23 +0000 (12:00 +0100)]
defconfigs: engicam: Enable MMC commands in nand
For writing Linux or rootfs on to NAND, the best suitable way
is to use MMC commands since MMC driver by default enabled by
mx6_common.h, hence enabled MMC commands in nand defconfigs.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:22 +0000 (12:00 +0100)]
configs: engicam: Rename nand with gpmi-name in mtdparts
gpmi-nand is the proper name used in nand driver from Linux for all
imx related nand boards, so rename mtdparts name as gpmi-nand instead
of nand, this will eventually reflects all nand info to Linux from
u-boot like mtdparts.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
projects / platform / kernel / u-boot.git / log