virgl: Fix buffer overflow warning:

./src/gallium/winsys/virgl/drm/virgl_drm_winsys.c: In function ‘virgl_drm_winsys_resource_set_type’:
../src/gallium/winsys/virgl/drm/virgl_drm_winsys.c:607:10: warning: array subscript 14 is above array bounds of ‘uint32_t[14]’ {aka ‘unsigned int[14]’} [-Warray-bounds]
  607 |       cmd[VIRGL_PIPE_RES_SET_TYPE_PLANE_OFFSET(i)] = plane_offsets[i];
      |       ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/gallium/winsys/virgl/drm/virgl_drm_winsys.c:582:13: note: while referencing ‘cmd’
  582 |    uint32_t cmd[VIRGL_PIPE_RES_SET_TYPE_SIZE(VIRGL_MAX_PLANE_COUNT)];
      |             ^~~

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18231>

ci: drop last bits of wine32

This allows us droping i386 subarchitecture, which leads to saving about
100 MiB from the base image.

v2:
 - dropped DEBIAN_BUILD_TAG and DEBIAN_BUILD_MINGW_TAG change, since
   DEBIAN_BASE_TAG is enough

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18222>

docs: Add d3d10umd and lavapipe to the doc for the gallium frontends.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17243>

venus: add support for VK_EXT_primitive_topology_list_restart

See:
virgl/virglrenderer!902
olv/venus-protocol!46

Test:
./deqp-vk -n dEQP-VK.pipeline.monolithic.input_assembly.primitive_restart.*

Test run totals:
  Passed:        55/55 (100.0%)
  Failed:        0/55 (0.0%)
  Not supported: 0/55 (0.0%)
  Warnings:      0/55 (0.0%)
  Waived:        0/55 (0.0%)

Signed-off-by: Juston Li <justonli@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18283>

venus: sync venus protocol headers for VK_EXT_primitive_topology_list_restart

Signed-off-by: Juston Li <justonli@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18283>

docs: update perfetto with the latest status

intel and turnip support renderstages.  EGL supports track events.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18260>

pps: enable track_event in system.cfg

This enables MESA_TRACE_* tracepoints.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18260>

venus: use MESA_TRACE_*

Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18260>

util/perf: support and prefer perfetto for cpu trace

To keep tracing working, this also adds util_perfetto_init to
eglGet*Display.

Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18260>

util/perfetto: add a simple C wrapper for track events

The C wrapper only uses public APIs from the C++ SDK.  For efficient
tracepoint skipping, it copies the states of categories (there is one
category in this commit) to a util_perfetto_category_states array.

Other options are to use percetto, or wait for an official C SDK.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18260>

util/perf: fix multiple tracepoints in a scope

Fixes

 "../src/util/perf/cpu_trace.h:32:8: error: redefinition of ‘_mesa_trace_scope___LINE__’"

This should work until someone wants multiple MESA_TRACE_SCOPE on the
same line :)

Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18260>

util/perf: add cpu_trace.h

Move MESA_TRACE_* to the new file.

Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18260>

util/perf: move u_perfetto to here

Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18260>

ci: use shellcheck for .gitlab-ci/container/ directory

It checks our CI shell code in `debian-build-testing` job.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17574>

ci: make shellcheck happy about .gitlab-ci/container/ directory

Makes easier do changes, when shellcheck is warning-free.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17574>

ci: move lava-test into debian-build-testing

Should speed up the debian-testing job by a few seconds.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17574>

ci: rename debian-gallium to debian-build-testing

This should provide a more accurate description of the task
and allow us to offload some minor checks into it.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17574>

freedreno: Add support for upload transfers

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18258>

freedreno/drm: Add offset param for fd_bo_upload()

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18258>

freedreno/drm: Let backend hint about upload vs map

For the virtgpu backend, immediately mmap'ing a buffer can be expensive
(ie. require a sync with host), so for small transfers we'd prefer to go
the upload path.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18258>

freedreno/a6xx: Random indent fixes

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18258>

nv50: fix code heap after pipe_shader_enum change

Instead of keying the shader heaps with the TGSI enum, do it with our nv50
one, so we won't run into issues like this in the future.

Fixes: 27f46465c7a ("gallium/tgsi: reorder pipe shader type defines.")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18236>

ir3: fix predicate splitting in scheduler

Fix up src->def->instr, not src->instr.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7014
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18096>

lavapipe: delete some code

now that the descriptor structs are flattened, more code can be deleted

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

lavapipe: create gallium descriptor image/sampler view types for views

this simplifies handling pipe_sampler_view and pipe_image_view by creating
them at the time the view is created, thus enabling the lifetime of samplerview
objects to be managed by the object that owns them instead of everywhere

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

lavapipe: apply VK_WHOLE_SIZE to bufferviews at creation

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

lavapipe: use gallium buffer descriptor types directly

this cleans up a bit of code

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

lavapipe: delete lvp_buffer::offset

this was always 0

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

lavapipe: use pipe_sampler_state directly in descriptor info

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

lavapipe: replace lvp_sampler internals with pipe_sampler_state

less indirection, less code

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

lavapipe: remove lvp_sampler::state

I don't know what this was for but it's not doing anything now

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

lavapipe: use cso for compute samplers too

somehow I missed this?

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

lavapipe: stop tracking descriptor image layout

this is unused

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17740>

aco: allow direct_fetch=true for vec4 VS input loads

This seems to be a (mostly harmless) mistake from 369b8cffea2.

fossil-db (navi21):
Totals from 15 (0.01% of 135636) affected shaders:
Instrs: 1992 -> 1999 (+0.35%)
Latency: 13557 -> 13567 (+0.07%); split: -0.24%, +0.31%
InvThroughput: 4059 -> 4065 (+0.15%); split: -0.20%, +0.34%
Copies: 186 -> 193 (+3.76%)

fossil-db (polaris10):
Totals from 5 (0.00% of 135610) affected shaders:

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>

aco: don't expand vec3 VS input load to vec4 on GFX6

Removes the (small) possibility of invalid memory access.

fossil-db (pitcairn):
Totals from 35456 (26.15% of 135610) affected shaders:
MaxWaves: 259508 -> 260642 (+0.44%); split: +0.44%, -0.01%
Instrs: 7915383 -> 7965774 (+0.64%); split: -0.09%, +0.72%
CodeSize: 37163748 -> 37524804 (+0.97%); split: -0.04%, +1.01%
SGPRs: 1515128 -> 1513576 (-0.10%); split: -0.27%, +0.17%
VGPRs: 1218376 -> 1211160 (-0.59%); split: -0.71%, +0.12%
SpillSGPRs: 1152 -> 1144 (-0.69%)
Latency: 83777626 -> 83867137 (+0.11%); split: -0.61%, +0.72%
InvThroughput: 25722445 -> 25727745 (+0.02%); split: -0.23%, +0.25%
VClause: 232058 -> 230464 (-0.69%); split: -2.53%, +1.84%
SClause: 322579 -> 322108 (-0.15%); split: -0.76%, +0.61%
Copies: 547032 -> 547954 (+0.17%); split: -1.83%, +2.00%
Branches: 72538 -> 72542 (+0.01%)
PreVGPRs: 898453 -> 897584 (-0.10%); split: -0.13%, +0.03%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>

radv/llvm: fix packed VS inputs on GFX6/GFX10+

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>

aco: fix 16-bit VS inputs

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 3fba5bb9cc4 ("aco: implement 16-bit vertex fetches with tbuffer_load_format_d16_*")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>

radv: fix 16-bit support in radv_lower_vs_input

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: b366fef091d ("radv: optimize the number of loaded components for VS inputs in NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>

radv: remove claimed support for sRGB vertex buffer formats

These probably don't work.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18225>

Revert "ci: disable the freedreno farm."

Should be back now

This reverts commit bc2e1a3ed67fb4cca88229e547f6b95be05c4d5e.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18277>

st_pbo/compute: fix memset() warning

Using memset() to zero a few sequential fields in gl_pixelstore_attrib
is a bit dodgy (what if someone were to add/reorder fields?).  And gcc
emits a warning in optimized builds:

In function ‘memset’,
    inlined from ‘copy_converted_buffer’ at ../src/mesa/state_tracker/st_pbo_compute.c:1038:7,
    inlined from ‘st_GetTexSubImage_shader’ at ../src/mesa/state_tracker/st_pbo_compute.c:1146:7:
/usr/include/x86_64-linux-gnu/bits/string_fortified.h:71:10: warning: ‘__builtin_memset’ offset [9, 24] from the object at ‘packing’ is out of the bounds of referenced subobject ‘RowLength’ with type ‘int’ at offset 4 [-Warray-bounds]
   71 |   return __builtin___memset_chk (__dest, __ch, __len, __bos0 (__dest));
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Just replace the memset with ordinary assignments.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18261>

radv: move determining NGG shader info to radv_fill_shader_info()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: move more MS info to gather_shader_info_ms()

Only the workgroup size computation remains at the same place, but I
think it should be computed in a separate helper later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: move more CS info to gather_shader_info_cs()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: add gather_shader_info_task() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: add gather_shader_info_cs() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: add gather_shader_info_vs() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: add gather_shader_info_tcs() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: add gather_shader_info_tes() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: add gather_shader_info_gs() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: add gather_shader_info_mesh() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: add gather_shader_info_fs() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: move filling cs.block_size

This is used for compute and task shaders and will help for adding
new helpers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: stop gathering info for FS before other stages

This is no longer needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: link primitive ID/clip distance shader info from the new helper

No functional changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: add a helper that links shader info between stages

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: remove redundant VS output parameter assignments

assign_outinfo_params() should already assign them.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: fill radv_vs_output_info unconditionally for vertex related stages

That shouldn't change anything for VS as LS (or as ES) and for
TES as ES because radv_vs_output_info is only used by the last
vertex stage. So, if we have TES+GS, radv_vs_output_info for TES
will be overwritten by GS. This allows to decouple the shader info
pass from other stages.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: stop duplicating radv_vs_output_info

Only the last vertex stage needs to access this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv/llvm: remove unused parameter in handle_vs_outputs_post()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: replace cs.uses_task_rings by ms.has_task

Task shaders always use a ring, so this field was useless somehow.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: remove dead code about task ring when binding a compute pipeline

This is probably a leftover when task shader has been reworked, but it
has no effect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: compute the ESGS itemsize outside of radv_nir_shader_info_pass()

radv_nir_shader_info_pass() should run on individual shaders only, and
"linked" shader info should be done separately for better design.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: use esgs_itemsize when calling ac_nir_lower_es_outputs_to_mem

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

radv: stop duplicating radv_es_output_info

This structure isn't really useful and it contains only one field.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

ac: constify ac_compute_cs_workgroup_size()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>

aco: fix wrong size for 1D images and A16 on GFX9

Size is in bytes, not bits.

Fixes plenty of crashes in CI, like
dEQP-VK.synchronization.op.single_queue.event.write_image_fragment_read_image_tess_eval.image_128_r32_uint.

Fixes: 46f6e2ddbbb ("aco: Implement storage image A16.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18266>

radv: destroy the pipeline layout if creating a library failed

It should be properly cleaned.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18252>

radv: fix missing initialization of the pipeline layout when creating a lib

The base object won't be initialized otherwise.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18252>

radv: remove bogus assertion about independent set layouts with GPL

layout->independent_sets can't be TRUE here.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18252>

radv: re-emit viewports if negative one to one or depth clamp mode changed

The following sequence would be broken if we don't re-emit viewports.

vkCmdSetViewport()
VkCmdBindPipeline(negative_one_to_one = false)
vkCmdDraw()
VkCmdBindPipeline(negative_one_to_one = true)
vkCmdDraw()

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18245>

tu: Update HS_WAVE_INPUT_SIZE formula

A better explanation for SP_HS_WAVE_INPUT_SIZE is that it is the size
of local memory to allocate per wave (which can be more than one
patch), in 256B units.

Then the maximum of 64 makes sense because only 16KB of local memory
is reserved for VS<->HS linkage.

The resulting formula matches the blob behaviour, even when
patch_control_points and tcs_vertices_out have different values,
while the past formula gave wrong answers on gen3+.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Suggested-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17957>

tu: Fix streamout with tess_use_shared

Mirrors 31835ac3b8e30abe2677454bbc1468b4cd04b394 change in freedreno.

Together with "tu: Fix HS input size formula for gen3+" fixes following
tests from GL CTS running via Zink:

  dEQP-GLES31.functional.tessellation.invariance.inner_triangle_set.quads_fractional_odd_spacing
  dEQP-GLES31.functional.tessellation.invariance.inner_triangle_set.triangles_fractional_odd_spacing
  dEQP-GLES31.functional.tessellation.invariance.primitive_set.triangles_fractional_odd_spacing_ccw
  dEQP-GLES31.functional.tessellation.invariance.primitive_set.triangles_fractional_odd_spacing_cw
  dEQP-GLES31.functional.tessellation.invariance.triangle_set.triangles_fractional_odd_spacing
  dEQP-GLES31.functional.tessellation.primitive_discard.quads_fractional_odd_spacing_ccw
  dEQP-GLES31.functional.tessellation.primitive_discard.quads_fractional_odd_spacing_cw
  dEQP-GLES31.functional.tessellation.primitive_discard.triangles_fractional_odd_spacing_ccw
  dEQP-GLES31.functional.tessellation.primitive_discard.triangles_fractional_odd_spacing_cw

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17957>

freedreno: PC_SO_STREAM_CNTL_STREAM_ENABLE has per-stream enable bits

PC_SO_STREAM_CNTL.STREAM_ENABLE mirrors VPC_SO_STREAM_CNTL.STREAM_ENABLE

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17957>

tu: Implement VK_EXT_attachment_feedback_loop_layout

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18064>

zink: wrap discard in a function

This makes discard less weird, and allows us to treat it as
control-flow. This makes things less bizarre for drivers.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7070
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>

zink: add spirv_builder_function_call

It can be useful not just to create functions, but also being able to
call them. This adds the spirv_builder-helper for this.

Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>

zink: type_main -> type_void_func

This type will be reused later on, so let's have the name describe what
is *is*, not what it's *used for*.

Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18244>

intel/pci_ids: Add 0x468b ADL-S PCI-id

Ref: bspec 53655
Fixes: d399c3e861a ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>

intel/pci_ids: Update ADL-S strings

Ref: bspec 53655
Fixes: d399c3e861a ("intel/dev: Add device info for ADL-S")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17569>

r600/sfn: Use a low number for unused target register

This reduces the number of registers reserved by the shader
units and makes more threads possible.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6856

Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>

r600: Fix reporting TGSI IR support

When NIR is not explicitely enabled we still support TGSI.

Fixes: 33765aa92aa5c150873fc210e9d6c1fe22cf8646
    r600/sfn: Enable NIR for pre RG hardware

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>

r600/sfn: Use a heuristic to keep SSBO setup and store close

When SSBO instructions use constant address values the address loading
is immediately ready, scheduling the address loads early increases
the register pressure, so force a new instruction block to work around
this problem.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
   r600/sfn: rewrite NIR backend

v2: do handling in shader block to be thread save (hinted to by Filip)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>

r600/sfn: Don't scan the whole block for ready instructions

Limit the number of tested instructions and the number of
ready instructions that might be taken into account.

This reduces the time needed to run the scheduler significantly.

Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>

r600/sfn: Don't schedule GDS instructions early

Atomic GDS instructions like inc, dec, or read will increase the
register pressure, therefore we shouldn't prioritize scheduling them.

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
    r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>

r600/sfn: Don't tag mem-ring and stream instructions as exports

Export instructions allow burst writes, so it makes send to try
to allocate consecutive registers, but for ring writes we don't
schedule the outputs correctly to exploit this, so for now
don't mark these instructions as export to let the RA restart
picking colors.

When the scheduler starts to emit the ring writes in the right order
to allow for bust writes we might revisit this.

This fixes
  spec@glsl-1.50@execution@variable-indexing@gs-output-array-vec4-index-wr

Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
   r600/sfn: rewrite NIR backend

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>

r600/sfn: Handle color0 writes all on R700 like on EG

Fixes: 069f3869ac3a140898224c8c37d5b3b6349361a4
    r600/sfn: Fix color outputs when color0 writes all

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>

etnaviv: add debug option to disable linear PE feature

Linear PE has already shown to have some rough corner cases in the hardware
and also has performance implications. Add a debug option to allow to disable
the feature, so users can more easily check if some issue is caused by this
feature.

CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>

etnaviv: use linear PE rendering only on properly aligned surfaces

When linear rendering is used together with TS, the color tiles must be fully
contained in a single row of pixels. When wrapping around to the next row
TS gets confused and records wrong tile status information, leading to visual
corruption when the surface is resolved/decompressed.

The corruption can be fixed by increasing the stride alignment for linear
render targets, but that would break some existing use-cases, as some display
engines used together with Vivante GPUs currently don't support strides that
don't match the horizontal display resolution.

For now only enable linear PE rendering when the surface is properly aligned
already. This allows to use the optimization in a lot of common use-cases, but
falls back to the proven tiled rendering with subsequent resolve into linear
for the problematic cases.

CC: mesa-stable #22.2
Fixes: 53445284a42 ("etnaviv: add linear PE support")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>

etnaviv: move checking for MC2.0 for TS into screen init

The decision whether to use fast clear aka TS currently checks for two
feature bits: FAST_CEAR and MC20. We check for MC20, as TS on MC1.0 bypasses
the memory offset and we don't have any way to fixup the GPU address to
account for that. It could be done with some support of the kernel driver,
but then GPUs with MC1.0 are very rare to find these days, so not sure if we
are ever going to bother with that.

Instead of checking two separate feature bits to determine if TS can be used,
mask out the FAST_CLEAR bit from the features when MC20 isn't present. This
way we only have to check for a single feature bit.

CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>

radv: stop emitting RMW context registers for updating sample locations

RMW context registers have been removed in RadeonSI a while ago
because they don't seem good for performance.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>

radv: cleanup dynamic states in radv_emit_graphics_pipeline()

Some dynamic states always need to be emitted when the first pipeline
is emitted, some others depend on pipeline state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>

radv: stop clearing bitfields for registers that are emitted dynamically

These fields aren't set at pipeline creation, so clearing them is
just useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>

radv: stop setting CB_COLOR_CONTROL.ROP3 from the pipeline

This is useless because logic op is a dynamic state and it's already
emitted from the cmdbuf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>

ac/llvm: cast tes_u/v_replaced to float

Otherwise LLVM float ops fail to operate on them.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>

ac/nir/ngg: support clipdist culling

Port from radeonsi.

Besides vertex position based primitive culling, clipdist
attribute can also be used to cull a primitive. Normally
it's used by fixed-pipeline, but when NGG we can treate it
as a culling condition to filter out invisible primitive
before fixed-pipeline.

There are two kinds of clipdist:
1. user define a clip plane explicitly by glClipPlane(),
   fixed-pipeline calculate with vertex position to get
   clipdist, then cull. This is the legacy way.
2. Now GLSL define gl_ClipDistance/gl_CullDiatance so that
   user can calculate clipdist in any way he like.

This implementation support both way.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>

ac/nir/ngg: support component position store

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>

ac/nir/ngg: add gs culling

Port from radeonsi.

Cull primitive after GS thread and before final vertex/primitive
export. GS culling is like VS/TES culling which read out saved
vertex positions of a primitive from LDS then call the primitive
culling algorithm to check whether it's visiable or not, only
passed primitives will be exported.

Unlike the VS/TES culling that read vertex index of a primitive
from VGPRs as shader args, GS will set a primitive complete flag
for each last vertex of a primitive in LDS, so that vertex thread
know the previous 1/2/3 vertex can form a primitive and do primitive
culling.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>

ac/nir/ngg: save and restore position output base for nogs

radeonsi has different driver_location and io location.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>

ac/nir/ngg: save and restore output bit size for gs

radeonsi does not have io nir variables, so need to save output
bit size when lower store_output intrinsic.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17651>