Connor Abbott [Fri, 16 Apr 2021 15:13:30 +0000 (17:13 +0200)]
ir3: Assemble and disassemble swz/gat/sct
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10291>
Connor Abbott [Fri, 16 Apr 2021 12:07:44 +0000 (14:07 +0200)]
ir3: Improve cat1 modifier disassembly
Remove bit that shouldn't be part of (rptN), and rewrite the handling of
(even) and (pos_infinity) to uncover a missing (neg_infinity) modifier.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10291>
Connor Abbott [Fri, 16 Apr 2021 16:36:20 +0000 (18:36 +0200)]
ir3/parser: Fix oob write with immediates array
immediates_count and immediates_size are supposed to have the same
units, but it was only incrementing immediates_count by 1. While we're
here, also fix the case where constants are specified out-of-order.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10291>
Jesse Natalie [Sun, 18 Apr 2021 00:26:37 +0000 (17:26 -0700)]
microsoft/clc: If local size isn't specified either in the shader or at runtime, set it to (1,1,1)
Otherwise we can end up in situations like having divide-by-zero. If the optimization is smart enough
that we end up with a *constant* divide-by-zero, then the DXIL validator will fail to sign, which
can trigger fatal errors with CLOn12.
We want to run an initial translation of all kernels during program build, but at that point we don't
know the local size to be able to specify it through kernel specialization data.
v2: Metadata output of 0 is used to indicate that the size wasn't explicitly specific. Copy the
size to the metadata before overriding it to (1,1,1). If conf was explicitly specified,
update the metadata again (though nobody should be paying attention to it).
Closes: https://github.com/microsoft/OpenCLOn12/issues/20
Closes: https://github.com/darktable-org/darktable/issues/8700
Reviewed-By: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10303>
Stéphane Marchesin [Wed, 14 Apr 2021 06:05:24 +0000 (08:05 +0200)]
virgl: resources without any binding can be cached
Certain games create and destroy lots of resources without binding them.
This can take quite a bit of time and even create unneeded
synchronization. However, we know that if a resource was never bound to
anything, it can be cached. This change does that.
Counting the number of uncached allocation with a tabletop simulator trace:
Before: 2967 uncached allocations over the replay
After: 24 uncached allocations over the replay
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10225>
Erik Faye-Lund [Wed, 7 Apr 2021 17:29:40 +0000 (19:29 +0200)]
nir/lower_tex: do not stumble on 16-bit inputs
If a has been lowered to float16 here, then we end up trying to
construct a vector of mixed precision, which the validator asserts
about.
So let's make sure we use the same type for all arguments.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10201>
Erik Faye-Lund [Mon, 19 Apr 2021 11:30:22 +0000 (13:30 +0200)]
lavapipe: implement VK_EXT_custom_border_color
This fixes a bunch of piglit failures on Zink.
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10320>
Erik Faye-Lund [Mon, 19 Apr 2021 11:25:36 +0000 (13:25 +0200)]
lavapipe: resolve border-color when creating sampler
This is going to make it easier to implement the custom border-color
extension.
While we're moving the code, tweak the memset code a bit, so we don't do
any float-ism in the int-case. It doesn't change anything functionally,
just makes it slightly clearer what's going on here.
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10320>
Mike Blumenkrantz [Thu, 15 Apr 2021 16:50:19 +0000 (12:50 -0400)]
st/pbo: use cso_set_vertex_buffers_and_elements() for st_pbo_draw
this lets us use the more consistent codepath and ordering (buffers -> elems)
as well as set take_ownership=true to skip the unref
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10257>
Mike Blumenkrantz [Thu, 15 Apr 2021 14:20:29 +0000 (10:20 -0400)]
zink: fix tcs input reservation for user vars
tcs user vars are var_size[32], which isn't actually how many slots they need,
just how big the variable is (oops), so this needs to be divided
by MAX_PATCH_VERTICES to get the real slot count
slot mapping has always been broken for all tcs inputs, but this probably fixes
all of the related issues there, including unlimited crashes when playing Tomb Raider
Fixes:
2d98efd3232 ("zink: pre-populate locations in variables")
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10269>
Mike Blumenkrantz [Thu, 15 Apr 2021 14:23:21 +0000 (10:23 -0400)]
zink: fix tcs slot map eval for user vars
tcs user inputs need to have their size adjusted in order to determine whether
they'll overflow the existing slot map
Fixes:
5c5e1abea24 ("zink: evaluate existing slot map during program init and force new map as needed")
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10269>
Mike Blumenkrantz [Thu, 15 Apr 2021 14:24:33 +0000 (10:24 -0400)]
zink: always copy the nir shader before compiling
nir_convert_from_ssa and assign_io_locations both modify this unconditionally,
the latter of which possibly re-modifies variables in ways that can break the
slot map and cause stack overflows during vk driver pipeline compilation
Fixes:
2b4609b66cd ("zink: run nir_convert_from_ssa last during compile")
Fixes:
2d98efd3232 ("zink: pre-populate locations in variables")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10269>
Erik Faye-Lund [Thu, 15 Apr 2021 08:17:55 +0000 (10:17 +0200)]
zink: fix stencil-export cap emission
This cap should only ever be emitted for fragment-shaders, but we
accidentally emit it for all shaders. Let's tighten the check to avoid a
validator warning when emitting non-fragment shaders without support for
VK_EXT_shader_stencil_export.
Fixes:
8724d4fb361 ("zink: check shader stencil output")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10249>
Marek Olšák [Fri, 2 Apr 2021 15:27:31 +0000 (11:27 -0400)]
gallium/util: add easy profiling helpers using TIME_ELAPSED queries
There are no users and that's intentional.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10262>
Gert Wollny [Mon, 19 Apr 2021 07:42:00 +0000 (09:42 +0200)]
Revert "r600: don't set an index_bias for indirect draw calls"
This reverts commit
acdf1a123436cb3fa7d4bbc9cfbb9566c7693de4.
While this commit fixed the gles CTS regressions, it introduced
regressions that made the driver unusable, hence the revert.
Closes #4657
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10311>
Lionel Landwerlin [Sun, 18 Apr 2021 09:45:01 +0000 (12:45 +0300)]
vulkan/util: cast enums to int64_t in switch
With the new Vulkan Video extensions a bunch of enum values have been
added. The problem is that those are behind #ifdef so our generated
code complains that we using enum values not defined.
Since we're not using enum names but integer values, we can silence
all those by casting the enum type to int64_t.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10304>
Dave Airlie [Sun, 18 Apr 2021 23:36:19 +0000 (09:36 +1000)]
iris: move target to isl dim translate to inline.
This avoids a conflict in namespace when crocus wants to use the
same function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10308>
Dave Airlie [Sun, 18 Apr 2021 23:30:49 +0000 (09:30 +1000)]
iris: move get_time into a static in bufmgr code.
This ends up polluting the namespace if you build iris/crocus
at once, just move it to where it's used for now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10308>
Rob Clark [Fri, 16 Apr 2021 19:26:04 +0000 (12:26 -0700)]
freedreno/fdl: Re-indent
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
Rob Clark [Fri, 16 Apr 2021 18:59:30 +0000 (11:59 -0700)]
freedreno/perfcntrs: Re-indent
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
Rob Clark [Fri, 16 Apr 2021 18:34:25 +0000 (11:34 -0700)]
freedreno/ir2: Re-indent
clang-format -fallback-style=none --style=file -i src/freedreno/ir2/*.[ch]
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
Rob Clark [Fri, 16 Apr 2021 18:31:40 +0000 (11:31 -0700)]
freedreno/drm-shim: Re-indent
clang-format -fallback-style=none --style=file -i src/freedreno/drm-shim/*.[ch]
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
Rob Clark [Fri, 16 Apr 2021 18:25:06 +0000 (11:25 -0700)]
freedreno/decode: Re-indent
clang-format -fallback-style=none --style=file -i src/freedreno/decode/*.[ch]
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
Rob Clark [Fri, 16 Apr 2021 17:54:12 +0000 (10:54 -0700)]
freedreno/computerator: Re-indent
clang-format -fallback-style=none --style=file -i src/freedreno/computerator/*.[ch]
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
Rob Clark [Fri, 16 Apr 2021 17:51:51 +0000 (10:51 -0700)]
freedreno/common: Re-indent
clang-format -fallback-style=none --style=file -i src/freedreno/common/*.[ch]
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
Rob Clark [Fri, 16 Apr 2021 17:49:48 +0000 (10:49 -0700)]
freedreno/afuc: Re-indent
clang-format -fallback-style=none --style=file -i src/freedreno/afuc/*.[ch]
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
Rob Clark [Fri, 16 Apr 2021 17:42:48 +0000 (10:42 -0700)]
freedreno/drm: Re-indent
clang-format -fallback-style=none --style=file -i src/freedreno/drm/*.[ch]
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
Marek Olšák [Thu, 15 Apr 2021 00:08:03 +0000 (20:08 -0400)]
radeonsi: fix automatic DCC retiling after compute image stores
Only internal compute shaders use DCC stores, so the TODOs are not
critical yet.
Fixes:
1d64a1045ea - radeonsi: enable dcc image stores on gfx10+
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
Marek Olšák [Thu, 15 Apr 2021 00:08:03 +0000 (20:08 -0400)]
radeonsi: fix automatic DCC retiling after DCC clear and DCC decompression
Fixes:
d4f7962d48b - radeonsi: Add displayable DCC flushing without explicit flushes.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
Marek Olšák [Mon, 12 Apr 2021 01:57:10 +0000 (21:57 -0400)]
radeonsi: fix incorrect comments in culling code and NIR lowering
The lowering code removes the "VS inputs" item from the list because the hw
doesn't support indirect indexing of VS inputs.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
Marek Olšák [Wed, 24 Mar 2021 00:49:18 +0000 (20:49 -0400)]
radeonsi: don't decompress DCC for float formats in si_compute_copy_image
Format reinterpretation disabled it.
Fixes:
1d64a1045ea205ee0297d2f741a824811570fc6d "radeonsi: enable dcc image stores on gfx10+"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
Marek Olšák [Sun, 28 Mar 2021 09:11:09 +0000 (05:11 -0400)]
amd/registers: rename IMG_FORMAT to GFX10_FORMAT to disambiguate the meaning
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
Marek Olšák [Sun, 28 Mar 2021 04:42:13 +0000 (00:42 -0400)]
amd/registers: clean up gfx103.json
because gfx103.json is automatically generated and can't be changed
manually. This fixes the file generator without changing the generated
header.
Missing registers must be in registers-manually-defined.json, and
missing fields must be in parse_kernel_headers.py.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
Marek Olšák [Sun, 28 Mar 2021 05:03:42 +0000 (01:03 -0400)]
amd/registers: fix the kernel header parser with latest headers
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
Chia-I Wu [Fri, 16 Apr 2021 19:43:51 +0000 (12:43 -0700)]
venus: add vn_wsi_create_scanout_image
A helper called from vn_wsi_create_scanout_image to hijack wsi scanout
image creation.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10294>
Chia-I Wu [Fri, 16 Apr 2021 19:26:21 +0000 (12:26 -0700)]
venus: add vn_image_create
A helper called from vn_CreateImage to allocate and initialize vn_image.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10294>
Chia-I Wu [Fri, 16 Apr 2021 19:22:16 +0000 (12:22 -0700)]
venus: add vn_image_init_memory_requirements
A helper called from vn_CreateImage to initialize memory requirements.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10294>
Eric Anholt [Fri, 9 Apr 2021 23:10:30 +0000 (16:10 -0700)]
nir: Generate load_ubo_vec4 directly for !PIPE_CAP_NATIVE_INTEGERS
The prog_to_nir->NIR-to-TGSI change ended up causing regressions on r300,
and svga against r300-class hardware, because nir_lower_uniforms_to_ubo()
introduced shifts that nir_lower_ubo_vec4() tried to reverse, but that NIR
couldn't prove are no-ops (since shifting up and back down may drop bits),
and the hardware can't do the integer ops.
Instead, make it so that nir_lower_uniforms_to_ubo can generate
nir_intrinsic_load_ubo_vec4 directly for !INTEGER hardware.
Fixes:
cf3fc79cd0ab ("st/mesa: Replace mesa_to_tgsi() with prog_to_nir() and nir_to_tgsi().")
Closes: #4602
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10194>
Eric Anholt [Mon, 12 Apr 2021 18:47:45 +0000 (11:47 -0700)]
nir_to_tgsi: Use ARL instead of UARL in the !native_integers case.
Our "integer" index is stored as a float in this case, and we just need to
use teh right opcode for loading it, which will be the only one supported
by !native_integers hardware.
Fixes:
cf3fc79cd0ab ("st/mesa: Replace mesa_to_tgsi() with prog_to_nir() and nir_to_tgsi().")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10194>
Mike Blumenkrantz [Thu, 15 Apr 2021 19:46:36 +0000 (15:46 -0400)]
zink: compare against screen batch id when determining which semaphore to use
semaphores are per-screen now, so check the screen value
Fixes:
fa36a16c684 ("zink: make timeline semaphores per-screen")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10267>
Francisco Jerez [Mon, 29 Mar 2021 19:26:41 +0000 (12:26 -0700)]
iris/gen12: Work around push constant corruption on context switch.
This has been confirmed to fix sporadic graphics corruption on Gen12
platforms for a number of workloads (including Heaven, Valley and
CS:GO among others). Corruption seems to occur during context switch
fairly consistently, but unfortunately this problem doesn't seem to be
documented. Until the hardware team comes up with a better
workaround, fix the problem by reemitting constants at the beginning
of each batch.
No corruption has been observed so far in GL due to preemption,
however this is a possibility to keep in mind, it may be necessary to
disable preemption in addition to this patch in order to fully address
this problem (see also
81201e461772a06ed2).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4412
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4454
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jesse Natalie [Tue, 13 Apr 2021 16:05:52 +0000 (09:05 -0700)]
microsoft/compiler: Propagate access when lowering SSBO loads
We'll want to preserve whether the load is accessing a read-only
SSBO or not.
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Tue, 13 Apr 2021 16:04:29 +0000 (09:04 -0700)]
microsoft/compiler: Support raw SRVs in addition to typed SRVs
These will be used for read-only SSBOs
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Tue, 13 Apr 2021 16:02:45 +0000 (09:02 -0700)]
microsoft/compiler: Store nir_shader in the ntd_context
This means we can stop passing it as a second parameter all the time
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Tue, 13 Apr 2021 16:56:05 +0000 (09:56 -0700)]
microsoft/compiler: Better support UBO/SSBO references to descriptors
Previously UBOs only supported static indices, and SSBOs only
supported dynamic indices. UBO support for descriptors was added
as an alternative to static indices, but the logic for detecting
descriptors to SSBOs couldn't just differentiate on constants vs not.
Add a helper which can differentiate cleanly across the board and
handle pre-created handles from descriptors, or static/dynamic raw
indices.
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Fri, 9 Apr 2021 21:54:18 +0000 (14:54 -0700)]
microsoft/compiler: Split Vulkan resource_index / descriptor processing
Instead of doing all of the handle logic in the descriptor load, split
it so that the resource index is actually computed during resource_index
processing, and it's converted to a handle during the load_descriptor.
At the same time, add SSBO handling and dynamic indexing handling.
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Fri, 9 Apr 2021 21:42:27 +0000 (14:42 -0700)]
microsoft/compiler: Emit SSBO variables
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Fri, 9 Apr 2021 21:39:44 +0000 (14:39 -0700)]
microsoft/compiler: Emit CBVs via variables for Vulkan
The resources need to be emitted in a particular order, so CBVs
have to be emitted first and can't be emitted as we iterate through
instructions.
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Fri, 9 Apr 2021 21:10:29 +0000 (14:10 -0700)]
microsoft/compiler: Support arrays of UBOs
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Fri, 9 Apr 2021 20:43:25 +0000 (13:43 -0700)]
microsoft/compiler: Support raw SRVs/UAVs through dxil_module_get_res_type
Switch the OpenCL "globals" array to use that helper
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Fri, 9 Apr 2021 21:59:59 +0000 (14:59 -0700)]
microsoft/spirv_to_dxil: Lower loads/stores to DXIL
This adjusts UBO loads to be float4 loads, and handles SSBO accesses
that are larger/smaller than 32bit.
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Jesse Natalie [Fri, 9 Apr 2021 20:40:25 +0000 (13:40 -0700)]
microsoft/spirv_to_dxil: Lower samplers from deref to index
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10149>
Mauro Rossi [Thu, 15 Apr 2021 19:34:12 +0000 (21:34 +0200)]
egl/android: include "util/compiler.h" for FALLTHROUGH macro
Fixes the following building error:
external/mesa/src/egl/drivers/dri2/platform_android.c:1263:10: error: use of undeclared identifier 'FALLTHROUGH'
FALLTHROUGH; /* for pbuffers */
^
1 error generated.
Fixes:
2928c21eb73b ("Convert most remaining free-form fall-through comments to FALLTHROUGH")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10264>
Axel Davy [Thu, 15 Apr 2021 19:59:18 +0000 (21:59 +0200)]
st/nine: Fix compilation error on non-x86 platforms
The unused variable was improperly declared.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4647
Fixes:
d9e79bfe4f ("st/nine: Disable fpu exceptions during init")
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10263>
Michel Dänzer [Fri, 16 Apr 2021 08:49:34 +0000 (10:49 +0200)]
ci: Add test which occasionally times out to lavapipe-vk skips
E.g. https://gitlab.freedesktop.org/mesa/mesa/-/jobs/8912925 .
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10279>
Simon Ser [Thu, 8 Apr 2021 12:10:55 +0000 (14:10 +0200)]
frontends/va: improve surface attribs processing
Instead of checking whether the attribute is settable for each
attrib type, check that once at the beginning of the loop.
Instead of having an if for each attrib type, use a switch.
Return an error if we encounter an unknown attribute. This allows
the caller to make sure settable attributes aren't ignored. The
intel media driver seems to just assert [1] that it doesn't encounter
unknown attributes.
[1]: https://github.com/intel/media-driver/blob/
95d413e519a980f6a7178880ccbfedace092316c/media_driver/linux/common/ddi/media_libva.cpp#L2530
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10104>
Iago Toral Quiroga [Fri, 16 Apr 2021 10:50:00 +0000 (12:50 +0200)]
v3dv: better tracking of dirty push constant state
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10283>
Iago Toral Quiroga [Fri, 16 Apr 2021 10:25:29 +0000 (12:25 +0200)]
v3dv: dirty viewport doesn't affect fragment shaders
The uniform state for the viewport is only used with geometry stages.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10283>
Iago Toral Quiroga [Fri, 16 Apr 2021 08:14:23 +0000 (10:14 +0200)]
v3dv: improve dirty descriptor set state tracking
We were using the pipeline layout to discard uniform updates for
stages that don't use descriptors, but we can do better by keeping
track of the stages used by the specific dirty descriptor sets and
only update uniforms for stages that are included in those.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10283>
Lionel Landwerlin [Tue, 13 Apr 2021 14:53:18 +0000 (17:53 +0300)]
anv: disable baked in pipeline bits from dynamic emission path
In
27ee40f4c9d86e ("anv: Add support for sample locations") we
introduced the ability to emit sample locations baked in as part of
the pipeline or dynamically.
This is different from the previous dynamic states that were always
removed from the pipeline batch and instead emitted dynamically all
the time.
The mistake in
27ee40f4c9d86e is that sample locations are now emitted
all the time, leading to bigger command buffers for unnecessary
reasons.
This change introduces a bit fields of what is baked in the pipeline
and doesn't need to be dynamically emitted.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
4ad4cd89069bfc ("anv: Enabled the VK_EXT_sample_locations extension")
Cc: <mesa-stable>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10282>
Lionel Landwerlin [Fri, 16 Apr 2021 08:08:46 +0000 (11:08 +0300)]
anv: fix 3DSTATE_MULTISAMPLE emission on gen8+
When pipeline->dynamic_state.sample_locations.samples is not set
because the state is dynamic, we're currently calling
genX(emit_multisample) with a 0 samples value which is incorrect.
Found when using renderdoc with the drawing overlay.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
4ad4cd89069bfc ("anv: Enabled the VK_EXT_sample_locations extension")
Cc: <mesa-stable>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10282>
Juan A. Suarez Romero [Fri, 16 Apr 2021 08:21:20 +0000 (10:21 +0200)]
v3dv: avoid dereferencing null value
Fixes CID#1468079 "Dereference null return value (NULL_RETURNS)"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10280>
Rhys Perry [Fri, 9 Apr 2021 15:14:50 +0000 (16:14 +0100)]
radv: fix clearing DCC-compressed e5b9g9r9 images
Fixes
dEQP-VK.api.image_clearing.core.clear_color_image.2d.optimal.single_layer.e5b9g9r9_ufloat_pack32_33x128
with RADV_DEBUG=forcecompress on GFX10.3.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 21.1 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10176>
Adam Jackson [Tue, 13 Apr 2021 22:58:54 +0000 (18:58 -0400)]
glx: Remove some ancient backwards-compatibility typedefs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 22:54:00 +0000 (18:54 -0400)]
glx: Fold client_gl_only array into its one real user
The initialization we're doing for it in __glXExtensionsCtr is trivial,
and this is only to make glGetString(GL_EXTENSIONS) work in indirect
contexts anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 22:40:51 +0000 (18:40 -0400)]
glx: Enable pure-client-library extensions explicitly
These are rare enough to not be worth tracking separately. Especially
since after this change all the known_gl_extensions have N for both
direct_support and direct_only (unsurprising, since that's only used to
compute usable indirect extensions).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 21:12:09 +0000 (17:12 -0400)]
glx: Remove redundant client_support field from extension table
It's always true, simplify accordingly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 21:35:49 +0000 (17:35 -0400)]
glx: Generalize __glXGetStringFromTable a little
Make the second argument optional, and treat its absence as if the
filter always matches.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 21:06:50 +0000 (17:06 -0400)]
glx: Remove some non-functional GL extension from the table
We don't actually have GLX protocol for these in Mesa, hence the initial
N column.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 20:54:31 +0000 (16:54 -0400)]
glx: Mark GLX_{ATI_pixel_format_float,NV_float_buffer} as supported
... at least as far as libGL is concerned, because they'd work just fine
if you tried. The only thing the ATI extension seems to add (I can't
find an official spec, this is inferred from the registry XML) is
selecting the GLX_RENDER_TYPE, which we don't validate before putting on
the wire. The only thing the NV extension adds is an additional fbconfig
attribute, and that only known by glXGetFBConfigAttrib; our
implementation of that just reads the value the server sends, if any,
and doesn't try to filter out unknown attributes.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 20:31:24 +0000 (16:31 -0400)]
glx: Remove major/minor version tracking from extension table
With the previous ancient dead code removed, there's no longer anything
using these values.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 20:21:09 +0000 (16:21 -0400)]
glx: Remove some truly ancient unused code
The "left here but disabled" comment dates to 2004! The idea here is to
add extensions implied by a particular GL version to the GL extension
string, but nothing useful is accomplished by doing so, and this is all
only used in the case of indirect rendering anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Adam Jackson [Tue, 13 Apr 2021 20:01:38 +0000 (16:01 -0400)]
glx: Remove silly __glXGetGLVersion() indirection
Hardcode the values at the one caller that uses them.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10223>
Samuel Pitoiset [Mon, 12 Apr 2021 07:24:46 +0000 (09:24 +0200)]
radv: keep DCC compressed for clears on compute with image stores
Without image stores, DCC is always decompressed on compute.
Cc: 21.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10168>
Marek Olšák [Wed, 14 Apr 2021 01:37:40 +0000 (21:37 -0400)]
amd: remove some references to older LLVM versions in comments
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Marek Olšák [Sat, 27 Mar 2021 09:38:57 +0000 (05:38 -0400)]
amd: drop support for LLVM 10
It doesn't support RDNA 2.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Marek Olšák [Sat, 27 Mar 2021 09:34:16 +0000 (05:34 -0400)]
amd: drop support for LLVM 9
This would be easy to support except that it doesn't support RDNA 2.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Samuel Pitoiset [Thu, 30 Jan 2020 10:02:00 +0000 (11:02 +0100)]
amd: drop support for LLVM 8
It doesn't support Navi1x and the removal enables this nice code cleanup.
v2: rebase - mareko
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Marek Olšák [Wed, 14 Apr 2021 19:46:15 +0000 (15:46 -0400)]
ci: don't build clover with LLVM 9 on radeonsi because it's unsupported
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10199>
Matt Turner [Tue, 6 Apr 2021 20:14:26 +0000 (13:14 -0700)]
intel/eu: Add instruction compaction support on XeHP.
This patch includes a number of reworks and fixes squashed in by
Nanley Chery, Sagar Ghuge, Jordan Justen and Francisco Jerez.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Tue, 6 Apr 2021 20:11:33 +0000 (13:11 -0700)]
intel/fs: Add more efficient fragment coordinate calculation.
The PIXEL_X/Y opcodes used by the current implementation are broken on
XeHP due to the new regioning restrictions of the floating-point pipe.
We could have the regioning lowering pass fix it in theory by lowering
the conversions into separate MOV instructions, but that would be more
costly than this implementation that only needs a pair of pipelined
ADDs and a pair of pipelined MOVs.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 11 Jan 2019 04:23:53 +0000 (20:23 -0800)]
intel/fs: Introduce lowering pass to implement derivatives in terms of quad swizzles.
Unfortunately the funky Align1 regions used by the code generator in
order to implement derivatives efficiently aren't available to the
floating-point pipeline on XeHP. We need to lower them into a number
of pipelined integer shuffle instructions followed by the
floating-point difference computation.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Fri, 21 Dec 2018 10:21:57 +0000 (02:21 -0800)]
intel/compiler: Lower txd for 3D samplers on XeHP.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Mon, 6 Jan 2020 10:16:57 +0000 (02:16 -0800)]
intel/fs: End computer shader with message gateway on XeHP.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Tue, 6 Apr 2021 20:11:09 +0000 (13:11 -0700)]
intel/fs: Disable 3-src immediates on XeHP.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
[ Francisco Jerez: Add TODO comment explaining why this is helpful and
how we could better fix it. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Tue, 6 Apr 2021 20:10:29 +0000 (13:10 -0700)]
intel/eu: Allow 64-bit registers on XeHP.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Mon, 19 Nov 2018 22:54:43 +0000 (14:54 -0800)]
intel/compiler: Lower integer division on XeHP.
It has been removed from the hardware.
[jordan.l.justen@intel.com: Move to brw_postprocess_nir]
v2: Switch to nir_lower_idiv_precise (Rhys).
v3: Fix for interface changes of nir_lower_idiv.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Rafael Antognolli [Wed, 30 Jan 2019 00:34:30 +0000 (16:34 -0800)]
intel/fs: Lower dword integer multiplies on XeHP.
From the BSpec:
"When multiplying DW X DW, resulting dst can only be QW precision. If
DW precision is required at output than MUL/MACH macro must be used."
So for now simply lower it. We might want to revisit it later.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Tue, 6 Apr 2021 20:05:30 +0000 (13:05 -0700)]
intel/eu: Teach EU validator about FP/DP pipeline regioning restrictions.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Tue, 6 Apr 2021 20:04:26 +0000 (13:04 -0700)]
intel/fs: Handle regioning restrictions of split FP/DP pipelines.
The floating-point and double-precision FPU pipelines of XeHP
platforms don't support arbitrary regioning modes, corresponding
channels of sources and destination are required to be aligned to the
same sub-register offset, similar to the restriction FP64 instructions
had on CHV/BXT platforms.
Most violations of this restriction can be fixed easily by teaching
has_dst_aligned_region_restriction() about the change so the regioning
lowering pass gets rid of any unsupported regioning. For cases where
this is not sufficient (e.g. because a virtual instruction internally
uses some regioning mode not supported by the floating-point pipeline)
the regioning lowering pass is extended with an additional
lower_exec_type() codepath that bit-casts sources and destination to
an integer type whenever the execution type is not supported by the
instruction.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 7 Dec 2018 22:15:03 +0000 (14:15 -0800)]
intel/fs: Fix repclear assembly for XeHP+ regioning restrictions.
The regioning mode used here is no longer supported by the
floating-point pipeline. We could run the regioning lowering pass in
order to fix it with some extra copies, but it's more efficient to
change the instruction to use integer types.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 7 Dec 2018 22:27:24 +0000 (14:27 -0800)]
intel/fs: Use CHV/BXT implementation of 64-bit MOV_INDIRECT on XeHP+.
According to the hardware spec "Vx1 and VxH indirect addressing for
Float, Half-Float, Double-Float and Quad-Word data must not be used."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 19 Feb 2021 07:45:13 +0000 (23:45 -0800)]
intel/fs: Calculate SWSB cross-pipeline synchronization information.
In combination with the previous changes we can just check whether an
instruction has any potentially unsatisfied dependencies on more than
one pipeline, and if so use TGL_PIPE_ALL synchronization with an
appropriate RegDist counter, otherwise synchronize with the single
pipeline it has a dependency on, if any.
Only minor difficulty is caused by the fact that the hardware doesn't
have any way to encode pipeline information when a RegDist and an SBID
dependency need to be provided simultaneously, in which case the
synchronization pipeline is inferred by the hardware. We need to
verify that the hardware's inference will give the correct result
(which may not be the case if e.g. some data was bit-cast from a
different type), and if not emit separate SYNC instructions instead of
baking the RegDist dependency into the instruction (Note that SET SBID
dependencies must always be baked into the corresponding out-of-order
instruction).
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 19 Feb 2021 07:26:57 +0000 (23:26 -0800)]
intel/fs: Represent SWSB in-order dependency addresses as vectors.
This extends the current ordered_address instruction counter to a
vector with one component per asynchronous ALU pipeline, allowing us
to track the last instruction that accessed a register separately for
each ALU pipeline of the XeHP EU, making it straightforward to
infer the right cross-pipeline synchronization annotations.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
v2: Make unit tests happy (with ubsan as run by GitLab automation).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Jordan Justen [Fri, 17 Apr 2020 22:31:18 +0000 (15:31 -0700)]
Revert "intel/compiler: Silence unused parameter warning in update_inst_scoreboard"
This was a placeholder for the XeHP cross-pipeline synchronization
code, bring it back.
This reverts commit
a80e44902f66244d257c523afe77558cf334d624.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Fri, 19 Feb 2021 07:10:38 +0000 (23:10 -0800)]
intel/fs: Add helper functions inferring sync and exec pipeline of an instruction.
Define two helper functions local to the software scoreboard lowering
pass describing the behavior of the hardware and code generator:
inferred_sync_pipe() calculates the ALU pipeline the hardware will
implicitly synchronize with when a RegDist SWSB annotation is used
without providing explicit pipeline synchronization information,
inferred_exec_pipe() infers the ALU pipeline that will execute the
instruction.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Francisco Jerez [Tue, 6 Apr 2021 20:03:45 +0000 (13:03 -0700)]
intel/fs: Implement representation of SWSB cross-pipeline synchronization annotations.
The execution units of XeHP platforms have multiple asynchronous ALU
pipelines instead of (as far as software is concerned) the single
in-order pipeline that handled most ALU instructions except for
extended math in the original Xe. It's now the compiler's
responsibility to identify cross-pipeline dependencies and insert
synchronization annotations whenever necessary, which are encoded as
some additional bits of the SWSB instruction field.
This commit represents the cross-pipeline synchronization annotations
as part of the existing tgl_swsb structure used for codegen. The
existing tgl_swsb_*() helpers used by hand-crafted assembly are
extended to default to TGL_PIPE_ALL big-hammer synchronization in
order to ensure backwards compatibility with the existing assembly.
The following commits will extend the software scoreboard lowering
pass in order to keep track of cross-pipeline dependencies across IR
instructions, and insert more specific pipeline annotations in the
SWSB field.
The disassembler is also extended here to print out any existing
pipeline sync annotations.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
Adam Jackson [Tue, 23 Feb 2021 20:28:40 +0000 (15:28 -0500)]
glx/drisw: Enable GLX_ARB_create_context_no_error
Detect this the same way as we do for drihw.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9233>
Iago Toral Quiroga [Thu, 15 Apr 2021 11:47:58 +0000 (13:47 +0200)]
v3dv: fix sRGB blending workaround
This workaround needs to set a flag in the current job but it was
implemented at pipeline binding time, which can happen outside a
render pass. Move it to the pre-draw handler, where it belongs.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4645
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10255>
Christian Gmeiner [Sun, 4 Apr 2021 10:30:16 +0000 (12:30 +0200)]
ci: disable initrd support
For baremetal CI we are using a 'dummy' rootfs as it is required by
abootimg. This causes NFS boot problems when using u-boot as bootloader.
[ 13.230968] RAMDISK: gzip image found at block 0
[ 13.235645] using deprecated initrd support, will be removed in 2021.
[ 13.243106] List of all partitions:
If we disable CONFIG_BLK_DEV_INITRD nfsroot works.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10024>