radeonsi: don't read tcs_out_lds_layout.vertex_size from an SGPR

TCS outputs are usually not written to LDS, so no stats here.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't read LS out vertex stride from an SGPR in monolithic HS

-44 bytes in a monolithic LS-HS binary.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't read the LS output vertex stride from an SGPR in LS

Now it's able to generate ds_write2_b64 instead of ds_write2_b32.

-20 bytes in one shader binary. (having only 1 output)

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't read the number of TCS out vertices from an SGPR in TCS

-16 bytes in one shader binary.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't always apply the PrimID instancing bug workaround on SI

It looks like commit 391673af7ad1565a5f6ac8fc2f8c9fcdd1fe9908 that should
have fixed the perf regression didn't really change much if anything.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove 2 callbacks from si_shader_context

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: disable local BOs on Raven

It hangs with a high degree of reproducibility.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

disk_cache: make the thread queue resizable and low priority

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

loader/dri3: Make sure we invalidate a drawable on size change

If we're seeing a drawable size change, in particular after processing a
configure notify event, make sure we invalidate so that the state tracker
picks up the new geometry.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

loader/dri3: Process event after each fence wait

This tries to mimic dri2 behaviour where events are typically processed
while waiting for X replies. Since, during steady-state dri3 rendering, we
seldom wait for xcb replies, and haven't enabled any automatic event
processing, instead check for events after a fence wait.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

st/mesa: skip draw calls with pipe_draw_info::count == 0

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102502

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>

docs: update envvar docs to reflect MESA_NO_ERROR change

I changed the behaviour earlier today, but forgot to update the
corresponding docs.

Fixes: 77713a0acb09f475d29f "mesa: allow user to set MESA_NO_ERROR=0"
Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>

radv: do not use a bitfield when dirtying the vertex buffers

Useless to track which one has been updated because we
re-upload all the vertex buffers in one shot.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove unused radv_meta_saved_state::vertex_saved field

It's always false.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

mesa: allow user to set MESA_NO_ERROR=0

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102530
Cc: Michel Dänzer <michel@daenzer.net>
Cc: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

util: rename include guard to avoid clash

src/mesa/main/debug.h uses the same include guard.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

llvmpipe, tgsi: hook up dx10 gather4 opcode

Trivial. We already support tg4 for legacy tex opcodes, so the actual
texture sampling code already handles it.
(Just like TG4, we don't handle additional capabilities and always sample
red channel.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

llvmpipe, draw: increase shader cache limits

We're not particularly concerned with memory usage, if the tradeoff is
shader recompiles. And it's common for apps to have a lot of shaders
nowadays (and, since our shaders include a LOT of context state of course
we may create quite a bit more shaders even).
So quadruple the amount of shaders draw will cache (from 128 to 512).
For llvmpipe (fs shaders) quadruple the number of instructions, keep the
number of variants the same for now (only with very simple, non-texturing
shaders the variant limit could really be reached), and simplify the
definition, it's probably easier to just have one different definition
per branch...

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

ac/surface: reduce gfx9_surface_layout size.

152->144.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: reduce radv_amdgpu_winsys struct size.

1168->1160.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: reduce radv_image struct size.

1480->1472.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: reduce radv_shader_variant struct size.

544->536

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: reduce radv_cmd_state struct size.

1632->1624.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: reduce meta_saved_state struct size.

904->896.

Signed-off-by: Dave Airlie <airlied@redhat.com>

nir: put compact into bitfields in nir_variable_data

This being declared bool means it won't get merged with the previous
bitfields, this seems like an oversight rather than deliberate.

Noticed when running pahole.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

anv: Annotate entrypoint table with index and func name

This helps when debugging a broken entrypoint table.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeon/uvd: fix the assertion check for YUYV format

Fixes:7319ff87("radeon/uvd: add YUYV format support for target buffer")

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

intel: Add brand string for KBL-R

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel: Remove unused device info for KBL GT1.5

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel: Change a KBL pci id to GT2 from GT1.5

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel: Fix few KBL brand strings

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel: Remove unused Kabylake pci ids

These PCI IDs are not used in any Kabylake SKUs.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

Revert "Android: add -Wno-date-time flag for clang"

This reverts commit 6dae9176d60d12de61aa03906c44f81e20ef7622.

No longer needed as of last commit.

Cc: Rob Herring <robh@kernel.org>

mesa: replace date/time macros with MESA_GIT_SHA1

Former is non-deterministic, results in non-reproducible builds and
compilers throw a warning about it.

Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mesa: don't use %s for PACKAGE_VERSION macro

The macro itself is a well defined string, which cannot cause issues
with printf or other printf-like functions.

All other places through Mesa already use it directly, so let's update
the final two instances.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

docs/release-calendar: update and extend

v2: Correct 17.1.10 version, adjust some names.
v3: Add missing <tr> (Andres)

Cc: Juan A. Suárez <jasuarez@igalia.com>
Cc: Andres Gomez <agomez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)

docs/releasing: polish LLVM_CONFIG wording/handling

Use consistent way to manage "non-default" llvm installations, clearly
documenting it.

AKA, use LLVM_CONFIG throughout and unset for the Windows/mingw builds.

v2: unset the save_ variable (Andres)

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)

docs/releasing: remove -jX instances

One can control the number of jobs via MAKEFLAGS. As such there's
little reason to set the number of jobs for each make invocation.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

.gitignore: list *.orig and *.rej

Should prevent accidental check-in of patch artefacts.

Suggested-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>

egl/x11: advertise __DRI_USE_INVALIDATE for DRI2

Back in 2012 (commit 1e7776ca2bc - egl: Remove bogus invalidate code.)
the loader use of invalidate() was purged as "bogus". One of the factors
defining that statement was the lack of the loader-side invalidate
extension - __DRI_USE_INVALIDATE.

Since then the commit was reverted (commit eed0a80137d - egl: Restore
"bogus" DRI2 invalidate event code.), always performing the driver
invalidate call, although the loader was never updated to expose the
extension.

Do so allowing the driver to do fine grained tuning.

Cc: Eric Anholt <eric@anholt.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net

egl/x11/dri3: adding missing __DRI_BACKGROUND_CALLABLE extension

Fixes: 3b7b6adf3ac ("egl: Implement __DRI_BACKGROUND_CALLABLE")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: expose RGBA visuals only on Android

As Marek pointed out in earlier commit - exposing RGBA on other
platforms introduces ~500 Visuals, which are not tested.

Note that this does not quite happen, yet. Reason being that the GLX
code does not check the masks - see scaralEqual().

Thus as we fix that, we'll run into the issue described.

v2: Rebase, while keeping loaderPrivate
v3: Beef-up commit message, getCapability() returns unsigned (Tapani)

Fixes: 1bf703e4ea5 ("dri_interface,egl,gallium: only expose RGBA visuals
on Android")
Cc: Tomasz Figa <tfiga@chromium.org>
Cc: Chad Versace <chadversary@chromium.org>
Cc: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

swr/rast: FE/Clipper - unify SIMD8/16 functions using simdlib types

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Remove use of C++14 template variable

SWR rasterizer must remain C++11 compliant.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 FE remove templated immediates workaround

Fixed properly in gcc-compatible fashion.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: SIMD16 PA - rename Assemble_simd16 to Assemble

For consistency and to support overloading.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: FE/Binner - unify SIMD8/16 functions using simdlib types

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Removed some trailing whitespace caught during review

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: set caps for VB 4-byte alignment

Needed to compensate for change to fetch jit requiring
alignment.

Fixes regressions in piglit: vertex-buffer-offsets and about
another hundred of the vs-input*byte* tests.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Allow gather of floats from fetch shader with 2-4GB offsets

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

radv: fix error code when resizing the upload BO

malloc() failures are unrelated to the device memory.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

mesa/st/st_glsl_to_tgsi_temprename.cpp: Fix compilation with MSVC

If <windows.h> is included then max is a macro that clashes
with std::numeric_limits::max, hence undefine it.
For some reason the struct access_record is not recognizes
outside the anonymouse namespace, make it a class.
The patch successfully was tested on AppVeyor.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/st: glsl_to_tgsi: tie in new temporary register merge approach

This patch replaces the old register lifetime estiamtion and
rename mapping evaluation with the new one.

Performance to compare between the current and the new implementation
were measured by running the shader-db in one thread.

-----------------------------------------------------------
                    old          new(std::sort)

---------------- time ./run -j1 shaders --------------------

  real              5.80s          5.75s
  user              5.75s          5.70s
  sys               0.05s          0.05s

---- valgrind --tool=callgrind --dump-instr=yes------------

 merge               0.08%         0.18%
 estimate lifetime   0.02%         0.11%
 evaluate mapping  (incl=0.3%)     0.04%
 apply mapping       0.03%         0.02%

---   perf (approximate because of statistic sampling) ----

merge (total)        0.09%         0.16%
estimate lifetime    0.03%         0.10%
evaluate mapping  (incl=0.02%)     0.04%
apply mapping        0.04%         0.04%

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/st: glsl_to_tgsi: Add test set for evaluation of rename mapping

The patch adds tests for the register rename mapping evaluation and
combined life time estimation and renaming.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/st: glsl_to_tgsi: add register rename mapping evaluator

The remapping evaluator first sorts the temporary registers ascending
based on their first life time instruction, and then uses a binary search
to find merge canidates.
For the initial sorting it uses std::sort because qsort is quite slow in
comparison. By removing the define USE_STL_SORT in
  src/mesa/state_tracker/st_glsl_to_tgsi_temprename.cpp
one can enable the alternative code path that uses qsort.

Registers that are not written to are not considered for renaming since in
glsl_to_tgsi_visitor::renumber_registers they are eliminated anyway.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/st: glsl_to_tgsi: add tests for the new temporary lifetime tracker

This patch adds a set of unit tests for the new lifetime tracker.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/st: glsl_to_tgsi: implement new temporary register lifetime tracker

This patch adds a class for tracking the life times of temporary registers
in the glsl to tgsi translation. The algorithm runs in three steps:
First, in order to minimize the number of needed memory allocations the
program is scanned to evaluate the number of scopes.
Then, the program is scanned  second time to record the important register
access time points: first and last reads and writes and their link to the
execution scope (loop, if/else branch, switch case).
In the third step for each register the actual minimal life time is
evaluated.

In addition, when compiled in debug mode (i.e. NDEBUG is not defined)
the shaders and estimated temporary life times can be logged to stderr
by setting the environment variable GLSL_TO_TGSI_RENAME_DEBUG.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/st: glsl_to_tgsi move some helper classes to extra files

To prepare the implementation of a temp register lifetime tracker
some of the classes are moved into seperate header/implementation
files to make them accessible from other files.

Specifically these are:

    class st_src_reg;
    class st_dst_reg;
    class glsl_to_tgsi_instruction;
    struct rename_reg_pair;

    int swizzle_for_type(const glsl_type *type, int component);

  as inline:

    bool is_resource_instruction(unsigned opcode);
    unsigned num_inst_dst_regs(const glsl_to_tgsi_instruction *op);
    unsigned num_inst_src_regs(const glsl_to_tgsi_instruction *op);

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st_glsl_to_tgsi: rewrite rename registers to use array fully.

Instead of having to search the whole array, just use the whole
thing and store a valid bit in there with the rename.

Removes this from the profile on some of the fp64 tests

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug

When the HS wave is empty, the hardware writes the LS VGPRs starting at
v0 instead of v2. Workaround by shifting them back into place when
necessary. For simplicity, this is always done in the LS prolog.

According to the hardware team, this will be fixed in future chips,
so take that into account already.

Note that this is not a bug fix, as the bug was already worked
around by commit 166823bfd26 ("radeonsi/gfx9: add a temporary workaround
for a tessellation driver bug"). This change merely replaces the
workaround by one that should be better.

v2: add workaround code to shader only when necessary
v3: clarify the prefer_mono comment

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/debug: take ASIC generation into account when printing registers

There were some overlapping changes in gfx9 especially in the CB/DB
blocks which made register dumps rather misleading.

The split is along the lines of the header files, so we'll print VI-only
fields on SI and CI, for example, but we won't print GFX9 fields on
SI/CI/VI, and we won't print SI/CI/VI fields on GFX9.

Acked-by: Marek Olšák <marek.olsak@amd.com>

amd/common: pass chip_class to ac_dump_reg

Acked-by: Marek Olšák <marek.olsak@amd.com>

ac/sid_tables: add FieldTable object

Automatically re-use table entries like StringTable and IntTable do.
This allows us to get rid of the "fields_owner" logic, and simplifies
the next change.

Acked-by: Marek Olšák <marek.olsak@amd.com>

ac/sid_tables: remove unused variable varname_values

Acked-by: Marek Olšák <marek.olsak@amd.com>

radeonsi/gfx9: always flush DB metadata on framebuffer changes

This fixes GL45-CTS.shader_image_load_store.basic-glsl-earlyFragTests.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

util/ralloc: set prev-pointers correctly in ralloc_adopt

Found by inspection.

I'm not aware of any actual failures caused by this, but a precise
sequence of ralloc_adopt and ralloc_free should be able to cause
problems.

v2: make the code slightly clearer (Eric)

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mesa/main: Fix GetTextureImage error reporting

GetTex*Image should return INVALID_ENUM if target is not valid, however,
GetTextureImage does not receive a target, and instead should return
INVALID_OPERATION if the effective target is not valid. From the
OpenGL 4.6 core profile spec, section 8.11 Texture Queries:

"An INVALID_OPERATION error is generated by GetTextureImage if the effective
 target is not one of TEXTURE_1D, TEXTURE_2D, TEXTURE_3D, TEXTURE_1D_ARRAY,
 TEXTURE_2D_ARRAY, TEXTURE_CUBE_MAP_ARRAY, TEXTURE_RECTANGLE, or
 TEXTURE_CUBE_MAP (for GetTextureImage only)."

Fixes:
KHR-GL45.direct_state_access.textures_image_query_errors

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

egl: remove unused 'Screens' array from _egl_display

This was used by EGL_MESA_screen_surface that has been removed
in commit 7a58262e58d8edac3308777def0950032628edee.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <eml.velikov@collabora.com>

Revert "radv: disable support for VEGA for now."

This reverts commit 611076a41aac3095a82dff2432943d7f8d429822.

With the two previous commits, vega shouldn't be unstable,
doesn't pass CTS, but can do a complete run, and games shouldn't
hang anymore, so bring it back online.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: set descriptor up for base_mip to level range.

This is required on GFX9, fixes a bug in Talos where all the
mipmaps overlay each other.

Just pushing this as well as it fixes Talos.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: disable 1d/2d linear optimisation on gfx9.

This causes hangs in some of the CTS tests with a 2d
1536x2 texture.

This fixes hangs with:
dEQP-VK.pipeline.image.suballocation.sampling_type.combined.iew_type.1d_aray.format.r4g4b4a4_unorm_pack16.count_1.size.512x1_array_of_3
if we reenable it, make sure these don't regress.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: fix buffer size on gfx9.

The VI sizing only applies to VI.

This fixes:
dEQP-VK.image.image_size.buffer.*

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Fix vkCopyImage with both depth and stencil aspects.

Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>

mesa/mtypes: repack gl_sampler_object.

160->152.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/mtypes: repack gl_texture_object.

reduces size from 1144 to 1128.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/mtypes: repack gl_shader_program_data.

This reduces the size from 144 bytes to 128 bytes.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/mtypes: reorganise gl_shader

This reduces this from 200->182 bytes.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/mtypes: repack display list structs.

This reduces each of these by 8 bytes.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/mtypes: reduce size of gl_sync_object.

Drops from 40->32 bytes.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/mtypes: reorg vertex/fragment program state.

reduces both of these by 8 bytes.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/bindless: reorder gl_bindless_image gl_bindless_sampler.

This makes these use 16-bytes instead of 24-bytes.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: fix a memleak when compiling the GS copy shader

Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

svga: move index buffer bind flag assertion

The buffer bind flags can be promoted in svga_buffer_handle(), so
move the assertion after it. This has already been done for
vertex buffer in commit 6b4bf7e8be, but it misses the one for
index buffer.

Fixes assertion running WarThunder.

Reviewed-by: Neha Bhende <bhenden@vmware.com>

svga: avoid emitting redundant SetShaderResources and SetVertexBuffers

Minor performance improvement in avoiding binding the same shader resource
or the same vertex buffer for the same slot.

Tested with MTT glretrace.

v2: Per Brian's suggestion, add a helper function to do vertex buffer
    comparision.
v3: Change the helper function to vertex_buffers_equal().

Reviewed-by: Brian Paul <brianp@vmware.com>

spirv: Add support for the HelperInvocation builtin

I have no idea how this got missed but it's been missing since forever.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

loader/dri3: Use client local back to front blit in copySubBuffer if available

The copySubBuffer functionality always attempted a server side blit from
back to fake front if a fake front was present, and we weren't displaying
on a remote GPU.

Now that we always have local blit capability on modern drivers, first
attempt a local blit, and only if that fails, try the server blit.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Axel Davy <axel.davy@normalesup.org>

radeonsi/gfx9: implement primitive binning

This increases performance, but it was tuned for Raven, not Vega.
We don't know yet how Vega will perform, hopefully not worse.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add more state flags into si_state_dsa

3 flags for primitive binning, 2 flags for out-of-order rasterization
(but that will be done some other time)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't use BREAK_BATCH and FLUSH_DFSM if DFSM is disabled

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

vbo: fix build errors on android

incompatible pointer to integer conversion assigning to 'GLintptr' (aka 'int')
from 'const char *' [-Werror,-Wint-conversion]

      offset = indices;
             ^ ~~~~~~~

Fixes: 2d93b462b4d ("vbo: fix offset in minmax cache key")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

docs: add news item and link release notes for 17.2.0

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 17.2.0

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit b4473dd5191878249ccb53f40407206f1e57fa6f)

docs: Update 17.2.0 release notes

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit f5925b2897308530c64e1abf44ebc1ee0e017ada)

radeonsi: eliminate PS color outputs when colormask kills them

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: sort DBG shader flags according to pipe_shader_type

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: ensure cache flushes happen before SET_PREDICATION packets

The data is read when the render_cond_atom is emitted, so we must
delay emitting the atom until after the flush.

Fixes: 0fe0320dc074 ("radeonsi: use optimal packet order when doing a pipeline sync")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix ARB_transform_feedback_overflow_query on <= VI

The result written by the shader workaround needs to be written back, or
the CP may read stale data.

Fixes: 78476cfe071a ("radeonsi: enable ARB_transform_feedback_overflow_query")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix compute shader state dumping

Fixes: 420c438589c8 ("radeonsi: log draw and compute state into log context")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: add an assertion that only two-dimensional constant references are used

v2: remove some redundant checks

Acked-by: Roland Scheidegger <sroland@vmware.com> (v1)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> (v1)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

gallium/radeon: always use two-dimensional constant references

Acked-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>