glsl: stop adding pointers from glsl_struct_field to the cache

This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

glsl: stop adding pointers from gl_shader_variable to the cache

This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

glsl: allow NULL to be passed to encode_type_to_blob()

This will be used by the following commit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv/gfx9: don't expose linear depth on vega.

This just zeros out the linear flags for gfx9 + depth formats.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: don't degrade tiling mode for small compressed or depth texture.

This is what radeonsi does, so we should do the same, also vega
doesn't support linear depth textures anyways.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: only minify image view width/height/depth before gfx9.

For gfx9 the addressing for images has changed, so we need to
provide the hw with the level0, however we still need to scale
for format block differences (so our compressed upload paths still
work).

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/image: don't rescale width/height if the format isn't changing

If the image view has the same format, we don't need to rescale
the w/h.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: cleanup some image view descriptor setup.

Avoid passing the vulkan image creation into the image view descriptor
setup. This cleans up the usage of range inside the init, instead
using the properly inited values in the image view.

This is just a cleanup but some future vega changes will depend on it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: emit sx_mrt_blend registers

GFX9 needs the SX MRT blend registers programmed, port over
the code from radeonsi to workout the values from the blend
state, and program the registers on rbplus systems.

This fixes lots of:
dEQP-VK.pipeline.blend.*

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: bump space check for indexed draw.

For the GFX9 packet we need one more dword.

Fixes an assert in:
dEQP-VK.draw.shader_draw_parameters.base_vertex.draw_indexed

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: fixup db/stencil disable.

This fixes disabled Z/stencil.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: fix level count in color register setup.

There was an off by one here.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: use total levels in texture descriptor

We need to use all the levels when filling out the gfx9
descriptor.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Implement bc optimize.

Seems like we actually enabled it already, but did not implement
the shader part. With this patch we do.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: refactor input variable iteration.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

i965: Stop using wm_prog_data->binding_table.render_target_start.

Render target surfaces always start at binding table index 0.
This is required for us to use headerless FB writes, which we
really want to do.  So, we'll never change that.

Given that, it's not necessary to look up a wm_prog_data field
which we already know contains 0.  We can drop the dependency in
brw_renderbuffer_surfaces (Gen4-5)...which was already confusingly
missing from gen6_renderbuffer_surfaces.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Add a brw_wm_prog_data::has_render_target_reads field.

State upload code should use prog_data rather than poking at shader_info
directly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Inline brw_update_renderbuffer_surfaces().

Less baklava layers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Pass fb into emit_null_surface instead of dimensions.

We either want the framebuffer dimensions or 1x1x1.  Passing fb and
falling back to 1x1x1 lets us shorten some calls.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Devirtualize update_renderbuffer_surface.

Replace piles of my own boilerplate with 1-2 lines of code.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Delete update_renderbuffer_surface flags.

We don't need yet another set of flags.  The function already has access
to both brw and the unit, so it can check brw->draw_aux_buffer_disabled
itself in one line of code.  The layered flag was only used to assert
that Gen4-5 doesn't do layered rendering, which isn't that useful.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Make brw_update_renderbuffer_surface static.

Also rename it to gen6_update_renderbuffer_surface, as this is the
function for Gen6+.  Having functions named "brw_*" and "gen4_*"
is confusing...if we're using gens, let's stick with those.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Drop BRW_NEW_BLORP from SURFACE_STATE setup code.

BLORP invalidates the binding tables, but it doesn't destroy any of the
existing SURFACE_STATE entries in the statebuffer.  We can reuse those.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit.

When changing fast clear colors, we need to emit new SURFACE_STATE
with the updated color at the next draw call.

Most things work today because the atoms that handle SURFACE_STATE
for images (mutable images, textures, render targets) also listen to
BRW_NEW_BLORP, causing us to re-emit these on every BLORP operation.
However, this is overkill - most BLORP operations don't require us
to re-emit SURFACE_STATE.

One case where this is broken today is a fast clear to a different
color followed by a non-coherent framebuffer fetch.  The renderbuffer
read atom doesn't listen to BRW_NEW_BLORP, and would not get the new
fast clear color.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Drop Gen7+ nonsense from brw_ff_gs.c.

brw_ff_gs.c is about using the geometry shader to implement things
that the fixed function ought to do, but doesn't on old hardware.

Gen7+ does not need this.  We should drop the misleading comment
about Gen7 not using geometry shaders.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

i965: Only set key->flat_shade if COL0/COL1 are written.

This may reduce some recompiles.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

i965: Clean up brwNewProgram().

All shader stages do the exact same thing, so we don't need the switch
statement, or the redundant FS case.  I believe these used to be
different before Tim eliminated the (e.g.) brw_vertex_program
subclasses.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

st/va: exclude the buffer reallocation for encode case

Since encoder only support de-interlaced buffers.

v2: move to parameter call to tell dec/enc

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

swr: limit pipe_draw_info->restart_index usage

Only copy this value when in restart drawing mode.

Eliminates valgrind errors when running trivial programs.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

radeonsi: fix wrong assertion in si_init_bindless_descriptors()

Bad mistake, sorry.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeon/video: Return false explicitly for HEVC if not the case

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/docs: Fix the math formula of U2I64

before:
  dst.xy = (uint64_t) src0.x
  dst.zw = (uint64_t) src0.y

after:
  dst.xy = (int64_t) src0.x
  dst.zw = (int64_t) src0.y

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/docs: Add missing word "Not"

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

tgsi: store opcode mnemonics in a separate table

They are only used for debug info.

Together with making tgsi_opcode_info::opcode a bitfield, this reduces
the size of tgsi_opcode_info on 64-bit systems from 24 bytes to 4 bytes,
and makes the whole data structure a bit more linker friendly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: use tgsi_get_opcode_name instead of tgsi_opcode_info::mnemonic

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

tgsi: macro-ify the opcodes table

So we can easily re-arrange members of tgsi_opcode_info, and readers of
the code don't have to guess what all the 0s mean.

Mostly done with regex search&replace.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

tgsi: remove post_indent from some 64-bit opcodes

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

tgsi: reduce tgsi_opcode_info::pre_dedent and post_indent to 1 bit

It's not clear why they were ever 2 bits to begin with. Perhaps
the original intent was to use signed values, but that doesn't
seem to have ever been the case in master.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: fix saving multi-part command streams

Use the correct type to fix pointer arithmetic.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/debug: invoke valgrind checks while parsing IBs

Help catch garbage data written into IBs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/debug: annotate IB dumps with the raw values

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/debug: use an explicit getter for fetching words from the IB

Guard against out-of-bounds accesses, and prepare for upcoming changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: update comment describing indices into sctx->descriptors

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

util: fix valgrind errors when dumping pipe_draw_info

Various index-related fields are only initialized when required, so
they should only be dumped in those cases.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: do not assert when reserving bindless slot 0

When assertions were disabled, the compiler removed
the call to util_idalloc_alloc() and the first allocated
bindless slot was 0 which is invalid per the spec.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: rename some bindless-related helper functions

I think it makes more sense.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: minor cleanups in si_make_{texture,image}_handle_resident()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Android: gallium_dri: pass dri.sym to linker

Pass the dri.sym version script to the linker. This ensures only
explicitly exported symbols are exported and shrinks the library by up
to 60KB.

HAVE_DLADDR also needs to be set so that __driDriverExtensions is defined.

We need to pass "--undefined-version" because the Android build system
sets --no-undefined-version by default and we get an error on
driver specific symbols if those drivers are disabled without the option.

Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>

st/va: enable P016 format i.e. reallocate buffer if format changed

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: enable P016 mode support

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vcn: correct target buffer pitch calculation

since the way should be as same as UVD

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

anv: Check that in_fence fd is valid before closing it.

Probably harmless, but will overwrite errno with a failure status
code.  Reported by coverity.

CID 1416600: Argument cannot be negative (NEGATIVE_RETURNS)
Fixes: 5c4e4932e02 (anv: Implement support for exporting semaphores as FENCE_FD)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Add error handling to setup_empty_execbuf().

The anv_execbuf_add_bo() call can actually fail in practice, which
should cause the QueueSubmit operation to fail.  Reported by Coverity.

CID: 1416606: Unchecked return value (CHECKED_RETURN)
Fixes: 017cdb10cf (anv: Submit a dummy batch when only semaphores are provided.)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

tgsi/scan: fix uses_double

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium: remove TGSI opcode SCS

use COS+SIN instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>

gallium/u_blitter: don't use boolean, TRUE, FALSE

v2: cherry-picked from the bigger patch series

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Brian Paul <brianp@vmware.com>

gallium/u_simple_shaders: do util_make_layered_clear_vertex_shader differently

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>

gallium/u_blitter: remove get_next_surface_layer callback

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>

st/glsl_to_tgsi: fix getting the image type for array of structs (again)

We want the type of the field, not of the struct.

This fixes a regression in the following piglit test:
arb_bindless_texture/compiler/images/arrays-of-struct.frag

Fixes: 49d9286a3f ("glsl: stop copying struct and interface member names")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

gallium: remove TGSI opcode BREAKC

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium: remove TGSI opcode XPD

use MUL+MAD+MOV instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: remove TGSI opcode DPH

use DP4 or DP3 + ADD.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: remove TGSI opcode DP2A

use DP3 instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: remove TGSI_OPCODE_CALLNZ

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: remove TGSI FENCE opcodes

use MEMBAR instead

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZ

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

radeonsi: emit VGT_REUSE_OFF in the right place

clip_regs aren't marked dirty when writes_viewport_index is changed.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add support for TGSI opcodes DCEIL, DFLR, DROUND, DSSG, DTRUNC

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use a faster version of PK2H

+ 4 piglit regressions, but it's correct accorcing to the GL spec and
performance is more important than piglit.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't decompress Z/S if there is no HTILE

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add helpers for whether HTILE is enabled

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't flush L2 metadata for DB if not needed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't flush L2 metadata for CB if not needed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't flush TC L2 between rendering and texturing if not needed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: use correct TC flush flags when invalidating CB & DB

Now we can finally stop flushing L2 data.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface/gfx9: don't allow DCC for the smallest mipmap levels

This fixes garbage there if we don't flush TC L2 after rendering.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't use GS scenario A for VS writing ViewportIndex

Vulkan doesn't do it anymore.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: clean up EOP_DATA_SEL magic numbers

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set 'not a query' for r600_gfx_write_event_eop correctly

0 is PIPE_QUERY_OCCLUSION_COUNTER, which is not what we want.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: prevent shader-db crashes

- don't precompile LS and ES (they don't exist on GFX9), compile as VS instead
- don't precompile HS and GS (we don't have LS and ES parts)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: properly handle imported textures with unexpected swizzle mode

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove Constant Engine support

We have come to the conclusion that it doesn't improve performance.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add a temporary workaround for a tessellation driver bug

The workaround will do for now. The root cause is still unknown.

This fixes new piglit: 16in-1out

Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

glsl_to_tgsi: clean up opcode translation

An island of beauty in the middle of chaos.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: pass ctx to add_uniform_to_shader constructor

Fixes: 4c2422067b5c ("glsl: pass UseSTD430AsDefaultPacking to where it will be used")

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

egl: deduplicate allocations of local buffer over each platform backend (v2)

platform_drm, platform_wayland and platform_android have similiar local buffer
allocation routines. For deduplicating, it unifies dri2_egl_surface's
local buffer allocation routines. And it polishes inconsistent indentations.

Note that as dri2_wl_get_buffers_with_format() have not make a __DRI_BUFFER_BACK_LEFT
attachment buffer for local_buffers, new helper function, dri2_egl_surface_free_local_buffers(),
will drop the __DRI_BUFFER_BACK_LEFT check.
So if other platforms use new helper functions, we have to ensure not to make
__DRI_BUFFER_BACK_LEFT attachment buffer for local_buffers.

v2: Fixes from Emil's review:
   a) Make local_buffers variable, dri2_egl_surface_alloc_local_buffer() and
      dri2_egl_surface_free_local_buffers() unconditionally.
   b) Preserve the original codeflow for error_path and normal_path.
   c) Add note on commit messages for dropping of __DRI_BUFFER_BACK_LEFT check.
   c) Rollback the unrelated whitespace changes.
   d) Add a missing blank line.

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>

mesa: only expose EXT_memory_object functions if the ext is supported

They should not be exposed when the extension is unsupported.
Note that ARB_direct_state_access is always exposed and
EXT_semaphore is not supported at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: only expose glImportMemoryFdEXT if the ext is supported

From the EXT_external_objects_fd spec:

   "If the GL_EXT_memory_object_fd string is reported, the following
    commands are added:

    void ImportMemoryFdEXT(uint memory,
                           uint64 size,
                           enum handleType,
                           int fd);"

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: try to re-use previously deleted bindless descriptor slots

Currently, when the array is full it is resized but it can grow
over and over because we don't try to re-use descriptor slots.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: use slot indexes for bindless handles

Using VRAM address as bindless handles is not a good idea because
we have to use LLVMIntToPTr and the LLVM CSE pass can't optimize
because it has no information about the pointer.

Instead, use slots indexes like the existing descriptors. Note
that we use fixed 16-dword slots for both samplers and images.
This doesn't really matter because no real apps use image handles.

This improves performance with DOW3 by +7%.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: add si_emit_global_shader_pointers() helper

To share common code between rw buffers and bindless descriptors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: only initialize dirty_mask when CE is used

Looks like it's useless to initialize that field when CE is
unused. This will also allow to declare more than 64 elements
for the array of bindless descriptors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: make some si_descriptors fields 32-bit

The number of bindless descriptors is dynamic and we definitely
have to support more than 256 slots.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: declare new user SGPR indices for bindless samplers/images

A new pair of user SGPR is needed for loading the bindless
descriptors from shaders. Because the descriptors are global for
all stages, there is no need to add separate indices for GFX9.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/util: add new module that allocate "numbers"

Will be used for allocating bindless descriptor slots for
RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi/gfx9: add performance counters

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: extract common code of si_upload_{graphics,compute}_shader_descriptors

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: remove unused PIPE_DUMP_* defines

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ddebug: remove dd_draw_record::driver_state_log

It is no longer used.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: emit string markers to log context

Reviewed-by: Marek Olšák <marek.olsak@amd.com>