Timur Kristóf [Tue, 22 Aug 2023 20:28:43 +0000 (22:28 +0200)]
ac/nir/ngg: Refactor mesh shader primitive export.
Cleanup the code that generates the two channels of the
primitive export instruction, and move storing the built-in
per-primitive outputs out to match how vertex attributes work.
Prepares the mesh shader lowering for a workaround that
affect export instructions.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 19:51:43 +0000 (21:51 +0200)]
ac/nir/ngg: Wait for attribute stores before VS/TES/GS pos0 export.
This is a HW bug workaround for some (all?) GFX11 chips.
On these chips, rasterization can start before the attribute ring
stores are finished, which can cause issues.
As a workaround, wait for attribute ring stores to finish
before doing the position export.
Mesh shaders will be taken care of in another commit.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 19:30:05 +0000 (21:30 +0200)]
ac/nir: Slightly refactor how pos0 exports are added when missing.
Prepares for a workaround. Makes it possible for this function
to not emit the pos0 export at all so that it can be emitted
by a subsequent call to the function later.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 18:22:32 +0000 (20:22 +0200)]
ac/nir: Add done arg to ac_nir_export_position.
This prepares for a workaround where we won't need to add
the done flag to the last export in this function, because
it will be added in a subsequent call to the same function.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Lionel Landwerlin [Fri, 25 Aug 2023 07:48:19 +0000 (10:48 +0300)]
isl/tilememcpy_test: add multiple tile testing
Also verify that there is no out-of-bounds accesses.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Thu, 28 Jul 2022 00:35:03 +0000 (17:35 -0700)]
Revert "iris: Disable tiled memcpy for Tile4"
This reverts commit
0022a11ff4fbbe89c2511d758f807b286ebb1bd7.
Enable path for Tile4 memcpy functions to be used.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Mon, 18 Jul 2022 23:59:46 +0000 (16:59 -0700)]
intel/isl: Linear to Tile-4 conversion unittest
Add unittest to test conversion of data from linear to
Tile-4 format based on bit swizzling conversion info
mentioned in Bspec.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Mon, 18 Jul 2022 21:22:12 +0000 (14:22 -0700)]
intel/isl: Convert Tile4 texture to linear format
Add memcpy function to convert Tile-4 4KB texture to linear
format.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Mon, 18 Jul 2022 21:18:24 +0000 (14:18 -0700)]
intel/isl: Convert linear texture to Tile4 format
Add memcpy function to convert linear data to Tile 4 format.
Tile 4 format consists of 4KB block divided into chunks of 512B.
Each 512B chunk/block is comprised of 8 64B blocks arranged in
Y-tile format.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Mon, 1 Nov 2021 21:41:04 +0000 (14:41 -0700)]
intel/isl: Unittest for linear to Ytile conversion
Add unittests for linear to tiled and tiled to linear texture
conversions for Ytile. The test prints the source/output buffer
in hex format with debug flags to verify the result.
Linear to tile conversion fills the linear buffer with values
based on the OWORD index number i.e., OWORD3 will contain
all values filled as 0x03 and
OWORD3 = 0x03030303030303030303030303030303.
The Y-tile to Linear tile conversion uses a similar logic to place
the tiled values in a manner that will result in a linear buffer with
OWORDs filled according to index number as mentioned above.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Rohan Garg [Fri, 1 Sep 2023 11:48:51 +0000 (13:48 +0200)]
blorp: drop undefined macro
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
97d6ceaf04 ("intel: Remove GEN_IS_HASWELL macro")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 11:48:20 +0000 (13:48 +0200)]
crocus: fix GFX_VERx10 macro
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 11:29:53 +0000 (13:29 +0200)]
crocus: add a __gen_get_batch_address declaration
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 10:39:13 +0000 (12:39 +0200)]
anv: use the lineage number for WA
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
d0669f3ede ("intel/dev: switch defect identifiers to use lineage numbers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 10:38:35 +0000 (12:38 +0200)]
iris: use the correct WA macros and lineage numbers
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
0ce595a89a ("intel: use generated helpers for Wa_1508744258")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 09:48:18 +0000 (11:48 +0200)]
anv: drop dead ifdef
The GFX_VERX10 macro doesn't exist and we no longer use
SCRATCH_SURFACE_STATE_POOL_SIZE.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
b3f6e5dc702 ('anv: remove incorrect ifdef')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Matt Turner [Sat, 2 Sep 2023 12:22:53 +0000 (08:22 -0400)]
intel: Limit Intel Vulkan RT to x86_64
Note: passed CI repeatedly except for the timing out WHL jobs.
Fixes:
28c1053c07c ("intel: Allow using intel_clc from the system")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25009>
Alyssa Rosenzweig [Sat, 2 Sep 2023 19:43:01 +0000 (15:43 -0400)]
ci: Disable WHL jobs
Timing out all day.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 30 Aug 2023 00:56:53 +0000 (20:56 -0400)]
ci: Disable known broken Bifrost Vulkan job
Until someone does the work to eliminate faults, PanVK will be inherently flaky
and should not be in CI. deqp-runner can eat a lot of flakes, and then retrying
the whole job eats more flakes, but neither is a substitute for not testing
known broken (and hence flaky) code and both increase runtime unacceptably. the
g52-vk job earned 2 spots on the latest leaderboard for slowest jobs, I clicked
on https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
48142375 to see a jawdropping
54 flakes reported by deqp-runner.
If people insist on keeping the job, then panfrost-g52-vk needs to be demoted to
manual until after someone fixes all these bugs on the driver side. If that's
not going to happen, then there's no point in it being in CI at all. It's broken
code. After a buggy MR, it'll still be broken code. CI doesn't matter if we're
ok with it being broken.
Bottom line is, we can't be running known broken code in CI (bugs = faults =
flakes = unhappy developers), at least for non-robust stacks (panfrost.ko
included). This needs to be policy if it isn't already. Merging this single
character change deals with the hot problem without any fanfare or adverse
effects.
This turns the job into a nightly as David suggested to get it out of the
premerge path until someone is committed to supporting it and does the work to
make it happen.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9721
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24943>
Georg Lehmann [Tue, 8 Aug 2023 11:35:18 +0000 (13:35 +0200)]
aco: implement some exclusive scans with inclusive scans
exclusive scan lowering uses full wave shift, for iadd/ixor it's faster
to do inclusive scans and subtract/xor the thread's source.
Foz-DB Navi21:
Totals from 21 (0.02% of 132657) affected shaders:
Instrs: 10925 -> 10727 (-1.81%)
CodeSize: 58064 -> 56488 (-2.71%)
Latency: 178471 -> 177928 (-0.30%)
InvThroughput: 24374 -> 24145 (-0.94%)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24555>
Karol Herbst [Tue, 29 Aug 2023 19:59:31 +0000 (21:59 +0200)]
rusticl/memory: only specify PIPE_BIND_SHADER_IMAGE where supported
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24982>
Georg Lehmann [Sat, 12 Aug 2023 22:14:29 +0000 (00:14 +0200)]
nir: add nir_scalar_equal
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>
Georg Lehmann [Sat, 12 Aug 2023 22:03:03 +0000 (00:03 +0200)]
nir: add nir_scalar intrinsic helpers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>
David Heidelberg [Wed, 30 Aug 2023 19:11:26 +0000 (21:11 +0200)]
docs: add LAVA farm informations
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>
David Heidelberg [Wed, 30 Aug 2023 17:49:20 +0000 (19:49 +0200)]
Revert "ci: disable a660 jobs"
This reverts commit
209ed8eace0ba9095e3ef956a10cd9196407047f.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>
Lionel Landwerlin [Wed, 14 Jun 2023 09:31:19 +0000 (12:31 +0300)]
anv: enable standard Y tiles
We kept those tilings disabled up to know. Now that ISL has proper
support for them, remove this.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 11 Oct 2018 21:38:31 +0000 (16:38 -0500)]
anv: Align memory VA to support for Ys, Tile64 tiled images
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Aditya Swarup [Thu, 8 Jun 2023 22:22:11 +0000 (15:22 -0700)]
isl: enable Tile64 for 3D images
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 03:02:09 +0000 (19:02 -0800)]
intel/isl: Allow Ys tiling
Ys & Yf are both implemented in ISL now, we still have some Yf issues
to investigate. Instead of disabling them in ISL, we disable them in
the two drivers.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Mon, 26 Jun 2023 10:03:23 +0000 (13:03 +0300)]
isl: reorder tiling selection
Select tilings in this order :
- recommended Y tilings
- Yf tilings
- Ys/Tile64 tilings
- legacy tilings (W, X) & Linear
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Wed, 28 Jun 2023 06:32:54 +0000 (09:32 +0300)]
intel/aux_map: correctly program tiling mode for Ys
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Wed, 21 Jun 2023 15:44:27 +0000 (18:44 +0300)]
blorp: allow 3D blits/copies on Ys/Yf/Tile64 tiling
The data in Ys/Yf/Tile64 tiled images is arranged differently for 2D &
3D images. Therefore we cannot assume that we will use 2D images for
blits/copies.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 15 Aug 2023 13:24:59 +0000 (16:24 +0300)]
isl: disable CCS on Ys/Yf
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 27 Jun 2023 11:42:52 +0000 (14:42 +0300)]
isl: disable miptails on gfx12 with yuv formats
A number of CTS tests are failing, like :
dEQP-VK.ycbcr.format.b8g8r8g8_422_unorm.vertex_optimal
Failures are reproduced on simulation.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 27 Jun 2023 11:06:43 +0000 (14:06 +0300)]
isl: disallow miptails on planar formats
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Wed, 28 Jun 2023 11:29:30 +0000 (14:29 +0300)]
isl: add Gfx12/12.5 restriction on 3D surfaces & compression
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Tue, 6 Mar 2018 01:42:11 +0000 (17:42 -0800)]
intel/isl: Disallow CCS on 3D surfaces with miptails
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Sat, 3 Mar 2018 03:02:17 +0000 (19:02 -0800)]
intel/isl: Start using miptails
This commit adds the code for choosing where to start the miptail and
enables miptails by default unless the client driver passes
info->min_miptail_start_level >= info->levels.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Sat, 3 Mar 2018 00:43:35 +0000 (16:43 -0800)]
intel/isl: Support miptails in isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 29 Aug 2023 08:54:47 +0000 (11:54 +0300)]
isl: make isl_surf_get_uncompressed_surf robust to argument accesses
Since the input & output arguments can point to the same location in
memory, if you ever access the input after writing the output you're
in trouble.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Fri, 2 Mar 2018 20:37:52 +0000 (12:37 -0800)]
intel/isl: Add support for computing offsets with miptails
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Fri, 2 Mar 2018 23:30:24 +0000 (15:30 -0800)]
intel/isl: Add a max_miptail_levels field to isl_tile_info
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Sat, 3 Mar 2018 00:02:58 +0000 (16:02 -0800)]
intel/isl: Add initial data-structure support for miptails
This commit just adds a miptail start field to isl_surf and wires it up
in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code. We also add a
minimum miptail LOD so that client drivers have a knob to control the
miptails a bit.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Fri, 25 Aug 2017 18:23:23 +0000 (11:23 -0700)]
intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Fri, 25 Aug 2017 04:16:03 +0000 (21:16 -0700)]
intel/isl: Support Yf/Ys tiling in surf_fill_state
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 21:53:03 +0000 (13:53 -0800)]
intel/isl: Support Ys, Yf & Tile64 in isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Wed, 7 Jul 2021 15:37:57 +0000 (10:37 -0500)]
intel/isl: Indent uncompressed surface code
We're about to add separate code for Yf/Ys and this helps keep the diff
reasonable.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 02:12:30 +0000 (18:12 -0800)]
intel/isl: Fill out the correct phys_total_extent for Ys/Yf/Tile64
With these tilings, everything is aligned to a tile and the tiled
surface size calculations will handle the array stride for us. We need
to provide an accurate 4D size so that 3D and multisampled images get
tiled correctly.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 02:05:15 +0000 (18:05 -0800)]
intel/isl: Use the depth field of phys_level0_sa for GFX4_2D 3D surfaces
This makes things a tiny bit stickier in isl_calc_phys_total_extent_el
but will be worth it when we enable Yf and Ys.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Sun, 25 Jun 2023 20:31:39 +0000 (23:31 +0300)]
isl: disallow TileYs/Yf on 3D storage images on Gfx9/11
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Fri, 23 Jun 2023 21:47:25 +0000 (00:47 +0300)]
isl: add a usage flag to request 2D/3D compatible views
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 8 Aug 2023 11:14:02 +0000 (14:14 +0300)]
isl: disable Yf/Ys/Tile64 tilings for 1D images
The ICL+ PRMs show that this is not a supported thing anymore for
Ys/Yf and there isn't really much use for it in Vulkan/Sparse.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Fri, 12 Oct 2018 17:17:02 +0000 (12:17 -0500)]
intel/isl: Disallow Yf, Ys and Tile64 for 3D depth/stencil surfaces
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 00:04:32 +0000 (16:04 -0800)]
intel/isl: Implement correct tile size calculations for Ys/Yf
The tile size calculations use a clever bit of math to make them short
and simple. We add unit tests to assert that they identically match the
tables in the PRM.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Wed, 7 Mar 2018 05:04:50 +0000 (21:04 -0800)]
intel/isl: Add ICL variants of Yf and Ys tiling
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Wed, 7 Mar 2018 04:50:44 +0000 (20:50 -0800)]
intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_SKL_Yf/s
The Yf and Ys tilings change a bit between SKL and later generations so
we have to be able to distinguish between them.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Mon, 19 Jun 2023 13:38:24 +0000 (16:38 +0300)]
isl: program 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode as documented
Since this value is 0, it doesn't change anything, but it's just good
practice like we did for Gfx12.5 right above.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Mon, 19 Jun 2023 13:37:42 +0000 (16:37 +0300)]
genxml/gfx12: rename Tiled Resource Mode
To match documentation.
BSpec 46965
TGL PRMs, Volume 2d: Command Reference: Structures, 3DSTATE_HIER_DEPTH_BUFFER_BODY
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Mon, 19 Jun 2023 13:36:58 +0000 (16:36 +0300)]
genxml/gfx11: remove Tiled Resource Mode field from HIER_DEPTH_BUFFER
This field doesn't exist according to documentation. Only a MBZ.
BSpec 6511
ICL PRMs, Volume 2a - Command Reference: Instructions (Command
Opcodes) 3DSTATE_HIER_DEPTH_BUFFER
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Mon, 26 Jun 2023 07:09:50 +0000 (10:09 +0300)]
anv: add missing ISL storage usage
ISL makes a bunch of decision on programming (MOCS,
RENDER_SURFACE_STATE values) based on this flag. It's important to set
it if we're going to use an image as storage.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Matt Turner [Thu, 31 Aug 2023 17:16:29 +0000 (13:16 -0400)]
intel: Allow using intel_clc from the system
With -Dintel-clc=system, the build system will search for an `intel_clc`
binary and use it instead of building `intel_clc` itself.
This allows Intel Vulkan ray tracing support to be built when cross
compiling without terrible hacks (that would otherwise be necessary due
to `intel_clc`'s dependence on SPIRV-LLVM-Translator, libclc, clang, and
LLVM).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24983>
Karol Herbst [Fri, 1 Sep 2023 10:49:59 +0000 (12:49 +0200)]
rusticl/memory: do not verify pitch for IMAGE1D_BUFFER
Devices might report an image_pitch_alignment of 0 leading to a division
by 0 trap.
Fixes:
06daa03c5cd ("rusticl: Implement spec for cl_khr_image2d_from_buffer")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24993>
Eric Engestrom [Fri, 1 Sep 2023 13:52:31 +0000 (14:52 +0100)]
ci/amd: split the polaris10 rules into one for each farm
There is now one polaris10 in each farm, so we need two rules for which
one to use.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24996>
Mark Janes [Thu, 24 Aug 2023 00:24:34 +0000 (17:24 -0700)]
intel: allow reduced memory usage for INTEL_MEASURE
The default batch size was increased to support large numbers of
INTEL_MEASURE snapshots for complex workloads. Some titles create
large numbers of small secondary command buffers, and quickly exhaust
memory. An example of this is Dota2, where INTEL_MEASURE increases
the memory usage by a factor of 20.
Allow the user to specify smaller batch sizes and buffer sizes.
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24860>
Georg Lehmann [Fri, 25 Aug 2023 17:23:14 +0000 (19:23 +0200)]
aco: use v_cvt_f32_ubyte for signed casts too
The extract is always positive, so signed vs unsigned conversion doesn't matter.
Foz-DB GFX11:
Totals from 167 (0.13% of 133461) affected shaders:
Instrs: 401631 -> 401225 (-0.10%)
CodeSize: 2107256 -> 2104344 (-0.14%)
VGPRs: 13320 -> 13332 (+0.09%)
Latency: 6468063 -> 6467241 (-0.01%)
InvThroughput: 801854 -> 801653 (-0.03%)
Copies: 13926 -> 13927 (+0.01%); split: -0.08%, +0.09%
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24893>
Nanley Chery [Wed, 23 Aug 2023 14:30:33 +0000 (10:30 -0400)]
anv: Initialize the clear color more often for FCV
Instead of only initializing the clear color when the first subresource
is accessed, initialize it for every FCV-enabled subresource. This is
needed because writes to any subresource may be converted to fast
clears.
Now that init_fast_clear_color is called for every subresource, we take
care not to stomp on the fast-clear-tracking state of the first
subresource by moving the code which updates it outside of
init_fast_clear_color.
Now init_fast_clear_color does just what it says: initializes the fast
clear color.
This fixes the regression introduced with commit
57445adc891,
("anv: Re-enable CCS_E on TGL+").
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8461
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24857>
Samuel Pitoiset [Thu, 31 Aug 2023 10:26:33 +0000 (12:26 +0200)]
radv/ci: re-enable vkcts-polaris10-valve
This was disabled a long time ago because of unknown GPU hangs during
boot but it seems stable again for some reasons.
This also bumps the job timeouts to make sure it will be able to finish.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24968>
Karol Herbst [Fri, 1 Sep 2023 09:10:28 +0000 (11:10 +0200)]
rusticl/queue: properly implement clCreateCommandQueueWithProperties
It didn't do any of the error checking, but it was supposed to be. Also
the error checking was slightly wrong and we should return
CL_INVALID_QUEUE_PROPERTIES instead of CL_INVALID_VALUE for unsupported
properties.
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24991>
Samuel Pitoiset [Thu, 31 Aug 2023 14:35:21 +0000 (16:35 +0200)]
zink/ci: add zink-radv-polaris10-valve
This introduces Zink/RADV testing on Polaris10!
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24976>
Feng Jiang [Thu, 10 Aug 2023 02:53:47 +0000 (10:53 +0800)]
meson: Move video to separate section in meson configuration summary
Since the video configuration is shared by multiple video APIs, not
just vulkan, move it to a separate section.
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24598>
Tapani Pälli [Thu, 31 Aug 2023 03:15:35 +0000 (06:15 +0300)]
ci: add a fix for KHR-GLES3.packed_pixels.*snorm tests
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24600>
Tapani Pälli [Thu, 10 Aug 2023 05:07:29 +0000 (08:07 +0300)]
mesa: remove GL_UNSIGNED_BYTE as supported for snorm reads
UNSIGNED_BYTE should not be allowed for reading snorm color buffers.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9718
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24600>
Vlad Schiller [Mon, 21 Aug 2023 08:55:18 +0000 (09:55 +0100)]
pvr: Implement VK_EXT_tooling_info
This commit will enable the EXT_tooling_info extension,
which was already implemented in the common code.
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24928>
Rohan Garg [Thu, 31 Aug 2023 17:06:34 +0000 (19:06 +0200)]
anv: use the pre defined _3DPRIMITIVE_DIRECT macro
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24978>
Konstantin Seurer [Mon, 28 Aug 2023 16:24:36 +0000 (18:24 +0200)]
aco/lower_to_cssa: Fix typo
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
Konstantin Seurer [Mon, 28 Aug 2023 13:39:44 +0000 (15:39 +0200)]
radv: Only generate debug info if required
Fixes:
51f2fa1a5ef ("radv: Break up radv_shader_nir_to_asm")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
Konstantin Seurer [Mon, 28 Aug 2023 08:58:05 +0000 (10:58 +0200)]
aco: Unify demote and demote_if selection
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
Konstantin Seurer [Mon, 28 Aug 2023 07:36:50 +0000 (09:36 +0200)]
aco: Use bytes() instead of size() in emit_wqm
This should get most of the cases that would fail validation.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
Konstantin Seurer [Mon, 28 Aug 2023 07:36:18 +0000 (09:36 +0200)]
aco/validate: Handle p_wqm like p_parallelcopy
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
Samuel Pitoiset [Mon, 28 Aug 2023 13:53:40 +0000 (15:53 +0200)]
aco: allow separate compilation of NGG shaders
Also prevent to emit a long-jump for VS as NGG without a GS.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
Samuel Pitoiset [Mon, 28 Aug 2023 14:51:17 +0000 (16:51 +0200)]
aco: adjust fix_exports() for VS/TES as NGG and non-monolithic shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
Samuel Pitoiset [Mon, 28 Aug 2023 14:48:24 +0000 (16:48 +0200)]
aco: flag blocks with long-jump as export_end for separate compilation
This will allow us to adjust fix_exports().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
Samuel Pitoiset [Mon, 28 Aug 2023 13:39:08 +0000 (15:39 +0200)]
radv: preserve shader argument for separate compilation of NGG shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
Qiang Yu [Sat, 5 Aug 2023 09:24:55 +0000 (17:24 +0800)]
radeonsi: enable aco compile for part mode standalone vs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
Qiang Yu [Sat, 5 Aug 2023 12:30:05 +0000 (20:30 +0800)]
radeonsi: set vs has prolog aco shader info
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
Qiang Yu [Sat, 5 Aug 2023 08:56:33 +0000 (16:56 +0800)]
radeonsi: add vs prolog aco build
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
Qiang Yu [Fri, 4 Aug 2023 12:50:28 +0000 (20:50 +0800)]
radeonsi: fix aco options has_ls_vgpr_init_bug setup
Fixes:
b313d950e23 ("radeonsi: enable aco compile for mono merged LS/HS")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
Qiang Yu [Fri, 4 Aug 2023 12:06:18 +0000 (20:06 +0800)]
radeonsi: extract si_get_vs_prolog_args to be shared with aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
Qiang Yu [Fri, 4 Aug 2023 09:49:04 +0000 (17:49 +0800)]
radeonsi: remove is_monolithic from vs prolog key
We do not generate vs prolog for monolithic shader any more.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24713>
Dave Airlie [Tue, 29 Aug 2023 01:23:27 +0000 (11:23 +1000)]
nvk: add build_id linker argument.
the build id was failing for a gentoo build causing instance
creation to fail, this seems to fix it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24916>
Qiang Yu [Tue, 29 Aug 2023 06:49:00 +0000 (14:49 +0800)]
radeonsi: fill aco_shader_info->is_monolithic
Fixes:
80177e02962 ("aco: add support for compiling VS+TCS separately on GFX9+")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24944>
Karol Herbst [Tue, 29 Aug 2023 18:30:21 +0000 (20:30 +0200)]
rusticl/event: disable profiling for devices without timestamps
Timestamp queries are strictly required, but a bit odd to not expose CL
for not supporting it...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>
Karol Herbst [Tue, 29 Aug 2023 18:20:24 +0000 (20:20 +0200)]
rusticl/query: fix use-after-free, but also fix incorrect usage of unsafe
`PipeQuery::new` create a `PipeQuery` wrapper before handling errors, so
we ended up calling `drop` and destroy_query, meaning the latter ended up
being called twice.
While at it, also restrict visibility of related methods and add some
unsafe declarations.
Fixes:
52e53938c37 ("rusticl: Wrap pipe queries")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24938>
Lina Versace [Thu, 31 Aug 2023 17:44:30 +0000 (10:44 -0700)]
docs: Add row for VK_KHR_maintenance5
Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24980>
Matt Turner [Wed, 30 Aug 2023 18:47:30 +0000 (14:47 -0400)]
intel: Only build perf if drivers or tools are enabled
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>
Matt Turner [Wed, 30 Aug 2023 18:46:59 +0000 (14:46 -0400)]
intel: Only build ds if drivers are enabled
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>
Matt Turner [Wed, 30 Aug 2023 18:46:03 +0000 (14:46 -0400)]
intel: Only build blorp if drivers are enabled
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>
Matt Turner [Wed, 30 Aug 2023 18:51:14 +0000 (14:51 -0400)]
intel: Consider with_intel_clc in with_any_intel
This makes it possible to configure mesa to build only intel_clc.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>
Matt Turner [Wed, 30 Aug 2023 18:50:00 +0000 (14:50 -0400)]
intel: Rearrange for next commit
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24974>
Lang Yu [Sun, 27 Aug 2023 11:56:49 +0000 (19:56 +0800)]
radeonsi: use wave size to determine index stride
Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>