Kadir Cetinkaya [Mon, 2 Nov 2020 10:27:21 +0000 (11:27 +0100)]
[clangd] Introduce ProjectAwareIndex
An index implementation that can dispatch to a variety of indexes
depending on the file path. Enables clangd to work with multiple indexes in the
same instance, configured via config files.
Depends on D90749, D90746
Differential Revision: https://reviews.llvm.org/D90750
Kadir Cetinkaya [Tue, 6 Oct 2020 12:21:42 +0000 (13:21 +0100)]
[clangd] Introduce config compilation for External blocks
Compilation logic for External blocks. A few of the high level points:
- Requires exactly one-of File/Server at a time:
- Server is ignored in case of both, with a warning.
- Having none is an error, would render ExternalBlock void.
- Ensures mountpoint is an absolute path:
- Interprets it as relative to FragmentDirectory.
- Defaults to FragmentDirectory when empty.
- Marks Background as Skip.
Depends on D90748.
Differential Revision: https://reviews.llvm.org/D90749
Kadir Cetinkaya [Thu, 1 Oct 2020 11:29:55 +0000 (12:29 +0100)]
[clangd] Introduce config parsing for External blocks
Enable configuration of remote and static indexes through config files
in addition to command line arguments.
Differential Revision: https://reviews.llvm.org/D90748
Aaron Puchert [Sun, 22 Nov 2020 19:51:00 +0000 (20:51 +0100)]
Build reproducible tarballs for releases
Currently the tarballs contain superfluous metadata, like the user name
of the packager and via Pax headers even the PID of the tar process that
packaged the files. We build the monorepo projects directly from the git
repo using "git archive" and for the test-suite we add some flags as
recommended by https://reproducible-builds.org/docs/archives/. We don't
use numeric owners though to be compatible with "git archive".
The advantage of "git archive" is that the releaser doesn't have to
download the tar ball and extract it, rather the archive is built
directly from the repository. This is probably what GitHub uses
internally to produce the tarballs, so I wouldn't expect a difference.
Reviewed By: tstellar
Differential Revision: https://reviews.llvm.org/D91494
Aaron Puchert [Sun, 22 Nov 2020 17:43:15 +0000 (18:43 +0100)]
[Sema] Introduce function reference conversion, NFC
Technically 'noexcept' isn't a qualifier, so this should be a separate conversion.
Also make the test a pure frontend test.
Reviewed By: rsmith
Differential Revision: https://reviews.llvm.org/D67112
Nikita Popov [Sun, 22 Nov 2020 19:09:56 +0000 (20:09 +0100)]
[BasicAA] Avoid unnecessary cache update (NFC)
If the final recursive query returns MayAlias as well, there is
no need to update the cache (which already stores MayAlias).
Sanjay Patel [Sun, 22 Nov 2020 18:43:53 +0000 (13:43 -0500)]
[CostModel] add basic handling for FP maximum/minimum intrinsics
This might be a regression for some ARM targets, but that should
be changed in the target-specific overrides.
There is apparently still no default lowering for these nodes,
so I am assuming these intrinsics are not in common use.
X86, PowerPC, and RISC-V for example, just crash given the most
basic IR.
Sanjay Patel [Sun, 22 Nov 2020 18:33:42 +0000 (13:33 -0500)]
[CostModel] add tests for FP maximum; NFC
These min/max intrinsics are not handled in the basic
implementation and probably not handled in target-specific
overrides either.
Sanjay Patel [Sun, 22 Nov 2020 17:54:18 +0000 (12:54 -0500)]
[ValueTracking][MemCpyOpt] avoid crash on inttoptr with vector pointer type (PR48075)
Nikita Popov [Sun, 22 Nov 2020 12:50:23 +0000 (13:50 +0100)]
[BasicAA] Add more phi-phi tests (NFC)
Test a few more variations:
* NoAlias with different strides
* MustAlias without loop
* MustAlias with same stride
* MustAlias base pointers with different stride
Marek Kurdej [Sun, 22 Nov 2020 14:56:39 +0000 (15:56 +0100)]
[libc++] [libc++abi] Use C++20 standard.
This change is needed to use char8_t when building libc++.
Using the same standard in libc++abi for coherence.
See https://reviews.llvm.org/D91517.
Reviewed By: ldionne, #libc, #libc_abi
Differential Revision: https://reviews.llvm.org/D91691
Yashaswini [Sun, 22 Nov 2020 13:06:59 +0000 (18:36 +0530)]
Add Semantic check for Flang OpenMP 4.5 - 2.7.1 ordered and collapse clause
Semantic check added to check and restrict the value of the parameter in the COLLAPSE or ORDERED clause
if it is larger than the number of nested loops following the construct.
Test Cases:
omp-do-collapse-positivecases.f90
omp-do-collapse.f90
omp-do-ordered-positivecases.f90
omp-do-ordered.f90
Reviewed by: Kiran Chandramohan @kiranchandramohan , Valentin Clement @clementval
Differential Revision: https://reviews.llvm.org/D89860
Simon Pilgrim [Sun, 22 Nov 2020 13:02:27 +0000 (13:02 +0000)]
[DAG] LowerMINMAX - move default expansion to generic TargetLowering::expandIntMINMAX
This is part of the discussion on D91876 about trying to reduce custom lowering of MIN/MAX ops on older SSE targets - if we can improve generic vector expansion we should be able to relax the limitations in SelectionDAGBuilder when it will let MIN/MAX ops be generated, and avoid having to flag so many ops as 'custom'.
Nathan James [Sun, 22 Nov 2020 10:48:48 +0000 (10:48 +0000)]
[clangd] Fix compile error after
20b69af7
Some of the buildbots were failing due to what seems to be them using a non c++14 compilant std::string implementation.
Since c++14 std::basic_string::append(const basic_string, size_t, size_t) has a defaulted 3rd paramater, but some of the build bots were reporting that it wasn't defaulted in their implementation.
Simon Pilgrim [Sun, 22 Nov 2020 10:30:43 +0000 (10:30 +0000)]
[Analysis] Remove unused system header includes
Cleanup unused system headers and fix an implicit dependency
Nathan James [Sun, 22 Nov 2020 10:04:00 +0000 (10:04 +0000)]
[clangd] Add clang-tidy options to config
First step of implementing clang-tidy configuration into clangd config.
This is just adding support for reading and verifying the clang tidy options from the config fragments.
No support is added for actually using the options within clang-tidy yet.
That will be added in a follow up as its a little more involved.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D90531
Craig Topper [Sun, 22 Nov 2020 08:43:12 +0000 (00:43 -0800)]
[RISCV] Use separate Lo and Hi MemOperands when expanding BuildPairF64Pseudo and SplitF64Pseudo.
We generate two 4 byte loads or two stores as part of the expansion.
Previously the MemOperand was set the same for both to cover the
full 8 bytes. Now we set a separate 4 byte mem operand for each
with a 4 byte offset for the high part.
Esme-Yi [Sun, 22 Nov 2020 07:37:24 +0000 (07:37 +0000)]
[PowerPC] Extend folding RLWINM + RLWINM to post-RA.
Summary: We have the patterns to fold 2 RLWINMs before RA, while some RLWINM will be generated after RA, for example rGc4690b007743. If the RLWINM generated after RA followed by another RLWINM, we expect to perform the optimization too.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D89855
Kazu Hirata [Sun, 22 Nov 2020 07:35:02 +0000 (23:35 -0800)]
[MBP] Remove unused declaration shouldPredBlockBeOutlined (NFC)
The function was introduced on Jun 12, 2016 in commit
071d0f180794f7819c44026815614ce8fa00a3bd. Its definition was removed
on Mar 2, 2017 in commit
1393761e0ca3fe8271245762f78daf4d5208cd77.
Yashaswini [Sun, 22 Nov 2020 06:32:00 +0000 (12:02 +0530)]
Add Semantic check for Flang OpenMP 4.5 - 2.15.3.2 and 2.15.3.3 shared and private clause
Semantic check to restrict the appearance of a variable that is part of another variable
(as an array or structure element) in a PRIVATE or SHARED clause.
Test Cases:
omp-parallel-private01.f90
omp-parallel-private02.f90
omp-parallel-private03.f90
omp-parallel-private04.f90
omp-parallel-shared01.f90
omp-parallel-shared02.f90
omp-parallel-shared03.f90
omp-parallel-shared04.f90
Reviewed by: Kiran Chandramohan @kiranchandramohan , Valentin Clement @clementval
Differential Revision: https://reviews.llvm.org/D89395
Kazu Hirata [Sun, 22 Nov 2020 06:55:37 +0000 (22:55 -0800)]
[MachineLICM] Remove unused declaration HoistRegion
The function definition was removed on Dec 22, 2011 in commit
in
1eed5b51e87758affdbc10627b4a0884ab86606f.
Kazu Hirata [Sun, 22 Nov 2020 06:29:44 +0000 (22:29 -0800)]
[SelectionDAG] Remove unused declaration ExpandStrictFPOp (NFC)
ExpandStrictFPOp started taking two parameters instead of one on Jan
10, 2020 in commit
f678fc7660b36ce0ad6ce4f05eaa28f3e9fdedb5, but the
declaration for the single-perameter version has remained since.
Mircea Trofin [Sun, 22 Nov 2020 05:46:53 +0000 (21:46 -0800)]
thinlto_embed_bitcode.ll: clarify grep should treat input as text
The input to the test's use of grep should be treated as text, and
that's not the case on certain Linux distros. Added --text.
Ella Ma [Sun, 22 Nov 2020 05:04:12 +0000 (21:04 -0800)]
[llvm][clang][mlir] Add checks for the return values from Target::createXXX to prevent protential null deref
All these potential null pointer dereferences are reported by my static analyzer for null smart pointer dereferences, which has a different implementation from `alpha.cplusplus.SmartPtr`.
The checked pointers in this patch are initialized by Target::createXXX functions. When the creator function pointer is not correctly set, a null pointer will be returned, or the creator function may originally return a null pointer.
Some of them may not make sense as they may be checked before entering the function, but I fixed them all in this patch. I submit this fix because 1) similar checks are found in some other places in the LLVM codebase for the same return value of the function; and, 2) some of the pointers are dereferenced before they are checked, which may definitely trigger a null pointer dereference if the return value is nullptr.
Reviewed By: tejohnson, MaskRay, jpienaar
Differential Revision: https://reviews.llvm.org/D91410
Haowei Wu [Sun, 22 Nov 2020 03:59:51 +0000 (19:59 -0800)]
[StaticAnalyzer] Support struct annotations in FuchsiaHandleChecker
Support adding handle annotations to sturucture that contains
handles. All the handles referenced by the structure (direct
value or ptr) would be treated as containing the
release/use/acquire annotations directly.
Patch by Yu Shan
Differential Revision: https://reviews.llvm.org/D91223
Kazu Hirata [Sat, 21 Nov 2020 23:47:11 +0000 (15:47 -0800)]
[InstCombine] Use is_contained (NFC)
Michael Liao [Sat, 21 Nov 2020 22:06:41 +0000 (17:06 -0500)]
Fix shared build.
Fangrui Song [Sat, 21 Nov 2020 20:38:00 +0000 (12:38 -0800)]
[libunwind] Delete unused handlerNotFound in unwind_phase1
Nikita Popov [Sat, 21 Nov 2020 20:31:06 +0000 (21:31 +0100)]
[BasicAA] Remove unnecessary sextOrSelf (NFC)
We are doing a sextOrTrunc directly afterwards, so this seems
useless. There is a multiplication in between, but truncating
before or after the multiplication should not make a difference.
Martin Storsjö [Fri, 20 Nov 2020 09:15:38 +0000 (11:15 +0200)]
[compiler-rt] [profile] Silence a warning about an unused function on mingw targets
This function is only used within the ifdef below.
Differential Revision: https://reviews.llvm.org/D91850
Nikita Popov [Sat, 21 Nov 2020 19:47:11 +0000 (20:47 +0100)]
[BasicAA] Return DecomposedGEP (NFC)
Instead of requiring the caller to initialize the DecomposedGEP
structure and then passing it in by reference, make
DecomposeGEPExpression() responsible for initializing and returning
the structure.
Nikita Popov [Sat, 21 Nov 2020 19:29:28 +0000 (20:29 +0100)]
[BasicAA] Remove some intermediate variables (NFC)
Use DecompGEP1.Offset instead of GEP1BaseOffset, etc. I found the
asymmetry of modifying DecompGEP1.VarIndices, but not modifying
DecompGEP1.Offset odd here.
clementval [Sat, 21 Nov 2020 19:32:31 +0000 (14:32 -0500)]
[NFC] Fix typo in atomic
Valentin Clement [Sat, 21 Nov 2020 19:31:17 +0000 (14:31 -0500)]
[flang][openmp] Separate memory-order-clause parser creating OmpClause node
This patch introduce the separate parser for the memory-order-clause from the general
OmpClauseList. This parser still creates OmpClause node and therefore can use all the feature
from TableGen and the OmpStructureChecker.
This is applied only for the Flush construct in this patch and it should be applied for
atomic as well.
This is the approach we disscussed several time during the weekly call.
Reviewed By: kiranchandramohan, sameeranjoshi
Differential Revision: https://reviews.llvm.org/D91839
Nikita Popov [Sat, 21 Nov 2020 19:05:47 +0000 (20:05 +0100)]
[BasicAA] Remove stale FIXME (NFC)
If aliasGEP returns MayAlias, the code does fall through to
aliasPHI etc, so this FIXME is no longer applicable.
Harald van Dijk [Sat, 21 Nov 2020 17:20:20 +0000 (09:20 -0800)]
[X86] Include %rip for 32-bit RIP-relative relocs for x32
%rip was only included for 64-bit RIP-relative relocations, but needs to be included for 32-bit as well.
Reviewed By: MaskRay, RKSimon
Differential Revision: https://reviews.llvm.org/D91339
Simon Pilgrim [Sat, 21 Nov 2020 17:11:08 +0000 (17:11 +0000)]
MachineDominators.h - remove unused <vector> include
Simon Pilgrim [Sat, 21 Nov 2020 17:04:30 +0000 (17:04 +0000)]
DominanceFrontier - remove unused <vector> includes
Simon Pilgrim [Sat, 21 Nov 2020 16:50:50 +0000 (16:50 +0000)]
[X86] Regenerate vector-reduce-or-cmp.ll
Fix AVX512 prefixes to appease update_llc_test_checks.py
sameeran joshi [Thu, 5 Nov 2020 08:55:06 +0000 (14:25 +0530)]
[Flang][OpenMP][NFC][2/2] Reorder OmpStructureChecker and simplify it.
`OmpStructureChecker` has too much boilerplate code in source file.
This patch:
1. Use helpers from `check-directive-structure.h` and reduces the boilerplate.
2. Use TableGen infrastructure as much as possible.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D90834
Nikita Popov [Sat, 21 Nov 2020 16:36:57 +0000 (17:36 +0100)]
[BasicAA] Add recphi test with dynamic offset (NFC)
Currently, we don't recognize that %a an %p don't alias.
Michał Górny [Sun, 15 Nov 2020 17:36:22 +0000 (18:36 +0100)]
[lldb] Reland "Use translated full ftag values"
Translate between abridged and full ftag values in order to expose
the latter in the gdb-remote protocol while the former are used by
FXSAVE/XSAVE... This matches the gdb behavior.
The Shell/Register tests now rely on the new behavior, and therefore
are run on non-Darwin systems only. The Python (API) test relies
on the legacy behavior, and is run on Darwin only.
Differential Revision: https://reviews.llvm.org/D91504
Paul C. Anagnostopoulos [Mon, 16 Nov 2020 19:24:25 +0000 (14:24 -0500)]
[TableGen] [ISel Matcher Emitter] Rework with two passes: one to size, one to emit
Differential Revision: https://reviews.llvm.org/D91632
Faisal Vali [Sat, 21 Nov 2020 15:49:52 +0000 (09:49 -0600)]
[NFC, Refactor] Modernize enum FunctionDefinitionKind (DeclSpech.h) into a scoped enum
Reviewed by aaron.ballman, rsmith, wchilders
Highlights of review:
- avoid specifying an underlying type (unless such an enum is stored (or part of an abi?))
- avoid using enums as bit-fields, preferring unsigned bit-fields that we static_cast enumerators to. (MS's abi laysout enum bit-fields differently).
- clang-format, clang-format, clang-format.
https://reviews.llvm.org/D91035
Thank you!
Eugene Zhulenev [Sat, 21 Nov 2020 15:01:06 +0000 (07:01 -0800)]
[mlir] Fix async microbench integration test
Differential Revision: https://reviews.llvm.org/D91912
sameeran joshi [Sat, 21 Nov 2020 10:21:29 +0000 (15:51 +0530)]
[flang][openmp] Fix bug in `OmpClause::Hint` clause which was missing to generate inside in OMP.cpp.inc file.
Before this patch "Hint" isn't found inside the generated file.
./bin/llvm-tblgen --gen-directive-gen ../llvm-project/llvm/include/llvm/Frontend/OpenMP/OMP.td -I ../llvm-project/llvm/include/ > OMP.cpp.in
Reviewed By: clementval
Differential Revision: https://reviews.llvm.org/D91909
Eugene Zhulenev [Sat, 21 Nov 2020 11:50:05 +0000 (03:50 -0800)]
[mlir] AsynToLLVM: do no use op->getOperands() in conversion patterns
Differential Revision: https://reviews.llvm.org/D91910
Eugene Zhulenev [Sat, 21 Nov 2020 11:24:05 +0000 (03:24 -0800)]
[mlir] Add microbenchmark for linalg+async-parallel-for
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D91896
Kazushi (Jam) Marukawa [Thu, 19 Nov 2020 12:31:21 +0000 (21:31 +0900)]
[VE][NFC] Modify function order and simplify comments
Kazushi (Jam) Marukawa [Sun, 15 Nov 2020 01:08:10 +0000 (10:08 +0900)]
[VE] Correct types of return/argument values for getAdjustedFrameSize()
A getAdjustedFrameSize function may need to handle larger than 32 bits
integer, so change int to uint64_t.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91862
Tom Stellard [Mon, 16 Nov 2020 19:06:58 +0000 (11:06 -0800)]
GitHub Actions: Add job for automatically updating the main branch
Differential Revision: https://reviews.llvm.org/D91554
Tony [Fri, 13 Nov 2020 21:08:37 +0000 (21:08 +0000)]
[NFC][AMDGPU] Document kernel descriptor
- Document that the kernel descriptor defined is for code object V3.
Document that it also applies to earlier code object formats for CP.
- Document the deprecated bits in kernel descriptor.
Differential Revision: https://reviews.llvm.org/D91458
Kazushi (Jam) Marukawa [Sat, 21 Nov 2020 04:07:29 +0000 (13:07 +0900)]
[VE][NFC] Update missing bulk update tests to use typed sret
Nico Weber [Sat, 21 Nov 2020 03:32:31 +0000 (22:32 -0500)]
[mac/arm] Fix test/Driver/darwin-sdk-version.c on arm macs
Two invocations in this test used `-m64`, which on an arm mac means
arm64 in the triple, not x86_64.
Nico Weber [Sat, 21 Nov 2020 02:48:40 +0000 (21:48 -0500)]
[mac/arm] Fix clang/test/Sema/wchar.c on mac/arm hosts
Part of PR46644.
Matt Arsenault [Fri, 20 Nov 2020 23:16:11 +0000 (18:16 -0500)]
OpaquePtr: Make byval/sret types mandatory
Matt Arsenault [Tue, 20 Oct 2020 16:56:12 +0000 (12:56 -0400)]
AMDGPU: Fix counting kernel arguments towards register usage
Also use DataLayout to get type size. Relying on the IR type size is
also pretty broken here, since this won't perfectly capture how types
are legalized.
Kazu Hirata [Sat, 21 Nov 2020 02:08:05 +0000 (18:08 -0800)]
[Analysis] Use llvm::is_contained (NFC)
Arthur O'Dwyer [Wed, 18 Nov 2020 23:54:38 +0000 (18:54 -0500)]
Revert "Revert "[libc++] ADL-proof <vector> by adding _VSTD:: qualification on calls.""
This reverts commit
620adacf87a376ec536ccc66af59df5bb4dc3b38.
Fix: unsupport C++03 for the new test, define helpers before __swap_allocator
(1) Add _VSTD:: qualification to __swap_allocator.
(2) Add _VSTD:: qualification consistently to __to_address.
(3) Add some more missing _VSTD:: to <vector>, with a regression test.
This part is cleanup after
d9a4f936d05.
Note that a vector whose allocator actually runs afoul of any of these ADL calls will
likely also run afoul of simple things like `v1 == v2` (which is also an ADL call).
But, still, libc++ should be consistent in qualifying function calls wherever possible.
Relevant blog post: https://quuxplusone.github.io/blog/2019/09/26/uglification-doesnt-stop-adl/
Differential Revision: https://reviews.llvm.org/D91708
Valentin Clement [Sat, 21 Nov 2020 01:17:18 +0000 (20:17 -0500)]
[flang][openacc] Add clause validity tests for the host_data directive
Add some clause validity tests for the host_data directive to avoid future regressions.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D91889
Matt Arsenault [Fri, 20 Nov 2020 23:14:28 +0000 (18:14 -0500)]
Verifier: Fix assert when verifying non-pointer byval or preallocated
This would fail on a cast<PointerType> when verifying the attribute if
these attributes were incorrectly used with a non-pointer type.
Matt Arsenault [Sat, 21 Nov 2020 00:02:42 +0000 (19:02 -0500)]
OpaquePtr: Update more tests to use typed sret
Valentin Clement [Sat, 21 Nov 2020 01:04:54 +0000 (20:04 -0500)]
[flang][openacc] Add clause validity tests for the parallel directive
Add some clause validity tests for parallel directive.
Reviewed By: sameeranjoshi
Differential Revision: https://reviews.llvm.org/D91871
Aart Bik [Thu, 19 Nov 2020 20:56:30 +0000 (12:56 -0800)]
[mlir][sparse] refine optimization, add few more test cases
Adds tests for full sum reduction (tensors summed up into scalars)
and the well-known sampled-dense-dense-matrix-product. Refines
the optimizations rules slightly to handle the summation better.
Reviewed By: penpornk
Differential Revision: https://reviews.llvm.org/D91818
Evgenii Stepanov [Thu, 19 Nov 2020 22:34:56 +0000 (14:34 -0800)]
[hwasan] Implement error report callback.
Similar to __asan_set_error_report_callback, pass the entire report to a
user provided callback function.
Differential Revision: https://reviews.llvm.org/D91825
wlei [Sat, 21 Nov 2020 00:20:37 +0000 (16:20 -0800)]
[llvm-profgen][NFC]Fix build failure on different platform
see titile
Test Plan:
ninja & ninja check-llvm
Reviewed By: hoy
Differential Revision: https://reviews.llvm.org/D91897
Michael Jones [Tue, 17 Nov 2020 23:47:19 +0000 (23:47 +0000)]
[libc] Make more of the libc unit testing llvm independent
(WIP, hopefully I'll add more to this patch before submitting)
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D91665
Michael Jones [Fri, 13 Nov 2020 00:26:57 +0000 (00:26 +0000)]
[libc] Switch functions to using global headers
This switches all of the files in src/string, src/math, and
test/src/math from using relative paths (e.g. `#include “include/string.h”`)
to global paths (e.g. `#include <string.h>`) to make bringing up those
functions on other platforms, such as fuchsia, easier.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D91394
Samuel Giddins [Fri, 20 Nov 2020 23:11:34 +0000 (15:11 -0800)]
Don’t break before nested block param when prior param is not a block
Add ScopedTrace to verify methods in FormatTestObjC
Add tests from D17700
Reviewed By: keith, kastiglione
Differential Revision: https://reviews.llvm.org/D91669
Matt Arsenault [Fri, 20 Nov 2020 19:07:11 +0000 (14:07 -0500)]
OpaquePtr: Bulk update tests to use typed sret
wlei [Mon, 19 Oct 2020 17:19:08 +0000 (10:19 -0700)]
[CSSPGO][llvm-profgen] Instruction symbolization
This stack of changes introduces `llvm-profgen` utility which generates a profile data file from given perf script data files for sample-based PGO. It’s part of(not only) the CSSPGO work. Specifically to support context-sensitive with/without pseudo probe profile, it implements a series of functionalities including perf trace parsing, instruction symbolization, LBR stack/call frame stack unwinding, pseudo probe decoding, etc. Also high throughput is achieved by multiple levels of sample aggregation and compatible format with one stop is generated at the end. Please refer to: https://groups.google.com/g/llvm-dev/c/1p1rdYbL93s for the CSSPGO RFC.
This change adds the support of instruction symbolization. Given the RVA on an instruction pointer, a full calling context can be printed side-by-side with the disassembly code.
E.g.
```
Disassembly of section .text [0x0, 0x4a]:
<funcA>:
0: mov eax, edi funcA:0
2: mov ecx, dword ptr [rip] funcLeaf:2 @ funcA:1
8: lea edx, [rcx + 3] fib:2 @ funcLeaf:2 @ funcA:1
b: cmp ecx, 3 fib:2 @ funcLeaf:2 @ funcA:1
e: cmovl edx, ecx fib:2 @ funcLeaf:2 @ funcA:1
11: sub eax, edx funcLeaf:2 @ funcA:1
13: ret funcA:2
14: nop word ptr cs:[rax + rax]
1e: nop
<funcLeaf>:
20: mov eax, edi funcLeaf:1
22: mov ecx, dword ptr [rip] funcLeaf:2
28: lea edx, [rcx + 3] fib:2 @ funcLeaf:2
2b: cmp ecx, 3 fib:2 @ funcLeaf:2
2e: cmovl edx, ecx fib:2 @ funcLeaf:2
31: sub eax, edx funcLeaf:2
33: ret funcLeaf:3
34: nop word ptr cs:[rax + rax]
3e: nop
<fib>:
40: lea eax, [rdi + 3] fib:2
43: cmp edi, 3 fib:2
46: cmovl eax, edi fib:2
49: ret fib:8
```
Test Plan:
ninja check-llvm
Reviewed By: wenlei, wmi
Differential Revision: https://reviews.llvm.org/D89715
wlei [Mon, 19 Oct 2020 17:02:05 +0000 (10:02 -0700)]
[CSSPGO][llvm-profgen] Disassemble text sections
This stack of changes introduces `llvm-profgen` utility which generates a profile data file from given perf script data files for sample-based PGO. It’s part of(not only) the CSSPGO work. Specifically to support context-sensitive with/without pseudo probe profile, it implements a series of functionalities including perf trace parsing, instruction symbolization, LBR stack/call frame stack unwinding, pseudo probe decoding, etc. Also high throughput is achieved by multiple levels of sample aggregation and compatible format with one stop is generated at the end. Please refer to: https://groups.google.com/g/llvm-dev/c/1p1rdYbL93s for the CSSPGO RFC.
This change enables disassembling the text sections to build various address maps that are potentially used by the virtual unwinder. A switch `--show-disassembly` is being added to print the disassembly code.
Like the llvm-objdump tool, this change leverages existing LLVM components to parse and disassemble ELF binary files. So far X86 is supported.
Test Plan:
ninja check-llvm
Reviewed By: wmi, wenlei
Differential Revision: https://reviews.llvm.org/D89712
wlei [Mon, 19 Oct 2020 04:36:54 +0000 (21:36 -0700)]
[CSSPGO][llvm-profgen] Parse mmap events from perf script
This stack of changes introduces `llvm-profgen` utility which generates a profile data file from given perf script data files for sample-based PGO. It’s part of(not only) the CSSPGO work. Specifically to support context-sensitive with/without pseudo probe profile, it implements a series of functionalities including perf trace parsing, instruction symbolization, LBR stack/call frame stack unwinding, pseudo probe decoding, etc. Also high throughput is achieved by multiple levels of sample aggregation and compatible format with one stop is generated at the end. Please refer to: https://groups.google.com/g/llvm-dev/c/1p1rdYbL93s for the CSSPGO RFC.
As a starter, this change sets up an entry point by introducing PerfReader to load profiled binaries and perf traces(including perf events and perf samples). For the event, here it parses the mmap2 events from perf script to build the loader snaps, which is used to retrieve the image load address in the subsequent perf tracing parsing.
As described in llvm-profgen.rst, the tool being built aims to support multiple input perf data (preprocessed by perf script) as well as multiple input binary images. It should also support dynamic reload/unload shared objects by leveraging the loader snaps being built by this change
Reviewed By: wenlei, wmi
Differential Revision: https://reviews.llvm.org/D89707
Amara Emerson [Fri, 20 Nov 2020 21:36:49 +0000 (13:36 -0800)]
[AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal.
Also fix a selection issue for this which was using LLT::isScalar() when it
should have been using !isVector(), add test for that too.
Richard Smith [Fri, 23 Oct 2020 02:29:36 +0000 (19:29 -0700)]
Demangling support for class type non-type template parameter extensions.
The extensions in question are described in:
https://github.com/itanium-cxx-abi/cxx-abi/issues/47
https://github.com/itanium-cxx-abi/cxx-abi/issues/63
Differential Revision: https://reviews.llvm.org/D90003
Alexey Bataev [Fri, 20 Nov 2020 21:03:53 +0000 (13:03 -0800)]
[SLP][NFC]Fix assert condition in newTreeEntry, NFC.
Vitaly Buka [Fri, 20 Nov 2020 11:51:13 +0000 (03:51 -0800)]
[msan] unpoison_file from fclose and fflash
Also unpoison IO_write_base/_IO_write_end buffer
memcpy from fclose and fflash can copy internal bytes without metadata into user memory.
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D91858
Nathan Lanza [Fri, 20 Nov 2020 20:36:29 +0000 (15:36 -0500)]
Revert "[lldb] add a missing dependency on intrinsics_gen"
This reverts commit
137ff7331705179c83533a074d800c481b7df1ac.
This belongs in Apple's Swift fork since this is a direct fix for
unified Swift + llvm + lldb builds.
Zbigniew Sarbinowski [Fri, 20 Nov 2020 19:46:21 +0000 (14:46 -0500)]
Guard init_priority attribute within libc++
Not all platforms support priority attribute. I'm moving conditional definition of this attribute to `include/__config`.
Reviewed By: #libc, aaron.ballman
Differential Revision: https://reviews.llvm.org/D91565
Craig Topper [Fri, 20 Nov 2020 20:08:16 +0000 (12:08 -0800)]
[RISCV] Put RV32 before RV64 in the ValueTypeByHwMode and RegInfoByHwMode lists in RISCVRegisterInfo.td
Addresses post-commit feedback from
77e25b5bc8860e23395f617dcca4940489f6355c
Thomas Raoux [Mon, 16 Nov 2020 18:52:10 +0000 (10:52 -0800)]
[mlir][vector] Add transfer_op LoadToStore forwarding and deadStore optimizations
Add transformation to be able to forward transfer_write into transfer_read
operation and to be able to remove dead transfer_write when a transfer_write is
overwritten before being read.
Differential Revision: https://reviews.llvm.org/D91321
Sam McCall [Fri, 20 Nov 2020 19:51:58 +0000 (20:51 +0100)]
[clangd] semanticTokens: fields are 'property', not 'member'
This isn't obvious, but vscode maps member as 'entity.name.function.member',
so it's really for member functions.
Fixes https://github.com/clangd/vscode-clangd/issues/105
Alexey Bataev [Thu, 19 Nov 2020 17:16:25 +0000 (09:16 -0800)]
[OPENMP]Use the real pointer value as base, not indexed value.
After fix for PR48174 the base pointer for pointer-based
array-sections/array-subscripts will be emitted as `&ptr[idx]`, but
actually it should be just `ptr`, i.e. the address stored in the ponter
to point correctly to the beginning of the array. Currently it may lead
to a crash in the runtime.
Differential Revision: https://reviews.llvm.org/D91805
Craig Topper [Fri, 20 Nov 2020 18:42:51 +0000 (10:42 -0800)]
[RISCV] Remove RV32 HwMode. Use DefaultMode for RV32
Prior to this the DefaultMode was never selected, but RISCVGenDAGISel.inc, RISCVGenRegisterInfo.inc, RISCVGenGlobalISel.inc all ended up with extra table entries for that mode.
This patch removes the RV32 and uses DefaultMode for RV32. This impressively reduces the size of my release+asserts llc binary by about 270K. About 15K from RISCVGenDAGISel.inc, 1-2K from RISCVGenRegisterInfo.inc, but the vast majority from RISCVGenGlobalISel.inc.
Differential Revision: https://reviews.llvm.org/D90973
Alexey Bataev [Tue, 17 Nov 2020 17:30:33 +0000 (09:30 -0800)]
[OPENMP]Honor constantness of captured variables.
Fixes bug reported via Stackoverflow:
https://stackoverflow.com/questions/
64179168/clang-overload-resolution-failure-with-templates-and-openmp-collapse
Need to honor constantness of private/target variables to make the code
compilable.
Differential Revision: https://reviews.llvm.org/D91644
Matt Arsenault [Fri, 20 Nov 2020 15:52:27 +0000 (10:52 -0500)]
OpaquePtr: Bulk update tests to use typed byval
Upgrade of the IR text tests should be the only thing blocking making
typed byval mandatory. Partially done through regex and partially
manual.
Hongtao Yu [Thu, 10 Sep 2020 18:21:19 +0000 (11:21 -0700)]
[CSSPGO] MIR target-independent pseudo instruction for pseudo-probe intrinsic
This change introduces a MIR target-independent pseudo instruction corresponding to the IR intrinsic llvm.pseudoprobe for pseudo-probe block instrumentation. Please refer to https://reviews.llvm.org/D86193 for the whole story.
An `llvm.pseudoprobe` intrinsic call will be lowered into a target-independent operation named `PSEUDO_PROBE`. Given the following instrumented IR,
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
call void @llvm.pseudoprobe(i64
837061429793323041, i64 1)
br i1 %cmp, label %bb1, label %bb2
bb1:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 2)
br label %bb3
bb2:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 3)
br label %bb3
bb3:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 4)
ret void
}
```
the corresponding MIR is shown below. Note that block `bb3` is duplicated into `bb1` and `bb2` where its probe is duplicated too. This allows for an accurate execution count to be collected for `bb3`, which is basically the sum of the counts of `bb1` and `bb2`.
```
bb.0.bb0:
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
TEST32rr killed renamable $edi, renamable $edi, implicit-def $eflags
PSEUDO_PROBE
837061429793323041, 1, 0
$edi = MOV32ri 1, debug-location !13; test.c:0
JCC_1 %bb.1, 4, implicit $eflags
bb.2.bb2:
PSEUDO_PROBE
837061429793323041, 3, 0
PSEUDO_PROBE
837061429793323041, 4, 0
$rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp
RETQ
bb.1.bb1:
PSEUDO_PROBE
837061429793323041, 2, 0
PSEUDO_PROBE
837061429793323041, 4, 0
$rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp
RETQ
```
The target op PSEUDO_PROBE will be converted into a piece of binary data by the object emitter with no machine instructions generated. This is done in a different patch.
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D86495
Craig Topper [Fri, 20 Nov 2020 18:29:01 +0000 (10:29 -0800)]
[RISCV] Custom type legalize i32 bswap/bitreverse to GREVIW on RV64 with Zbp extension
Previously we required a sra to pattern match these properly in isel. If the consumer didn't need the result sign extended we'll have an srl instead of sra and fail to match.
This patch switches to custom legalizing to GREVIW using portions of D91259.
Differential Revision: https://reviews.llvm.org/D91457
Hongtao Yu [Wed, 18 Nov 2020 20:42:51 +0000 (12:42 -0800)]
[CSSPGO] IR intrinsic for pseudo-probe block instrumentation
This change introduces a new IR intrinsic named `llvm.pseudoprobe` for pseudo-probe block instrumentation. Please refer to https://reviews.llvm.org/D86193 for the whole story.
A pseudo probe is used to collect the execution count of the block where the probe is instrumented. This requires a pseudo probe to be persisting. The LLVM PGO instrumentation also instruments in similar places by placing a counter in the form of atomic read/write operations or runtime helper calls. While these operations are very persisting or optimization-resilient, in theory we can borrow the atomic read/write implementation from PGO counters and cut it off at the end of compilation with all the atomics converted into binary data. This was our initial design and we’ve seen promising sample correlation quality with it. However, the atomics approach has a couple issues:
1. IR Optimizations are blocked unexpectedly. Those atomic instructions are not going to be physically present in the binary code, but since they are on the IR till very end of compilation, they can still prevent certain IR optimizations and result in lower code quality.
2. The counter atomics may not be fully cleaned up from the code stream eventually.
3. Extra work is needed for re-targeting.
We choose to implement pseudo probes based on a special LLVM intrinsic, which is expected to have most of the semantics that comes with an atomic operation but does not block desired optimizations as much as possible. More specifically the semantics associated with the new intrinsic enforces a pseudo probe to be virtually executed exactly the same number of times before and after an IR optimization. The intrinsic also comes with certain flags that are carefully chosen so that the places they are probing are not going to be messed up by the optimizer while most of the IR optimizations still work. The core flags given to the special intrinsic is `IntrInaccessibleMemOnly`, which means the intrinsic accesses memory and does have a side effect so that it is not removable, but is does not access memory locations that are accessible by any original instructions. This way the intrinsic does not alias with any original instruction and thus it does not block optimizations as much as an atomic operation does. We also assign a function GUID and a block index to an intrinsic so that they are uniquely identified and not merged in order to achieve good correlation quality.
Let's now look at an example. Given the following LLVM IR:
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
br i1 %cmp, label %bb1, label %bb2
bb1:
br label %bb3
bb2:
br label %bb3
bb3:
ret void
}
```
The instrumented IR will look like below. Note that each `llvm.pseudoprobe` intrinsic call represents a pseudo probe at a block, of which the first parameter is the GUID of the probe’s owner function and the second parameter is the probe’s ID.
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
call void @llvm.pseudoprobe(i64
837061429793323041, i64 1)
br i1 %cmp, label %bb1, label %bb2
bb1:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 2)
br label %bb3
bb2:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 3)
br label %bb3
bb3:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 4)
ret void
}
```
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D86490
Pete Steinfeld [Fri, 20 Nov 2020 18:33:21 +0000 (10:33 -0800)]
Update OptionComparison.md
Craig Topper [Fri, 20 Nov 2020 18:11:34 +0000 (10:11 -0800)]
[RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb.
This should result in better utilization of RORIW since we
don't need to look for a SIGN_EXTEND_INREG that may not exist.
Also remove rotl/rotr isel matching to GREVI and just prefer RORI.
This is to keep consistency so we don't have to match ROLW/RORW
to GREVIW as well. I imagine RORI/RORIW performance will be the
same or better than GREVI.
Differential Revision: https://reviews.llvm.org/D91449
Simon Pilgrim [Fri, 20 Nov 2020 18:07:33 +0000 (18:07 +0000)]
[X86][AVX] LowerADDSAT_SUBSAT - avoid X86ISD::BLENDV in UADDSAT/USUBSAT v8i32/v4i64 lowering
Use the OR(CMP,ADD) / AND(CMP,SUB) patterns like we do on SSE targets.
Enable custom lowering for v8i32/v4i64 and generalize the 128-bit lowering code for any vector size - this also lets us use the slightly cheaper codegen for icmp_ugt instead of umin/umax.
William S. Moses [Fri, 20 Nov 2020 18:05:09 +0000 (19:05 +0100)]
[MLIR] Correct block merge bug
Block merging in MLIR will incorrectly merge blocks with operations whose values are used outside of that block. This change forbids this behavior and provides a test where it is illegal to perform such a merge.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D91745
Yitzhak Mandelbaum [Fri, 20 Nov 2020 16:27:22 +0000 (16:27 +0000)]
[libTooling] Update Transformer's `node` combinator to include the trailing semicolon for decls.
Currently, `node` only includes the semicolon for (some) statements. However,
declarations have the same issue of (potentially) trailing semicolons, so `node`
should behave the same for them.
Differential Revision: https://reviews.llvm.org/D91872
Craig Topper [Fri, 20 Nov 2020 17:41:06 +0000 (09:41 -0800)]
[SelectionDAG][X86][PowerPC][Mips] Replace the default implementation of LowerOperationWrapper with the X86 and PowerPC version.
The default version only works if the returned node has a single
result. The X86 and PowerPC versions support multiple results
and allow a single result to be returned from a node with
multiple outputs. And allow a single result that is not result 0
of the node.
Also replace the Mips version since the new version should work
for it. The original version handled multiple results, but only
if the new node and original node had the same number of results.
Differential Revision: https://reviews.llvm.org/D91846
Alex Zinenko [Fri, 20 Nov 2020 17:50:52 +0000 (18:50 +0100)]
[mlir] add canonicalization patterns for trivial SCF 'for' and 'if'
Add canoncalization patterns to remove zero-iteration 'for' loops, replace
single-iteration 'for' loops with their bodies; remove known-false conditionals
with no 'else' branch and replace conditionals with known value by the
respective region. Although similar transformations are performed at the CFG
level, not all flows reach that level, e.g., the GPU flow may want to remove
single-iteration loops before deciding on loop mapping to thread dimensions.
Reviewed By: herhut
Differential Revision: https://reviews.llvm.org/D91865
Dave Lee [Wed, 18 Nov 2020 21:55:47 +0000 (13:55 -0800)]
[lldb] Add examples and reword source-map help string
Update the help string for `target.source-map` to remove the use of the word
"duple" and to add examples. Additionally I rewrote parts with the goal of
making the description more concrete.
rdar://
68736012
Differential Revision: https://reviews.llvm.org/D91742
Arthur Eubanks [Thu, 19 Nov 2020 23:52:21 +0000 (15:52 -0800)]
[Hexagon][NewPM] Port -hexagon-loop-idiom and add to pipeline
Fixes pmpy-mod.ll under NPM
Reviewed By: kparzysz
Differential Revision: https://reviews.llvm.org/D91829
Stella Stamenova [Fri, 20 Nov 2020 17:26:58 +0000 (09:26 -0800)]
[mlir] Expose parseDimAndSymbolList from affineops.h
This was removed from ops.h, but it is used by onnx-mlir
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D91830
Andrew Wei [Fri, 20 Nov 2020 16:35:53 +0000 (00:35 +0800)]
[DeadMachineInstrctionElim] Post order visit all blocks and Iteratively run DeadMachineInstructionElim pass until nothing dead
Patched by: guopeilin
Reviewed By: hliao,rampitec
Differential Revision: https://reviews.llvm.org/D91513