Patrick Delaunay [Thu, 4 Jun 2020 12:30:28 +0000 (14:30 +0200)]
gpio: stmfx: rename function used to change pin configuration
Rename the two function used to change the pin configuration
from stmfx_pinctrl_.. stmfx_conf_... to clarify the function usage.
No functional change.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 4 Jun 2020 12:30:27 +0000 (14:30 +0200)]
gpio: stmfx: move function to prepare new ops introduction
Move the functions stmfx_pinctrl_set_pupd and stmfx_pinctrl_set_type;
they can be used by the new ops get_dir_flags and set_dir_flags introduced
by next patch.
No functional change.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 4 Jun 2020 12:30:26 +0000 (14:30 +0200)]
gpio: stm32: add ops get_dir_flags
Add ops get_dir_flags() to read dir flags from GPIO registers.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 4 Jun 2020 12:30:25 +0000 (14:30 +0200)]
gpio: stm32: add ops set_dir_flags
Manage flags for GPIO configuration:
- open_drain, open_source, push_pull
- pull_up, pull_down
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 4 Jun 2020 12:30:24 +0000 (14:30 +0200)]
board: stm32mp1: update the gpio hog support
This patch updates the current gpio hog implementation and uses
the new API gpio_hog_probe_all(), activated with CONFIG_GPIO_HOG.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 4 Jun 2020 12:30:23 +0000 (14:30 +0200)]
configs: stm32mp1: activate CONFIG_GPIO_HOG
This patch activates the new configuration CONFIG_GPIO_HOG.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:49 +0000 (12:19 +0200)]
board: stm32mp1: move the function board_debug_uart_init in spl.c
Move the debug function board_debug_uart_init in spl.c
as the debug_uart_init() function is called in arch_cpu_init()
only for SPL and remove the board.c file.
For TFABOOT, the UART TX pin configuration is done in TF-A.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:48 +0000 (12:19 +0200)]
ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL
This patch allows to switch the CPU frequency to 800MHz on the
ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM
using the STM32MP15x SOC and when it is supported by the HW
(for STM32MP15xD and STM32MP15xF).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:47 +0000 (12:19 +0200)]
board: stm32mp1: update vddcore in SPL
For board using STPMIC1, the vddcore is provided by BUCK1 of STPMIC1
and need to be updated for 800MHz support and only after the clock
tree initialization.
The VDDCORE voltage value is provided by clock driver, saved in global
variable opp_voltage_mv and udpated in SPL board_early_init_f(),
just after clock tree initialization.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:46 +0000 (12:19 +0200)]
board: st: stpmic1: add function stpmic1_init
Add a function stmpic_init to early initialize the PMIC STPMIC1
- keep vdd on during the reset cycle (to avoid issue when backup battery
is absent)
- Check if debug is enabled to program PMIC according to the bit
This patch allows to remove the compilation of spl.c file from stm32mp1
board in dh_stm32mp1.
CONFIG_SPL_BOARD_INIT is removed as the new function is called earlier
in SPL, in the function board_early_init_f.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:45 +0000 (12:19 +0200)]
arm: stm32mp: add weak function to save vddcore
Add a weak functions to save the vddcore voltage value provided
in the OPP node when the clock tree is initialized.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:44 +0000 (12:19 +0200)]
stm32mp1: clk: configure pll1 with OPP
The PLL1 node (st,pll1) is optional in device tree, the max supported
frequency define in OPP node is used when the node is absent.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:43 +0000 (12:19 +0200)]
board: st: create common file stpmic1.c
Move function board_ddr_power_init() in a new file stpmic1 in
board/st/common to avoid duplicated code in each board using
stpmic1
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:42 +0000 (12:19 +0200)]
ARM: dts: stm32: add cpufreq support on stm32mp15x
This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses
operating points V2 bindings (no legacy). Nvmem cells have to be used to
know the chip version and then which OPPs are available. Note that STM32
cpufreq driver is mainly based on "cpufreq-dt" driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:41 +0000 (12:19 +0200)]
arm: stm32mp: spl: add bsec driver in SPL
Add the bsec driver in SPL, as it is needed by SOC part number detection
to found the supported OPP.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 14 May 2020 13:00:23 +0000 (15:00 +0200)]
net: dwc_eth_qos: update the compatible supported for STM32
Update the compatible associated with the STM32 MPU glue
in the DWC ethernet driver.
The supported compatible is the specific "st,stm32mp1-dwmac"
as indicated in Linux binding
Documentation/devicetree/bindings/net/stm32-dwmac.txt
and not the "snps,dwmac-4.20a" only used to the select IP
version.
This glue is implemented in Linux kernel in:
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
For information in stm32mp151.dtsi, the 2 compatibles are
supported:
ethernet0: ethernet@
5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
...
};
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Tom Rini [Mon, 6 Jul 2020 21:57:14 +0000 (17:57 -0400)]
Revert "riscv: sifive: fu540: Add gpio-restart support"
As part of merging the next branch in to master, the sifive_fu540 will
fail to link:
riscv64-linux-ld.bfd: lib/built-in.o: in function `panic_finish':
lib/panic.c:28: undefined reference to `do_reset'
make[2]: *** [spl/u-boot-spl] Error 1
make[1]: *** [spl/u-boot-spl] Error 2
make: *** [sub-make] Error 2
And while the "fix the build" option of enabling CONFIG_SPL_SYSRESET may
solve the issue, it is unclear that it is the correct path exactly. For
the moment, I am reverting this commit and take a "revert the revert"
and proper fix as soon as it's available.
This reverts commit
cdae446461191714d692190da1ad4344398adc57.
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Patrick Delaunay [Wed, 1 Jul 2020 12:56:10 +0000 (14:56 +0200)]
video: restore CONFIG_VIDCONSOLE_AS_LCD as boolean
This patch restores CONFIG_VIDCONSOLE_AS_LCD as boolean
and introduce a separate sting as CONFIG_VIDCONSOLE_AS_NAME
to search this string in stdout used as videoconsole.
This patch avoid issue with board defconfig or code expecting
CONFIG_VIDCONSOLE_AS_LCD as boolean.
Fixes:
22b897a12323 ("video: extend stdout video console work-around for 'vga'")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Tom Rini [Mon, 6 Jul 2020 19:46:38 +0000 (15:46 -0400)]
Merge branch 'next'
Merge all outstanding changes from the current next branch in now that
we have released.
Tom Rini [Mon, 6 Jul 2020 19:22:53 +0000 (15:22 -0400)]
Prepare v2020.07
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 6 Jul 2020 17:54:25 +0000 (13:54 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 5 Jul 2020 22:13:12 +0000 (18:13 -0400)]
Merge tag 'efi-2020-10-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi into next
Pull request for UEFI sub-system for efi-2020-10-rc1
This series comprises error corrections for the UEFI subsystem:
* correct consideration of timestamps for variable authentication
* correct collection of data regions for code authentication
* correct unit tests to test loading dbx
* enable FAT_WRITE as required by the UEFI spec
The boot manager uses log functions instead of printf() and debug().
The UEFI intialization state is exported.
Tom Rini [Sun, 5 Jul 2020 22:03:32 +0000 (18:03 -0400)]
Merge branch '2020-07-01-kconfig-etc-updates' into next
- Resync Kconfiglib with the v14.1.0 release.
- Re-sync our <linux/compiler*h> files with v5.7-rc5 from upstream.
- Fully resync checkpatch.pl with v5.7 release.
To safely to all of the above, we have a few bugfixes about functions
that need a 'static inline' but weren't. We also stop setting
CROSS_COMPILE in arch/*/config.mk. Finally, with the above changes
boards can now opt-in to optimizing inlining and we do this for the
socfpga stratix10 platform for space savings.
Tom Rini [Sun, 5 Jul 2020 12:06:52 +0000 (08:06 -0400)]
Merge branch '2020-07-05-gpio-regression-fix'
- Merge a fix to the gpio uclass and a test for it.
Heiko Schocher [Fri, 22 May 2020 09:08:58 +0000 (11:08 +0200)]
sandbox, test: add test for GPIO_HOG function
currently gpio hog function is not tested with "ut dm gpio"
so add some basic tests for gpio hog functionality.
For this enable GPIO_HOG in sandbox_defconfig, add
in DTS some gpio hog entries, and add testcase in
"ut dm gpio" command.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Schocher [Fri, 22 May 2020 09:08:56 +0000 (11:08 +0200)]
gpio-uclass.c: save the GPIOD flags also in the gpio descriptor
save the GPIOD_ flags also in the gpio descriptor.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Fixes:
788ea834124b ("gpio: add function _dm_gpio_set_dir_flags")
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Walter Lozano <walter.lozano@collabora.com>
Heinrich Schuchardt [Sat, 21 Mar 2020 19:45:50 +0000 (20:45 +0100)]
efi_loader: imply FAT, FAT_WRITE
The UEFI spec requires support for the FAT file system.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 19 Mar 2020 18:21:58 +0000 (18:21 +0000)]
efi_loader: export initialization state
Export the UEFI sub-system initialization state. This will allow to treat
the setting of UEFI variables during and after initialization differently.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Tue, 30 Jun 2020 10:02:14 +0000 (12:02 +0200)]
efi_loader: rtc_mktime() called twice
Don't call rtc_mktime() twice with the same argument in
efi_variable_authenticate().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 31 May 2020 08:07:31 +0000 (10:07 +0200)]
efi_loader: use log function in boot manager
When booting via the boot manager use log function for user messages
instead of printf() and debug().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 1 Jul 2020 13:32:47 +0000 (15:32 +0200)]
efi_loader: time based authentication
When overwriting an existing time base authenticated variable we should
compare to the preceding time value and not to the start of the epoch.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 1 Jul 2020 10:44:00 +0000 (12:44 +0200)]
efi_loader: add missing validation of timestamp
The UEFI specification requires that when UEFI variables are set using time
based authentication we have to check that unused fields of the timestamp
are zero
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 1 Jul 2020 18:01:53 +0000 (20:01 +0200)]
test: provide tests for efi_image_region_add()
Provide unit tests for efi_image_region_add().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 1 Jul 2020 18:01:52 +0000 (20:01 +0200)]
efi_loader: fix efi_image_region_add()
Use start and end address consistently as half-open interval.
Simplify the code.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Fri, 3 Jul 2020 16:00:36 +0000 (12:00 -0400)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- sbi: Add newline to error message
- fu540: dts: Correct reg size of otp and dmc nodes
- Enhance reserved memory fixup about PMP information passed from OpenSBI
- sifive: fu540: Add gpio-restart support
- qemu-riscv: Update QEMU run command
- Assorted fixes related to reserved memory
- fu540: enable all cache ways from U-Boot proper
- use log functions in fdt_fixup
Heinrich Schuchardt [Thu, 2 Jul 2020 06:25:46 +0000 (08:25 +0200)]
test: correct time stamps for UEFI authentication
A time authenticated variable cannot be overwritten with another value
with the same time stamp. So we must ensure the correct sequence of time
stamps when generating out test data.
Using parameter -t for sign-efi-sig-list gives reproducible results and
avoids sleep statements.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
AKASHI Takahiro [Tue, 9 Jun 2020 05:09:43 +0000 (14:09 +0900)]
test/py: efi_secboot: fix test case 1g of test_authvar
In the test case (1g) of test_authvar, "db" is mistakenly used,
and it ends up being the exact same as (1f).
So correct it as "dbx" test case.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
AKASHI Takahiro [Tue, 9 Jun 2020 05:09:42 +0000 (14:09 +0900)]
test/py: efi_secboot: remove all "re.search"
Currently, we don't use any regular expression in matching outputs from
U-Boot. Since its use is just redundant, we can remove all.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
AKASHI Takahiro [Tue, 9 Jun 2020 05:09:35 +0000 (14:09 +0900)]
efi_loader: image_loader: replace debug to EFI_PRINT
Just for style consistency, replace all the uses of debug() to
EFI_PRINT() in efi_image_loader.c.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
AKASHI Takahiro [Tue, 9 Jun 2020 05:09:34 +0000 (14:09 +0900)]
efi_loader: variable: replace debug to EFI_PRINT
Just for style consistency, replace all the uses of debug() to
EFI_PRINT in efi_variable.c.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
AKASHI Takahiro [Tue, 9 Jun 2020 05:09:33 +0000 (14:09 +0900)]
efi_loader: signature: replace debug to EFI_PRINT
Just for style consistency, replace all the uses of debug to
EFI_PRINT in efi_signature.c
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
AKASHI Takahiro [Tue, 9 Jun 2020 05:09:32 +0000 (14:09 +0900)]
Revert "test: stabilize test_efi_secboot"
This reverts commit
5827c2545849441dd60467565aac11964259972f.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
AKASHI Takahiro [Tue, 9 Jun 2020 05:09:31 +0000 (14:09 +0900)]
efi_loader: change efi objects initialization order
The simplest solution to revert the commit
b32ac16f9a32 ("test/py: fix
test_efi_secboot/conftest.py") is to move efi_console_register()
forward before efi_disk_register().
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Tue, 30 Jun 2020 09:30:59 +0000 (11:30 +0200)]
riscv: use log functions in fdt_fixup
Replace printf() and debug() by log_err() and log_debug().
"No reserved memory region found in source FDT\n" is not an error but a
debug information.
%s/can not/cannot/ - use the more common spelling.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Pragnesh Patel [Fri, 29 May 2020 06:44:51 +0000 (12:14 +0530)]
riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Atish Patra [Wed, 24 Jun 2020 21:56:15 +0000 (14:56 -0700)]
riscv: Use optimized version of fdtdec_get_addr_size_no_parent
fdtdec_get_addr_size_no_parent is not an optimized version if parent
node is already available with the caller.
Use fdtdec_get_addr_size_auto_parent to read the "reg" property
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Atish Patra [Wed, 24 Jun 2020 21:56:14 +0000 (14:56 -0700)]
riscv: Do not return error if reserved node already exists
Not all errors are fatal. If a reserved memory node already exists in the
destination device tree, we can continue to boot without failing.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Bin Meng [Tue, 23 Jun 2020 12:23:15 +0000 (05:23 -0700)]
doc: qemu-riscv: Update QEMU run command
Explicitly pass the "-bios" option to QEMU to run U-Boot, instead
of the "-kernel" option, as we know that "-bios" behavior will be
changed since QEMU 5.1.0.
This also updates validated QEMU version to 5.0.0.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Bin Meng [Tue, 23 Jun 2020 05:29:46 +0000 (22:29 -0700)]
riscv: sifive: fu540: Add gpio-restart support
The HiFive Unleashed board wires GPIO pin#10 to the input of the
system reset signal. This adds gpio reboot support.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Bin Meng [Tue, 23 Jun 2020 05:29:44 +0000 (22:29 -0700)]
riscv: Do not build reset.c if SYSRESET is on
SYSRESET uclass driver already provides all the reset APIs, hence
exclude our own ad-hoc reset.c implementation.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tom Rini [Thu, 2 Jul 2020 13:53:34 +0000 (09:53 -0400)]
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next
- Add Sipeed Maix support
- Update clock handler and proper cpu features
Bin Meng [Fri, 26 Jun 2020 01:16:08 +0000 (18:16 -0700)]
riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE
Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the
reserved memory node for PMP protected memory regions. All RISC-V
boards need to copy the reserved memory node from the device tree
provided by the firmware to the device tree used by U-Boot.
Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Fri, 26 Jun 2020 01:16:07 +0000 (18:16 -0700)]
riscv: Expand the DT size before copy reserved memory node
The FDT blob might not have sufficient space to hold a copy of
reserved memory node. Expand it before the copy.
Reported-by: Rick Chen <rick@andestech.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Fri, 26 Jun 2020 01:16:06 +0000 (18:16 -0700)]
riscv: Avoid the reserved memory fixup if src and dst point to the same place
The copy of reserved memory node from source dtb to destination dtb
can be avoided if they point to the same place. This is useful when
OF_PRIOR_STAGE is used.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Bin Meng [Tue, 9 Jun 2020 03:28:26 +0000 (20:28 -0700)]
riscv: fu540: dts: Correct reg size of otp and dmc nodes
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Bin Meng [Tue, 9 Jun 2020 03:28:25 +0000 (20:28 -0700)]
riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Sean Anderson [Sat, 6 Jun 2020 19:26:03 +0000 (15:26 -0400)]
riscv: sbi: Add newline to error message
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tom Rini [Tue, 16 Jun 2020 14:29:46 +0000 (10:29 -0400)]
checkpatch.pl: Fully re-sync with v5.7
While commit
048a648298b1 ("checkpatch.pl: Update to v5.7") largely
re-syncs us with checkpatch.pl from v5.7 there are a number of things
missing still. Re-copy the script and again take care to keep our
allowed debug prints and now localized checks intact.
Fixes:
048a648298b1 ("checkpatch.pl: Update to v5.7")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 18 May 2020 18:48:00 +0000 (14:48 -0400)]
kconfig: show compiler version text in the top comment
This is a side-port of commit
21c54b774744 ("kconfig: show compiler
version text in the top comment") from Linux:
"The kernel configuration phase is now tightly coupled with the compiler
in use. It will be nice to show the compiler information in Kconfig."
We have already had the required makefile logic for this and had not
included printing the value in various user and file visible places.
Cc: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:09 +0000 (08:30 -0400)]
socfpga: Enable optimized inlining on stratix10
Enable the new CONFIG_OPTIMIZE_INLINING and CONFIG_SPL_OPTIMIZE_INLINING
options for this platform. With gcc-9.2 from kernel.org this saves us
1784 bytes in U-Boot and 80 bytes in SPL.
Cc: Marek Vasut <marex@denx.de>
Cc: Chin-Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinh.nguyen@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Vasut <marex@denx.de>
Tom Rini [Thu, 14 May 2020 12:30:08 +0000 (08:30 -0400)]
compilers: Introduce options for forcing inlining on SPL/TPL
There are cases where when we allow the compiler to decide about making
inline decisions rather than forcing them it can save us space.
For now, we keep the default values for inlining that we have had
historically.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:07 +0000 (08:30 -0400)]
compiler_types.h: Re-introduce CONFIG_OPTIMIZE_INLINING for U-Boot
In the Linux kernel, support for forcing inline functions to be made
inline, rather than allowing the compiler to make its own choice has
been removed. With respect to performance, modern GCC (and Clang) do a
good job at deciding when to, or not to, inline code and there are no
run-time requirements in Linux anymore.
There is one downside to this, which is final binary size. On average
in U-Boot removing this support grows SPL by almost 1 kilobyte. But
there are cases where it shrinks the binary by making better inline
choices than we had forced.
Start by re-introducing CONFIG_OPTIMIZE_INLINING as a global which
essentially reverts
889b3c1245de ("compiler: remove CONFIG_OPTIMIZE_INLINING entirely")
from Linux.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:06 +0000 (08:30 -0400)]
compiler*.h: sync include/linux/compiler*.h with Linux 5.7-rc5
Copy these from Linux v5.7-rc5 tag.
This brings in some handy new attributes and is otherwise important to
keep in sync.
We drop the reference to smp_read_barrier_depends() as it is not
relevant on the architectures we support at this time, based on where
it's implemented in Linux today. We drop the call to kasan_check_read()
as that is not relevant to U-Boot as well.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 1 Jul 2020 15:46:45 +0000 (11:46 -0400)]
pci: rockchip: Mark inline functions as static inline
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:05 +0000 (08:30 -0400)]
socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA case
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Vasut <marex@denx.de>
Tom Rini [Thu, 14 May 2020 12:30:04 +0000 (08:30 -0400)]
x86: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our <linux/compiler.h> to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/x86/include/asm/atomic.h to the other macros.
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 14 May 2020 12:30:03 +0000 (08:30 -0400)]
tegra: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our <linux/compiler.h> to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/arm/mach-tegra/ivc.c to the other macros.
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:02 +0000 (08:30 -0400)]
Don't start ad-hoc games with -Wno-maybe-initialized
Borrowing from Linux commit
78a5255ffb6a ("Stop the ad-hoc games with -Wno-maybe-initialized")
move to have maybe-initialized warnings be handled with building with
W=2 instead of playing more guessing games with newer compilers.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:01 +0000 (08:30 -0400)]
kconfig: Add scripts/Kconfig.include from v4.19
As part of re-syncing our Kconfig logic up to v4.19, we had missed
adding this new file that includes helper macros. To quote the upstream
commit
e1cfdc0e72fc ("kconfig: add basic helper macros to scripts/Kconfig.include"):
Kconfig got text processing tools like we see in Make. Add Kconfig
helper macros to scripts/Kconfig.include like we collect Makefile
macros in scripts/Kbuild.include.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:00 +0000 (08:30 -0400)]
kconfiglib: Update to the 14.1.0 release
A large number of changes have happened upstream since our last sync
in commit
65e05ddc1ae2 ("kconfiglib: Update to the 12.14.0 release").
The big motivation for this sync is support for user defined macros
within Kconfig.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 19 May 2020 14:32:33 +0000 (10:32 -0400)]
Remove CROSS_COMPILE default from arch/*/config.mk
In order to support the compiler providing information used within
Kconfig itself we cannot have the compiler be determined by
arch/*/config.mk as we will not be able to evaluate that yet. Given
that most documentation tells people to specify CROSS_COMPILE, remove
these references.
Cc: Huan Wang <alison.wang@nxp.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Rick Chen <rick@andestech.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Sagar Shrikant Kadam [Sun, 28 Jun 2020 14:45:03 +0000 (07:45 -0700)]
riscv: cpu: check and append L1 cache to cpu features
All cpu cores within FU540-C000 having split I/D caches.
Set the L1 cache feature bit using the i-cache-size or d-cache-size
as one of the property from device tree indicating that L1 cache is
present on the cpu core.
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz: L1 cache, MMU
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Sagar Shrikant Kadam [Sun, 28 Jun 2020 14:45:02 +0000 (07:45 -0700)]
riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit
The conditional check to read "mmu-type" from the device tree
is not rightly handled due to which the cpu feature doesn't include
CPU_FEAT_MMU even if it's corresponding entry is present in the device
tree.
The initialization of cpu features is now taken care in cpu-uclass
driver, so no need to zero out cpu_freq in riscv_cpu driver and can be
removed.
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Sagar Shrikant Kadam [Sun, 28 Jun 2020 14:45:01 +0000 (07:45 -0700)]
uclass: cpu: fix to display proper CPU features
The cmd "cpu detail" fetches uninitialized cpu feature information
and thus displays wrong / inconsitent details as below.
For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it.
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
The L1 cache or MMU entry seen above is also displayed inconsistently.
So initialize cpu information to zero into cpu-uclass itself so that
similar issues can be avoided for other CPU drivers.
We now see correct features as:
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Sagar Shrikant Kadam [Sun, 28 Jun 2020 14:45:00 +0000 (07:45 -0700)]
riscv: dts: hifive-unleashed-a00: add cpu aliases
Add cpu aliases to U-Boot specific dtsi for hifive-unleashed.
Without aliases we see that the CPU device sequence numbers are set
randomly and the cpu list/detail command will show it as follows:
=> cpu list
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
0: cpu@4 rv64imafdc
Seems like CPU probing with dm-model also relies on aliases as observed
in case spi. The fu540-c000-u-boot.dtsi has cpu nodes and so adding
corresponding aliases we can ensure that cpu devices are assigned
proper sequence as follows:
=> cpu list
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
4: cpu@4 rv64imafdc
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:25 +0000 (06:41 -0400)]
riscv: Add Sipeed Maix support
The Sipeed Maix series is a collection of boards built around the RISC-V
Kendryte K210 processor. This processor contains several peripherals to
accelerate neural network processing and other "ai" tasks. This includes a
"KPU" neural network processor, an audio processor supporting beamforming
reception, and a digital video port supporting capture and output at VGA
resolution. Other peripherals include 8M of sram (accessible with and
without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
peripherals vary, but include spi flash; on-board usb-serial bridges; ports
for cameras, displays, and sd cards; and ESP32 chips. Currently, only the
Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly
similar.
Documentation for Maix boards is located at
<http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is
located at <https://kendryte.com/downloads/>. However, hardware details are
rather lacking, so most technical reference has been taken from the
standalone sdk located at
<https://github.com/kendryte/kendryte-standalone-sdk>.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:24 +0000 (06:41 -0400)]
doc: riscv: Add documentation for Sipeed Maix Bit
This patch adds documentation for the Sipeed Maix bit, and more generally
for the Kendryte K210 processor.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:23 +0000 (06:41 -0400)]
riscv: Add device tree for K210 and Sipeed Maix BitM
Where possible, I have tried to find compatible drivers based on the layout
of registers. However, many devices remain untested. All untested devices
have been left disabled, but some tentative properties (such as compatible
strings, and clocks, interrupts, and resets properties) have been added.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:22 +0000 (06:41 -0400)]
riscv: Enable cpu clock if it is present
The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:21 +0000 (06:41 -0400)]
riscv: Try to get cpu frequency from a "clocks" node if it exists
Instead of always using the "clock-frequency" property to determine cpu
frequency, try using a clock in "clocks" if it exists. This patch also
fixes a bug where there could be spurious higher frequencies if sizeof(u32)
!= sizeof(ulong).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:20 +0000 (06:41 -0400)]
riscv: Allow use of reset drivers
Currently, one cannot use a reset driver on RISC-V. Follow the MIPS
example, and disable the default reset handler when the sysreset driver is
enabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:19 +0000 (06:41 -0400)]
riscv: Add option to support RISC-V privileged spec 1.9
Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs. Using the new CSR on an old processor causes an illegal
instruction exception. This patch adds an option to use the old CSRs
instead of the new one.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:18 +0000 (06:41 -0400)]
riscv: Clean up IPI initialization code
The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is
called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions
should be called.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:17 +0000 (06:41 -0400)]
riscv: Clear pending interrupts before enabling IPIs
On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:16 +0000 (06:41 -0400)]
riscv: Add headers for asm/global_data.h
This header depended on bd_t and ulong, but did not include the appropriate
headers.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:15 +0000 (06:41 -0400)]
lib: Always set errno in hcreate_r
This could give a confusing error message if it failed and didn't set
errno.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:14 +0000 (06:41 -0400)]
reset: Add generic reset driver
This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 24 Jun 2020 10:41:13 +0000 (06:41 -0400)]
dm: Fix error handling for dev_read_addr_ptr
dev_read_addr_ptr had different semantics depending on whether OF_LIVE was
enabled. This patch converts both implementations to return NULL on error,
and converts all call sites which check for FDT_ADDR_T_NONE to check for
NULL instead. This patch also removes the call to map_physmem, since we
have dev_remap_addr* for those semantics.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 24 Jun 2020 10:41:12 +0000 (06:41 -0400)]
dm: Add support for simple-pm-bus
This type of bus is used in Linux to designate buses which have power
domains and/or clocks which need to be enabled before their child devices
can be used. Because power domains are automatically enabled before probing
in U-Boot, we just need to enable any clocks present.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 24 Jun 2020 10:41:11 +0000 (06:41 -0400)]
clk: Add K210 clock support
Due to the large number of clocks, I decided to use the CCF. The overall
structure is modeled after the imx code. Clocks parameters are stored in
several arrays, and are then instantiated at run-time. There are some
translation macros (FOOIFY()) which allow for more dense packing.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:10 +0000 (06:41 -0400)]
clk: Add a bypass clock for K210
This is a small driver to do a software bypass of a clock if hardware
bypass is not working. I have tried to write this in a generic fashion, so
that it could be potentially broken out of the kendryte code at some future
date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
so that the CPU keeps on working.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:09 +0000 (06:41 -0400)]
clk: Add K210 pll support
This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:08 +0000 (06:41 -0400)]
clk: Fix clk_get_by_* handling of index
clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean
predicate instead of the index. Other clk_get_by_* functions got the clock
correctly, but passed a predicate instead of the index to clk_get_by_tail.
This could lead to confusing error messages.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:07 +0000 (06:41 -0400)]
clk: Check that ops of composite clock components exist before calling
clk_composite_ops was shared between all devices in the composite clock
driver. If one clock had a feature (such as supporting set_parent) which
another clock did not, it could call a null pointer dereference.
This patch does three things
1. It adds null-pointer checks to all composite clock functions.
2. It makes clk_composite_ops const and sets its functions at compile-time.
3. It adds some basic sanity checks to num_parents.
The combined effect of these changes is that any of mux, rate, or gate can
be NULL, and composite clocks will still function normally. Previously, at
least mux had to exist, since clk_composite_get_parent was used to
determine the parent for clk_register.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Sean Anderson [Wed, 24 Jun 2020 10:41:06 +0000 (06:41 -0400)]
clk: Always use the supplied struct clk
CCF clocks should always use the struct clock passed to their methods for
extracting the driver-specific clock information struct. Previously, many
functions would use the clk->dev->priv if the device was bound. This could
cause problems with composite clocks. The individual clocks in a composite
clock did not have the ->dev field filled in. This was fine, because the
device-specific clock information would be used. However, since there was
no ->dev, there was no way to get the parent clock. This caused the
recalc_rate method of the CCF divider clock to fail. One option would be to
use the clk->priv field to get the composite clock and from there get the
appropriate parent device. However, this would tie the implementation to
the composite clock. In general, different devices should not rely on the
contents of ->priv from another device.
The simple solution to this problem is to just always use the supplied
struct clock. The composite clock now fills in the ->dev pointer of its
child clocks. This allows child clocks to make calls like clk_get_parent()
without issue.
imx avoided the above problem by using a custom get_rate function with
composite clocks.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Tom Rini [Tue, 30 Jun 2020 21:15:39 +0000 (17:15 -0400)]
Merge tag 'efi-2020-07-rc6-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-07-rc6 (2)
Fix an incorrect update of the GD register in efi_get_variable_common().
Fix an incorrect check for an FDT reg property.
Fix a device tree used for Python testing.
Tom Rini [Tue, 30 Jun 2020 19:03:25 +0000 (15:03 -0400)]
Merge branch '2020-06-30-minor-TI-board-updates' into next
- Minor updates to some platforms I am the listed maintainer of.
Notably this removes the ti814x_evm which stopped building with the PXA
MMC migration series (oops) but hasn't been functional in some time.
Tom Rini [Mon, 25 May 2020 18:34:06 +0000 (14:34 -0400)]
ti814x: Remove platform
The TI814x (DM814x) platform is rather old and in need of a lot of
migration work. As much of that work is well past the deadline, remove
this platform.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 25 May 2020 18:30:36 +0000 (14:30 -0400)]
ti816x_evm: Enable DM_MMC
This platform is already using DM in general and the MMC controller is
the early generation of what is compatible with "ti,omap4-hsmmc" so
enable DM_MMC (which in turn gets BLK enabled).
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 25 May 2020 18:28:43 +0000 (14:28 -0400)]
am335x: Update list of defconfigs
Both the am335x_boneblack and am335x_evm_usbspl configs have been gone
for a while, remove their entries from MAINTAINERS.
Signed-off-by: Tom Rini <trini@konsulko.com>