Thomas Symalla [Wed, 21 Sep 2022 08:15:55 +0000 (10:15 +0200)]
[NFC][AMDGPU] Pre-commit test for D132837.
Pre-commit an additional fmac test for D132837.
Bjorn Pettersson [Fri, 16 Sep 2022 12:54:40 +0000 (14:54 +0200)]
[SROA] Check typeSizeEqualsStoreSize in isVectorPromotionViable
Commit
de3445e0ef15c4209 (https://reviews.llvm.org/D132096) made
changes to isVectorPromotionViable basically doing
// Create Vector with size of V, and each element of type Ty
...
uint64_t ElementSize = DL.getTypeStoreSizeInBits(Ty).getFixedSize();
uint64_t VectorSize = DL.getTypeSizeInBits(V).getFixedSize();
...
VectorType *VTy = VectorType::get(Ty, VectorSize / ElementSize, false);
Not quite sure why it uses the TypeStoreSize for the ElementSize,
but the new vector would only match in size with the old vector in
situations when the TypeStoreSize equals the TypeSize for Ty.
Therefore this patch adds a typeSizeEqualsStoreSize check as yet
another condition for allowing the the new type as a promotion
candidate.
Without this fix the new @test15 test would fail with an assert
like this:
opt: ../lib/Transforms/Scalar/SROA.cpp:1966:
auto isVectorPromotionViable(llvm::sroa::Partition &,
const llvm::DataLayout &)
::(anonymous class)::operator()(llvm::VectorType *,
llvm::VectorType *) const:
Assertion `DL.getTypeSizeInBits(RHSTy).getFixedSize() ==
DL.getTypeSizeInBits(LHSTy).getFixedSize() &&
"Cannot have vector types of different sizes!"' failed.
...
#8 isVectorPromotionViable(...)::$_10::operator()...
#9 llvm::SROAPass::rewritePartition(...)
#10 llvm::SROAPass::splitAlloca(...)
#11 llvm::SROAPass::runOnAlloca(...)
#12 llvm::SROAPass::runImpl(...)
#13 llvm::SROAPass::run(...)
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D134032
River Riddle [Wed, 21 Sep 2022 01:11:08 +0000 (18:11 -0700)]
[mlir] Update tests to use kEmitAccessorPrefix_Prefixed
These aren't user facing, so just flip them directly to prefixed.
River Riddle [Wed, 21 Sep 2022 01:12:32 +0000 (18:12 -0700)]
[mlir][NFC] Tidy up the doc comment on CastInfo for Types
This had quite a few grammatical errors and typos.
River Riddle [Tue, 20 Sep 2022 23:42:59 +0000 (16:42 -0700)]
[mlir] Update Attributes to use the new casting infra
This allows for using the llvm namespace cast methods instead
of the ones on the Attribute class. The Attribute class methods
are kept for now, but we'll want to remove these eventually
(with a really long lead time).
Differential Revision: https://reviews.llvm.org/D134327
Adrian Kuegel [Wed, 21 Sep 2022 05:51:36 +0000 (07:51 +0200)]
[mlir][Bazel] Port
f5fe92f69385
Mark de Wever [Sat, 27 Aug 2022 11:43:51 +0000 (13:43 +0200)]
[libc++] Use Clang-16 for c++17.
Reviewed By: ldionne, #libc
Differential Revision: https://reviews.llvm.org/D132788
Chen Zheng [Fri, 16 Sep 2022 05:48:44 +0000 (01:48 -0400)]
[MachineCycle][NFC] add a cache for block and its top level cycle
This solves https://github.com/llvm/llvm-project/issues/57664
Reviewed By: sameerds
Differential Revision: https://reviews.llvm.org/D134019
Michał Górny [Tue, 20 Sep 2022 09:29:19 +0000 (11:29 +0200)]
[clang] [docs] Improve formatting & fix typo in config docs
Fix teletype formatting in configuration file documentation to use
double backticks rather than single backticks. Cover some more names
with this formatting. Correct the name of config file for `clang-cl`
invocation.
Differential Revision: https://reviews.llvm.org/D134271
Jennifer Yu [Tue, 20 Sep 2022 08:38:34 +0000 (01:38 -0700)]
[Clang][OpenMP] Codegen generation for has_device_addr claues.
This patch add codegen support for the has_device_addr clause. It use
the same logic of is_device_ptr. But passing &var instead pointer to var
to kernal.
Differential Revision: https://reviews.llvm.org/D134268
Mehdi Amini [Wed, 21 Sep 2022 03:54:32 +0000 (03:54 +0000)]
Revert "[mlir][tensor] Support more cases in MergeConsecutiveExtractSlice"
This reverts commit
5d4603a02d0c3e0106b10d245322b1d2072c0c3d.
The Dialect/Tensor/fold-consecutive-insert-extract-slice.mlir test is
failing when built with GCC
Kevin Gleason [Tue, 20 Sep 2022 21:49:08 +0000 (21:49 +0000)]
Fix -fuse-ld to be linker flag in feature detection check
Discovered an issue working in StableHLO when attempting to build with `-Wall -Werror`:
https://github.com/openxla/stablehlo/pull/137
Currently, if `LLVM_USE_LLD` and `-DCMAKE_CXX_FLAGS="${CMAKE_CXX_FLAGS} -Wall -Werror"`
are both specified for build, the build will error with:
```
-- Performing Test CXX_SUPPORTS_CUSTOM_LINKER - Failed
CMake Error at /usr/local/google/home/gleasonk/Coding/llvm-build/lib/cmake/llvm/HandleLLVMOptions.cmake:309 (message):
Host compiler does not support '-fuse-ld=lld'
...
$ cat <build_dir>/CMakeFiles/CMakeError.log
...
clang: error: argument unused during compilation: '-fuse-ld=lld' [-Werror,-Wunused-command-line-argument]
```
It looks like other repos have hit this same issue:
- https://github.com/golang/go/issues/41527 (mentioned in comment)
- https://github.com/iree-org/iree/pull/7450
This can be reproduced in llvm-project with the following build command:
```
# Compile command taken from https://mlir.llvm.org/getting_started/
# and modified for use case
cmake -G Ninja ../llvm \
-DLLVM_ENABLE_PROJECTS=mlir \
-DLLVM_BUILD_EXAMPLES=ON \
-DLLVM_TARGETS_TO_BUILD="X86;NVPTX;AMDGPU" \
-DCMAKE_BUILD_TYPE=Release \
-DLLVM_ENABLE_ASSERTIONS=ON \
-DCMAKE_CXX_COMPILER=clang++ \
-DCMAKE_C_COMPILER=clang \
-DLLVM_ENABLE_LLD=ON \
-DCMAKE_CXX_FLAGS="${CMAKE_CXX_FLAGS} -Wall -Werror"
```
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D134206
Christopher Bate [Tue, 20 Sep 2022 20:54:35 +0000 (14:54 -0600)]
[mlir][SCF] Fix loop pipelining unable to handle ops with regions
This change allows the SCF LoopPipelining transform to handle ops with
nested regions within the pipelined `scf.for` body. The op and nested
regions are treated as a single unit from the transform's perspective.
This change also makes explicit the requirement that only ops whose
parent Block is the loop body Block are allowed to be scheduled by the
caller.
Reviewed By: ThomasRaoux, nicolasvasilache
Differential Revision: https://reviews.llvm.org/D133965
Emmmer [Wed, 21 Sep 2022 03:52:04 +0000 (11:52 +0800)]
[LLDB][RISCV] Fix UndefinedBehaviorSanitizer in RISCVEmulatorTester
Craig Topper [Wed, 21 Sep 2022 03:26:48 +0000 (20:26 -0700)]
[RISCV] Remove support for the unratified Zbt extension.
This extension does not appear to be on its way to ratification.
Out of the unratified bitmanip extensions, this one had the
largest impact on the compiler.
Posting this patch to start a discussion about whether we should
remove these extensions. We'll talk more at the RISC-V sync meeting this
Thursday.
Reviewed By: asb, reames
Differential Revision: https://reviews.llvm.org/D133834
Fangrui Song [Wed, 21 Sep 2022 03:13:30 +0000 (20:13 -0700)]
[Driver] Fix -f[no-]unwind-tables -Wunused-command-line-argument after
4388b56d525c08ce3cf941cfbad2428b0e1695b0
jacquesguan [Tue, 30 Aug 2022 09:17:55 +0000 (17:17 +0800)]
[RISCV] Support peephole optimization to fold vmerge.vvm that has tail agnostic policy and unmasked intrinsics.
This patch supports the tail agnostic part of D130442.
Reviewed By: fakepaper56
Differential Revision: https://reviews.llvm.org/D132923
Ting Wang [Wed, 21 Sep 2022 01:21:06 +0000 (21:21 -0400)]
[PowerPC][NFC] Add virtual call to show redundant spill of vector registers
Reviewed By: lkail
Differential Revision: https://reviews.llvm.org/D133921
Volodymyr Sapsai [Tue, 20 Sep 2022 00:46:01 +0000 (17:46 -0700)]
[modules] Fix error "malformed or corrupted AST file: 'SourceLocation remap refers to unknown module...'".
When a framework can be found at a new location, all references to it in
the module cache become outdated. When we try to load such outdated .pcm
file, we shouldn't change any already loaded and processed modules.
If `Module` has `ASTFile`, it means we've read its AST block already and
it is too late to undo that. If `ASTFile` is `None`, there is no value
in setting it to `None` again. So we don't reset `ASTFile` in
`ModuleManager::removeModules` at all.
rdar://
97216258
Differential Revision: https://reviews.llvm.org/D134249
Kazu Hirata [Wed, 21 Sep 2022 00:41:58 +0000 (17:41 -0700)]
[clang] Fix an unused variable warning
This patch fixes:
clang/lib/Driver/ToolChains/PS4CPU.cpp:159:14: error: unused
variable 'IsPS5' [-Werror,-Wunused-variable]
Changpeng Fang [Wed, 21 Sep 2022 00:25:52 +0000 (17:25 -0700)]
AMDGPU: Implicit kernel arguments related optimization when uniform-workgroup-size=true
Summary:
Under code object version 5, ockl_get_local_size returns the value computed by the expression:
workgroup_id < hidden_block_count ? hidden_group_size : hidden_remainder
For functions with the attribute uniform-work-group-size=true. we can evaluate workgroup_id < hidden_block_count
as true, and thus hidden_group_size is returned for ockl_get_local_size.
With uniform-workgroup-size=true, this work also set all remainders to zero, and if there
is reqd_work_group_size, we also set work-group-size to the required value from the metadata.
Reviewers:
arsenm and bcahoon
Differential Revision:
https://reviews.llvm.org/D131276
Lei Zhang [Wed, 21 Sep 2022 00:16:42 +0000 (20:16 -0400)]
[mlir][tensor] NFC: name various Transforms/ files consistently
Use a suffix to make clear what the contents inside each file
are.
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D134202
Lei Zhang [Wed, 21 Sep 2022 00:00:49 +0000 (20:00 -0400)]
[mlir][tensor] Support more cases in MergeConsecutiveExtractSlice
This commit adds utility functions to perform general merging of
OffsetSizeAndStrideOpInterface by supporting producer rank
reducing and non-unit strides.
With it we can extend MergeConsecutiveExtractSlice to support
more cases.
Co-authored-by: Mahesh Ravishankar <ravishankarm@google.com>
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D134294
Fangrui Song [Wed, 21 Sep 2022 00:12:44 +0000 (17:12 -0700)]
[ELF] Make -V an alias for -v
In GNU ld,
* --version skips linker input processing.
* -v and -V keep processing if there is any input file. -V has more
information we don't support.
We currently make -V an alias for --version which skips input processing.
On many `*-freebsd` and `powerpc-*` targets, `gcc -v` passes `-V` to ld
and expects to process input. Make -V an alias for -v to provide
compatibility.
Fix https://github.com/llvm/llvm-project/issues/57859
Fangrui Song [Wed, 21 Sep 2022 00:05:35 +0000 (17:05 -0700)]
[ELF][test] Improve -v and --version tests
Shubham Sandeep Rastogi [Tue, 20 Sep 2022 23:58:14 +0000 (16:58 -0700)]
Change isLittleEndian to follow llvm style and add an accessor
Differential Revision: https://reviews.llvm.org/D134290
Lei Zhang [Tue, 20 Sep 2022 23:52:19 +0000 (19:52 -0400)]
[mlir][tensor] Merge consecutive insert_slice/extract_slice ops
Consecutive tensor.insert_slice/tensor.extract_slice can be
created for the case like tiling convolution and then downsizing
2-D convolutions into 1-D ones. It hinders further transformations.
So adding these patterns to clean it up.
Given that bufferization is sensitive and have requirements over
the IR structure (see https://reviews.llvm.org/D132666),
these patterns are put in Transforms/ with separate entry points
for explicit collection.
Reviewed By: ThomasRaoux, mravishankar
Differential Revision: https://reviews.llvm.org/D133871
Michael Jones [Fri, 16 Sep 2022 18:19:38 +0000 (11:19 -0700)]
[libc] add strerror
Strerror maps error numbers to strings. Additionally, a utility for
mapping errors to strings was added so that it could be reused for
perror and similar.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D134074
Jakub Kuderski [Tue, 20 Sep 2022 23:00:32 +0000 (19:00 -0400)]
[mlir][arith] Fix constant naming in integration tests. NFC.
Suggested by @antiagainst in D134321.
Jakub Kuderski [Tue, 20 Sep 2022 22:51:20 +0000 (18:51 -0400)]
[mlir][arith] Add integration tests for addi emulation
This includes tests with the exact expected values and comparison-based tests.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134321
Michael Berg [Tue, 20 Sep 2022 22:54:16 +0000 (15:54 -0700)]
[DSE] Add value type info checks for masked store candidates in Dead Store Elimination.
The type information of the store values can diverge when checking for valid
mask store candidates to eliminate via DSE. This patch checks for equivalence
wrt to size and element count.
Reviewed By: fhahn, rui.zhang
Differential Revision: https://reviews.llvm.org/D132700
Matheus Izvekov [Tue, 20 Sep 2022 13:18:20 +0000 (15:18 +0200)]
[clang] Fix missing template arguments in AST of access to member variable template
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Differential Revision: https://reviews.llvm.org/D134295
Stanley Winata [Tue, 20 Sep 2022 22:28:40 +0000 (15:28 -0700)]
[mlir][spirv] Query target environment for mapping memory space
Checks spirv::TargetEnv from op to see if it contains either Kernel or Shader capabilities.
If it does, then it will set the memory space mapping accordingly.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134317
Xiang Li [Mon, 22 Aug 2022 23:57:48 +0000 (16:57 -0700)]
[HLSL] Support PCH for cc1 mode
Add HLSLExternalSemaSource as ExternalSemaSource instead of ASTContext::ExternalSource when PCH is included.
This allows a different external source to be set for the AST context.
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D132421
Nirvedh Meshram [Mon, 19 Sep 2022 18:05:58 +0000 (11:05 -0700)]
[mlir][spirv] Add casting ops to/from generic storage space
Reviwed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134217
Matthew Voss [Tue, 20 Sep 2022 21:44:56 +0000 (14:44 -0700)]
[PS4] Always enable the .debug_aranges section when using LTO
This flag enables the .debug_aranges section by passing a flag to LLD
and our internal linker. This also adds a new routine that will generate
the correct flag for our internal linker or set of flags for LLD when
given a list of LLVM options. That ensures multiple LLVM codegen options
can be passed to either linker consistently.
Differential Revision: https://reviews.llvm.org/D134296
Pengxuan Zheng [Tue, 20 Sep 2022 00:21:21 +0000 (17:21 -0700)]
[LLD][COFF] Support /MAPINFO flag
This patch adds support for link.exe's /MAPINFO flag to lld-link.exe.
Here is a description of the flag from Microsoft
(https://learn.microsoft.com/en-us/cpp/build/reference/mapinfo-include-information-in-mapfile?view=msvc-170):
The /MAPINFO option tells the linker to include the specified information in a
mapfile, which is created if you specify the /MAP option. EXPORTS tells the
linker to include exported functions.
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D134247
Lei Zhang [Tue, 20 Sep 2022 21:31:16 +0000 (17:31 -0400)]
[mlir][linalg] Swap tensor.extract_slice(linalg.fill)
This commit adds a pattern to swap
```
tensor.extract_slice(linalg.fill(%cst, %init))
```
into
```
linalg.fill(%cst, tensor.extract_slice(%init))
```
when the linalg.fill op have no other users.
This helps to reduce the fill footprint.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D134102
Stanley Winata [Tue, 20 Sep 2022 21:16:52 +0000 (17:16 -0400)]
[mlir][spirv] Lower max/min vector.reduction for OpenCL
Templatizing vector reduction to enable lowering from
vector.reduction max/min to CL ops.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134313
Louis Dionne [Tue, 20 Sep 2022 21:22:00 +0000 (17:22 -0400)]
[NFC] Fix typo in comment
Naje George [Tue, 9 Aug 2022 00:07:42 +0000 (17:07 -0700)]
[flang] Add semantics test for atomic_add subroutine
Reviewed By: ktras
Differential Revision: https://reviews.llvm.org/D131535
Joshua Batista [Tue, 20 Sep 2022 21:04:08 +0000 (16:04 -0500)]
[HLSL] remove unnecessary abs attributes
remove abs non-elementwise attribute statements, stick to elementwise.
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D134312
Kai Nacke [Mon, 19 Sep 2022 16:03:32 +0000 (16:03 +0000)]
[GISel] TreeMatcher: always skip leaves if they don't care
In `GIMatchTreeOpcodePartitioner::applyForPartition()`, the loop over
the possible leaves skip a leaf if the instruction does not care
about the instruction.
When processing the referenced operands in the next loop the same
leaves need to be skipped.
Later, when these leaves are added to all partitions, the bit vector
must be resized first before the bit representing the leaf is set.
This fixes a crash in llvm-tblgen.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D134192
Matt Arsenault [Tue, 20 Sep 2022 18:58:52 +0000 (14:58 -0400)]
AtomicExpand: Use correct pointer size for integer
This was using the default address space.
Matt Arsenault [Tue, 20 Sep 2022 18:51:33 +0000 (14:51 -0400)]
AMDGPU: Add baseline test for expansion of 16-bit local atomics
The expansion is currently using the wrong pointer size.
Matt Arsenault [Tue, 20 Sep 2022 20:03:13 +0000 (16:03 -0400)]
AtomicExpand: Switch test to generated checks
Matt Arsenault [Tue, 20 Sep 2022 20:32:08 +0000 (16:32 -0400)]
VE: Use generated checks for a copy-pasted output test
Tom Praschan [Sun, 18 Sep 2022 16:48:11 +0000 (18:48 +0200)]
[clangd] Return earlier when snippet is empty
Fixes github.com/clangd/clangd/issues/1216
If the Snippet string is empty, Snippet.front() would trigger a crash.
Move the Snippet->empty() check up a few lines to avoid this. Should not
break any existing behavior.
Differential Revision: https://reviews.llvm.org/D134137
Joshua Batista [Tue, 20 Sep 2022 19:46:06 +0000 (14:46 -0500)]
[HLSL] add sqrt library function
This change exposes the sqrt library function for HLSL scalar types,
excluding long and long long doubles. Sqrt is supported for all scalar, vector,
and matrix types. This patch only adds a subset of scalar type support.
Long and long long double support is missing in this patch because that type
doesn't exist in HLSL.
The full documentation of the HLSL asin function is available here:
https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-sqrt
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D132711
Zequan Wu [Tue, 20 Sep 2022 20:38:18 +0000 (13:38 -0700)]
[LLDB][NativePDB] Pass register_kind as reference (an oversight in 71d778f).
Fix #57799
Scott Linder [Tue, 20 Sep 2022 20:05:19 +0000 (20:05 +0000)]
[NFC][AMDGPU] Refactor AMDGPUDisassembler
Clean up ahead of a patch to fix bugs in the AMDGPUDisassembler.
Use lit.local.cfg substitutions and more idiomatic use of split-file to
simplify and extend existing kernel-descriptor disassembly tests.
Add a comment to AMDHSAKernelDescriptor.h, as at least one small set
towards keeping all kernel-descriptor sensitive code in sync.
Reviewed By: kzhuravl, arsenm
Differential Revision: https://reviews.llvm.org/D130105
Craig Topper [Tue, 20 Sep 2022 19:13:01 +0000 (12:13 -0700)]
[RISCV] Support -mno-implicit-float.
This can be used to disable vectorization and memcpy/memset
expansion for things like OS kernels. It also disables implicit
uses of scalar FP, but I don't know if we have any of those for
RISC-V.
NOTE: Without this patch you can still do -Xclang -no-implicit-float
Reviewed By: rui.zhang
Differential Revision: https://reviews.llvm.org/D134077
Anshil Gandhi [Tue, 20 Sep 2022 20:23:46 +0000 (14:23 -0600)]
[AMDGPU] Fix size of SOPK instructions to 4 bytes
Instructions in SOPK format may not have 32-bit
literal constants following the instruction.
Differential Revision: https://reviews.llvm.org/D133972
Markus Böck [Tue, 20 Sep 2022 20:12:10 +0000 (22:12 +0200)]
[InstCombine] Handle integer extension in `select` patterns using the condition as value
These patterns were previously only implemented for i1 type but can be extended for any integer type by also handling zext and sext operands.
Differential Revision: https://reviews.llvm.org/D134142
Sam McCall [Tue, 20 Sep 2022 20:17:02 +0000 (22:17 +0200)]
[clangd] Remove second tracer (which breaks threading contract)
rkayaith [Tue, 20 Sep 2022 02:14:45 +0000 (22:14 -0400)]
[mlir][standalone] Specify python path when configuring
Specifying the python path here ensures that the python binary used matches the
one used by the main MLIR tests. This is useful when cmake's automatic detection
has to be overridden.
Reviewed By: stellaraccident, bondhugula
Differential Revision: https://reviews.llvm.org/D134251
Frederik Gossen [Tue, 20 Sep 2022 19:11:12 +0000 (15:11 -0400)]
[MLIR] Update bazel build files after
242d558658cd5a480b02883e2982d7246342e0d0
Differential Revision: https://reviews.llvm.org/D134301
George Hu [Tue, 20 Sep 2022 17:56:16 +0000 (10:56 -0700)]
[LLDB]Initialize accept_socket with nullptr
Fix high impact issue of illegal access of memory.
Initialize accept_socket with nullptr.
Differential Revision: https://reviews.llvm.org/D134293
owenca [Mon, 19 Sep 2022 22:28:18 +0000 (15:28 -0700)]
[clang-format] Wrap inserted braces only if preceded by comments
Fixes #57805.
Differential Revision: https://reviews.llvm.org/D134233
Zain Jaffal [Tue, 20 Sep 2022 18:45:02 +0000 (19:45 +0100)]
[InstCombine] Matrix multiplication negation optimisation
If one of the operands in a matrix multiplication is negated we can optimise the equation by moving the negation to the smallest element of the operands or the result.
Reviewed By: spatel, fhahn
Differential Revision: https://reviews.llvm.org/D133300
Matt Arsenault [Mon, 19 Sep 2022 21:50:36 +0000 (17:50 -0400)]
AMDGPU: Fix expansion of 16-bit atomicrmw
Fixes issue 57830
Douglas Yung [Tue, 20 Sep 2022 18:23:47 +0000 (11:23 -0700)]
Add explicit tests for the PS4/PS5 C/C++ standards version defaults.
Alex Brachet [Tue, 20 Sep 2022 18:25:16 +0000 (18:25 +0000)]
[Driver] Make --execute-only the default for aarch64-fuchsia
Clang already generates code that doesn't use writeable data in executable
sections so the linker flag is all that is necessary.
-Wl,--no-execute-only can be used to turn this default off.
Differential Revision: https://reviews.llvm.org/D134289
Katherine Rasmussen [Mon, 19 Sep 2022 17:53:10 +0000 (10:53 -0700)]
[flang] Write semantics test for atomic_or
Write a semantics test for the atomic intrinsic subroutine,
atomic_or.
Reviewed By: rouson
Differential Revision: https://reviews.llvm.org/D134200
Fangrui Song [Tue, 20 Sep 2022 18:14:04 +0000 (11:14 -0700)]
[ELF] Name ctx->objectFiles[0] in the EF_RISCV_FLOAT_ABI mismatch error
Reviewed By: compnerd
Differential Revision: https://reviews.llvm.org/D134198
Peiming Liu [Tue, 20 Sep 2022 17:50:34 +0000 (17:50 +0000)]
[mlir][scf] Support simple symbolic expression without depending on AffineDialect to simply trivial loops.
Remove dependence of AffineDialect
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D134291
Jeff Niu [Wed, 14 Sep 2022 00:19:19 +0000 (17:19 -0700)]
[mlir][ods] Allow empty array ref parameter
This patch "fixes" a longstanding issue where the assembly format for
ArrayRefParameter could not handle an empty list. This is because there
was no way to generically optionally parse the first element of the
array. The only solution was to write a (relatively simple) custom parser.
This patch implements "empty" ArrayRefParameters by using
inverted optional groups and an optional ArrayRefParameter.
Depends on D133816
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D133819
Jeff Niu [Tue, 13 Sep 2022 23:16:20 +0000 (16:16 -0700)]
[mlir][ods] Generalize default/optional parameters
This patch consolidates the notions of an optional parameter and a
default parameter. An optional parameter is a parameter equal to its
default value, which for a "purely optional" parameter is its "null"
value.
This allows the existing `comparator` and `defaultValue` fields to be
used enabled more complex "optional" parameters, such as empty arrays.
Depends on D133812
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D133816
Jeff Niu [Tue, 13 Sep 2022 22:08:39 +0000 (15:08 -0700)]
[mlir][ods] Format: allow anchors in the else elements
This patch changes optional groups to allow anchors in the 'else'
element group. When printing, the optional condition is inverted to
decide which group to print. This is useful for parsing concrete
optional elements that don't have a `parseOptional*` method or some
other way to test whether it's present.
Depends on D133805
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D133812
Jeff Niu [Tue, 13 Sep 2022 20:15:06 +0000 (13:15 -0700)]
[mlir][ods] Store the pointer to the anchor element (NFC)
Instead of its index. There is no benefit to storing the index instead
of the pointer.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D133805
Brett Wilson [Tue, 20 Sep 2022 17:54:28 +0000 (17:54 +0000)]
[clang-doc] Centralize TypeInfo creation.
Several different places in the code had similar computations for the parameters that were eventually passed to the TypeInfo constructor.
This centralizes that code in one function, and allows passing TypeInfo to the various other *Info structures that need it.
Remove some "auto" types and replace with the real type for getting declarations. This was making some duplicate checking difficult to see.
Reviewed By: paulkirth
Differential Revision: https://reviews.llvm.org/D134225
Jorge Gorbe Moya [Mon, 19 Sep 2022 23:35:24 +0000 (16:35 -0700)]
[NFCI] Clean up enum FormatCategoryItem.
- Merge pairs like `eFormatCategoryItemSummary` and
`eFormatCategoryItemRegexSummary` into a single value. See explanation
below.
- Rename `eFormatCategoryItemValue` to `eFormatCategoryItemFormat`. This
makes the enum match the names used elsewhere for formatter kinds
(format, summary, filter, synth).
- Delete unused values `eFormatCategoryItemValidator` and
`eFormatCategoryItemRegexValidator`.
This enum is only used to reuse some code in CommandObjectType.cpp. For
example, instead of having separate implementations for `type summary
delete`, `type format delete`, and so on, there's a single generic
implementation that takes an enum value, and then the specific commands
derive from it and set the right flags for the specific kind of
formatter.
Even though the enum distinguishes between regular and regex matches for
every kind of formatter, this distinction is never used: enum values are
always specified in pairs like
`eFormatCategoryItemSummary | eFormatCategoryItemRegexSummary`.
This causes some ugly code duplication in TypeCategory.cpp. In order to
handle every flag combination some code appears 8 times:
{format, summary, synth, filter} x {exact, regex}
Differential Revision: https://reviews.llvm.org/D134244
Anton Sidorenko [Tue, 20 Sep 2022 17:22:16 +0000 (10:22 -0700)]
[NFC][RISCV] Move calculations of SDNode policy operand idx to a separate function
Since there is no guaranteed correspondence of SDNode and MI operands, we need
getters simular to RISCVII::get*OpNum for SDNodes.
More uses of getVecPolicyOpIdx will be added in D130895.
Reviewed By: craig.topper, arcbbb
Differential Revision: https://reviews.llvm.org/D134179
Philip Reames [Tue, 20 Sep 2022 17:01:37 +0000 (10:01 -0700)]
[RISCV][MC] Add support for experimental Zawrs extension
This implements experimental support for the Zawrs extension as specified here: https://github.com/riscv/riscv-zawrs/releases/download/V1.0-rc3/Zawrs.pdf. Despite the 1.0 version name, this has not been ratified and there was a major change to proposed specification between rc2 and rc3. Once this is ratified, it'll move out of experimental status.
This change adds assembly support, but does not include C language or IR intrinsics. We can decide if we want them, and handle that in a separate patch.
Differential Revision: https://reviews.llvm.org/D133443
LLVM GN Syncbot [Tue, 20 Sep 2022 17:07:57 +0000 (17:07 +0000)]
[gn build] Port
00798e500644
Mingming Liu [Tue, 14 Jun 2022 21:04:49 +0000 (14:04 -0700)]
[AArch64] Define __ARM_FEATURE_RCPC
This patch implements the definition of __ARM_FEATURE_RCPC when clang
command specifies +rcpc.
Differential Revision: https://reviews.llvm.org/D127798
Mark de Wever [Mon, 5 Sep 2022 17:01:50 +0000 (19:01 +0200)]
[libc++] Applies P0602R4 retro-actively.
While testing a test failure of C++17 with Clang ToT it was noticed the
paper
P0602R4 variant and optional should propagate copy/move triviality
was not applied as a DR in libc++.
This was discovered while investigating the issue "caused by" D131479.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D133326
Gulfem Savrun Yeniceri [Fri, 16 Sep 2022 18:19:06 +0000 (18:19 +0000)]
[InstrProfiling] Emit runtime hook only once
This patch fixes the issue about calling emitRuntimeHook() twice
when we need to unconditionally emit runtime hook as discussed in
https://reviews.llvm.org/rGd6aed77f0d19.
Differential Revision: https://reviews.llvm.org/D134254
Mark de Wever [Fri, 16 Sep 2022 18:47:01 +0000 (20:47 +0200)]
[NFC][libc++][format] Uses ranges algorithm.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D134060
Mark de Wever [Thu, 5 May 2022 06:03:58 +0000 (08:03 +0200)]
[libc++][test] Adds format string helper.
Update the formatter day tests to the new style.
Other test will be done separately.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D134031
Mark de Wever [Tue, 13 Sep 2022 18:10:26 +0000 (20:10 +0200)]
[libc++][chrono] Removes format include.
Switch to the new granular format_functions header. Since the chrono's
format dependency in C++20 hasn't been in a release it's save to remove
it.
Depends on D133665
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D133796
Mark de Wever [Sun, 11 Sep 2022 11:05:26 +0000 (13:05 +0200)]
[libc++][format] Granularizes the format header.
Moves the last pieces of code to its own header.
Reviewed By: ldionne, #libc
Differential Revision: https://reviews.llvm.org/D133665
Jay Foad [Tue, 20 Sep 2022 12:29:39 +0000 (13:29 +0100)]
[AMDGPU] Disable fp atomic to s_denorm_mode hazard for GFX11
This hazard only exists on GFX10.
Differential Revision: https://reviews.llvm.org/D134276
yronglin [Tue, 20 Sep 2022 16:35:18 +0000 (12:35 -0400)]
Fix __builtin_assume_aligned incorrect type descriptor and C++ object polymorphic address
Fix __builtin_assume_aligned incorrect type descriptor
example from @rsmith
struct A { int n; };
struct B { int n; };
struct C : A, B {};
void *f(C *c) {
// Incorrectly returns `c` rather than the address of the B base class.
return __builtin_assume_aligned((B*)c, 8);
}
Differential Revision: https://reviews.llvm.org/D133583
Kazu Hirata [Tue, 20 Sep 2022 16:09:38 +0000 (09:09 -0700)]
[IPO] Reorder parameters of InlineFunction (NFC)
With the recent addition of new parameter MergeAttributes (D134117),
callers need to specify several default parameters before getting to
specify the new parameter.
This patch reorders the parameters so that callers do not have to
specify as many default parameters.
Differential Revision: https://reviews.llvm.org/D134125
David Green [Tue, 20 Sep 2022 16:09:14 +0000 (17:09 +0100)]
[AArch64] Enable LSLFast for modern OoO cpus
This patch enables the LSLFast feature for Cortex-A76, Cortex-A77,
Cortex-A78, Cortex-A78C, Cortex-A710, Cortex-X1, Cortex-X2, Neoverse N1,
Neoverse N2, Neoverse V1 and the Neoverse 512TB pseudo-cpu, in-line with
the software optimization guides for those CPUs.
Differntial revision: https://reviews.llvm.org/D134273
Chris Bieneman [Tue, 20 Sep 2022 15:41:43 +0000 (10:41 -0500)]
[HLSL] Pass flags to cc1 based on language
Having the flags only pass through if you're using the dxc-driver means
that the clang driver doesn't work for HLSL, which is undesirable. This
change switches to instead passing flags based on the language mode
similar to how OpenCL does it. This allows the clang driver to be used
for HLSL source files as well.
Reviewed By: python3kgae
Differential Revision: https://reviews.llvm.org/D133958
Ben Dunbobbin [Tue, 20 Sep 2022 15:50:18 +0000 (16:50 +0100)]
Revert "[Utils] Refactor update_cc_test_checks.py to use shutil"
This reverts commit
2e6c50855b7d879ded3776ba87b3d960e2035b89.
This caused failures on windows bots:
- https://lab.llvm.org/buildbot/#/builders/216/builds/10030
- https://ci.chromium.org/ui/p/fuchsia/builders/toolchain.ci/clang-windows-x64/
b8802513693562827489/overview
Simon Pilgrim [Tue, 20 Sep 2022 15:44:26 +0000 (16:44 +0100)]
[InstCombine] Fold ult(add(x,-1),c) -> ule(x,c) iff x != 0 (PR57635)
Alive2: https://alive2.llvm.org/ce/z/sZ6wwS
As detailed on Issue #57635 and #37628 - for unsigned comparisons, we can compare prior to a decrement iff the value is known never to be zero.
Differential Revision: https://reviews.llvm.org/D134172
Chris Bieneman [Mon, 19 Sep 2022 15:22:33 +0000 (10:22 -0500)]
[CMake] [NFC] Add clang headers to IDE projects
This just adds the clang headers into a source group so that they get
collected and added into generated IDE projects.
Amara Emerson [Mon, 19 Sep 2022 23:21:55 +0000 (00:21 +0100)]
[GlobalISel][Legalizer] Fix lowerSelect() not sign-extending the mask value.
I'm not sure why the SEXT_INREG was gated on a bitwidth check of the mask
vs element size.
This fixes a miscompile in chromium's skia library.
Differential Revision: https://reviews.llvm.org/D134236
Jakub Kuderski [Tue, 20 Sep 2022 15:37:26 +0000 (11:37 -0400)]
[mlir][arith] Add comparison-based integration tests
Introduces a simple framework for runtime tests of the wide integer emulation.
In these tests, we are only interested in checking that both wide and narrow calculation
produce the same results, and do not check for exact results. This allows us to cover
more of the input space, as we do not have to hardcode each of the expected outputs.
Introduce common helper functions to check the results, print a message on mismatch,
and sample the input space.
Implement runtime comparrison tests for `arith.muli` and `arith.shrui`.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134184
Jakub Kuderski [Tue, 20 Sep 2022 15:27:48 +0000 (11:27 -0400)]
[mlir][arith] Add integration test for shrui emulation
The new test cases focus on known edge cases in the current implementation.
Specifically, we check for low (0, 1), mid (7, 8, 9) and high (15) shift amounts with i16 operands.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134182
Jakub Kuderski [Tue, 20 Sep 2022 15:03:37 +0000 (11:03 -0400)]
[mlir][arith] Add test pass for wide integer emulation
The new test pass allows for running wide integer emulation conversion
within specified functions only.
I intend to use it in integration tests in a way that allows me print both
original and emulated results in the same format, or even compare both results
at runtime and print on mismatch only.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D134120
Louis Dionne [Tue, 23 Aug 2022 15:22:55 +0000 (11:22 -0400)]
[llvm] Remove libcxx, libcxxabi and libunwind from supported LLVM_ENABLE_PROJECTS
This is a breaking change. If you were passing one of those three runtimes
in LLVM_ENABLE_PROJECTS, you need to start passing them in LLVM_ENABLE_RUNTIMES
instead. The runtimes in LLVM_ENABLE_RUNTIMES will start being built using
the "bootstrapping build" instead, which means that they will be built
using the just-built Clang. This is usually what you wanted anyway.
If you were using LLVM_ENABLE_PROJECTS=all with the explicit goal of
building these three runtimes, you can now use LLVM_ENABLE_RUNTIMES=all
and these runtimes will be built using the bootstrapping build.
Differential Revision: https://reviews.llvm.org/D132480
Eric Li [Tue, 20 Sep 2022 15:10:16 +0000 (11:10 -0400)]
[Support][NFC] Clarify function comment
Follow-up to
86118ec2 that addresses the comments in D134072, which
were accidentally left off of the commit.
Eric Li [Fri, 16 Sep 2022 20:07:26 +0000 (16:07 -0400)]
[Support] Provide access to the full mapping in llvm::Annotations
Providing access to the mapping of annotations allows test helpers to
be expressive by using the annotations as expectations. For example, a
matcher could verify that all annotated points were matched by a
matcher, or that an refactoring surgically modifies specific ranges.
Differential Revision: https://reviews.llvm.org/D134072
Joe Nash [Wed, 13 Jul 2022 18:14:48 +0000 (14:14 -0400)]
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C
Due to the encoding changes in GFX11, we had a hack in place that
disables the use of VGPRs above 128. This patch removes the need for
that hack.
We introduce a new register class VGPR_32_Lo128 which is used for 16-bit
operands of VOP1, VOP2, and VOPC instructions. This register class only has the
low 128 VGPRs, but is otherwise identical to VGPR_32. Therefore, 16-bit VOP1,
VOP2, and VOPC instructions are correctly limited to use the first 128
VGPRs, while the other instructions can freely use all 256.
We introduce new pseduo-instructions used on GFX11 which have the suffix
t16 (True 16) to use the VGPR_32_Lo128 register class.
Reviewed By: foad, rampitec, #amdgpu
Differential Revision: https://reviews.llvm.org/D133723
Jeff Bailey [Tue, 20 Sep 2022 14:25:16 +0000 (14:25 +0000)]
[libc] Fix TWS issues in .td files
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D134256
Jeff Bailey [Tue, 20 Sep 2022 14:24:21 +0000 (14:24 +0000)]
[libc] Remove unneeded extra include
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D134255