Boris Brezillon [Wed, 2 Jun 2021 08:17:55 +0000 (10:17 +0200)]
pan/bi: Relax check on 8bit swizzles
Allow extracting components Y, Z or W from an 8bit vector.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12095>
Samuel Pitoiset [Mon, 20 Sep 2021 15:09:41 +0000 (17:09 +0200)]
radv: do not store meta shaders to the default shader disk cache
Meta shaders are already stored in a different shader cache file.
Storing them in two places wastes disk space and they are never
loaded from the default shader disk cache anyways.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12937>
Michel Zou [Mon, 20 Sep 2021 16:52:38 +0000 (18:52 +0200)]
wgl: fix 32 bits mingw exports
closes #5349
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12940>
Samuel Pitoiset [Mon, 20 Sep 2021 15:33:52 +0000 (17:33 +0200)]
radv: do not use a different disk cache key for LLVM
The driver already adds a pipeline hash for LLVM which is redundant.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12938>
Jordan Justen [Tue, 21 Sep 2021 10:39:31 +0000 (03:39 -0700)]
Revert "intel/dev: Add display_ver and set adl-p to 13"
This reverts commit
c81acd365ed2a965741a828504d4a1498eaa3d3a.
Jordan Justen [Tue, 21 Sep 2021 10:39:27 +0000 (03:39 -0700)]
Revert "iris: Disable I915_FORMAT_MOD_Y_TILED_GEN12* on adl-p/display 13"
This reverts commit
4961f4c50fe29e4b3e6145bfafae7e5026027d12.
Jordan Justen [Thu, 16 Sep 2021 22:40:21 +0000 (15:40 -0700)]
iris: Disable I915_FORMAT_MOD_Y_TILED_GEN12* on adl-p/display 13
Cc: mesa-stable
Fixes:
e435511b580 ("intel/dev: Add device info for ADL GT2")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12908>
Jordan Justen [Thu, 16 Sep 2021 22:39:11 +0000 (15:39 -0700)]
intel/dev: Add display_ver and set adl-p to 13
Cc: mesa-stable
Fixes:
e435511b580 ("intel/dev: Add device info for ADL GT2")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12908>
Connor Abbott [Mon, 20 Sep 2021 12:16:55 +0000 (14:16 +0200)]
freedreno, turnip: Set TPL1_DBG_ECO_CNTL better
Match the blob better here. Note that the value of 0x1000000 for a650
comes from the Vulkan blob, and it's required to fix cubic filtering
even though the GLES driver doesn't set it (and doesn't support cubic
filtering).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5261
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12929>
Connor Abbott [Mon, 20 Sep 2021 11:53:14 +0000 (13:53 +0200)]
freedreno/a6xx: Name TPL1_DBG_ECO_CNTL
This is a guess, but an informed guess, since every other block with a
known DBG_ECO_CNTL register has it at the very beginning immediately
followed by ADDR_MODE_CNTL.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12929>
Andreas Baierl [Mon, 20 Sep 2021 15:07:00 +0000 (17:07 +0200)]
lima: Remove depth near/far workaround
because this is fixed now.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12804>
Andreas Baierl [Fri, 10 Sep 2021 12:33:55 +0000 (14:33 +0200)]
lima: Expose GL_EXT_clip_control
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12804>
Pierre-Eric Pelloux-Prayer [Mon, 20 Sep 2021 14:58:30 +0000 (16:58 +0200)]
radeonsi/test: use -t for deqp tests
deqp-runner added support for this.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12899>
Pierre-Eric Pelloux-Prayer [Mon, 20 Sep 2021 14:58:02 +0000 (16:58 +0200)]
radeonsi/test: don't require a folder name
Generate a temp one if the user didn't supply one.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12899>
Pierre-Eric Pelloux-Prayer [Thu, 16 Sep 2021 15:04:12 +0000 (17:04 +0200)]
radeonsi/sqtt: add si_se_is_disabled
Based on radv_se_is_disabled.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12899>
Pierre-Eric Pelloux-Prayer [Thu, 16 Sep 2021 14:39:16 +0000 (16:39 +0200)]
radeonsi/sqtt: export wave size and scratch size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12899>
Pierre-Eric Pelloux-Prayer [Thu, 16 Sep 2021 14:38:49 +0000 (16:38 +0200)]
radeonsi/test: update expected results
These tests were fixed in piglit.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12899>
Pierre-Eric Pelloux-Prayer [Thu, 16 Sep 2021 14:38:17 +0000 (16:38 +0200)]
radeonsi/test: fix typo in the test script
glcts results were copied over deqp results.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12899>
Samuel Pitoiset [Wed, 3 Mar 2021 08:35:18 +0000 (09:35 +0100)]
radv: remove useless assertions in the SQTT path
The driver aborts when the chip class is older than GFX8.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12854>
Samuel Pitoiset [Wed, 3 Mar 2021 08:32:55 +0000 (09:32 +0100)]
radv: make the SQTT BO a resident buffer
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12854>
Samuel Pitoiset [Tue, 2 Mar 2021 15:13:17 +0000 (16:13 +0100)]
radv: replicate THREAD_TRACE_CTRL config when stopping SQTT
This seems missed and it might be important.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12854>
Bas Nieuwenhuizen [Sat, 13 Mar 2021 23:44:06 +0000 (00:44 +0100)]
radv: Experimentally enable RT extensions.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Fri, 27 Aug 2021 02:20:59 +0000 (04:20 +0200)]
radv: Add caching for RT pipelines.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Mon, 23 Aug 2021 23:40:09 +0000 (01:40 +0200)]
radv: Add support for setting a dynamic stack size.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Fri, 27 Aug 2021 00:19:45 +0000 (02:19 +0200)]
radv: Combine all the parts together with a main loop for an RT pipeline.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Fri, 27 Aug 2021 00:17:19 +0000 (02:17 +0200)]
radv: Add ray traversal loop.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Fri, 27 Aug 2021 00:09:51 +0000 (02:09 +0200)]
radv: Add pass to lower anyhit shader into an intersection shader.
So we avoid having yet another shader calling loop. Such a thing
is not needed since neither shader types do recursion.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Fri, 27 Aug 2021 00:09:08 +0000 (02:09 +0200)]
radv: Add helper to parse raytracing stages.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Fri, 27 Aug 2021 00:07:57 +0000 (02:07 +0200)]
radv: Add helper to inline shaders into the main shader.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Wed, 25 Aug 2021 00:11:49 +0000 (02:11 +0200)]
radv: Add main loop variables.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Tue, 24 Aug 2021 00:36:21 +0000 (02:36 +0200)]
radv: Add scaffolding for RT pipeline compilation incl libraries.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Tue, 24 Aug 2021 00:00:00 +0000 (02:00 +0200)]
radv: Make some pipeline functions non-static.
Want to put the rt stuff in its own file. radv_pipeline.c is pretty
large already.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Mon, 22 Mar 2021 02:52:13 +0000 (03:52 +0100)]
radv: Add raytracing pipeline properties.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sun, 15 Aug 2021 22:04:30 +0000 (00:04 +0200)]
radv: Add group info to pipeline.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sat, 31 Jul 2021 21:42:32 +0000 (23:42 +0200)]
radv: Add pipeline type.
I want to keep pointers that need to be freed in the union and need
to figure out the type a destruction time. This seems more reliable
than checking the shader array in case we destroy mid-creation (i.e.
on failure).
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sat, 15 May 2021 20:27:39 +0000 (22:27 +0200)]
radv: Add RT cache flushes.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sat, 24 Jul 2021 10:12:11 +0000 (12:12 +0200)]
radv: Support nir_intrinsic_load_global_constant.
SPIR-V parsing can result in some direct constant usage for shader
records. Lower this early to a global based intrinsic so that it
doesn't interfere with the later 32-bit offset based constants
for scratch usage.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sun, 11 Apr 2021 13:45:27 +0000 (15:45 +0200)]
nir: Support ray launch size in divergence analysis.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sat, 10 Apr 2021 23:06:11 +0000 (01:06 +0200)]
aco: Add support for ray launch size.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sat, 10 Apr 2021 23:04:42 +0000 (01:04 +0200)]
radv: Add support for ray launch size.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Wed, 31 Mar 2021 00:53:33 +0000 (02:53 +0200)]
nir: Add AMD rt intrinsics.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Mon, 26 Jul 2021 10:06:05 +0000 (12:06 +0200)]
radv: Implement NULL accel struct descriptor write.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sun, 11 Apr 2021 14:01:40 +0000 (16:01 +0200)]
radv: Do more meta shader lowering.
Need this to clean up our generated RT pipeline.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Mon, 26 Jul 2021 09:01:38 +0000 (11:01 +0200)]
radv: Refactor some nir_channels usage to use nir_channel.
cleanup, nir_channels wasn't needed as these were only accessing a
single channel.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Mon, 26 Jul 2021 10:05:38 +0000 (12:05 +0200)]
aco: Implement call scope.
Since we do no repacking yet, just use invocation.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Mon, 19 Jul 2021 23:21:11 +0000 (01:21 +0200)]
radv: Modify load_sbt_amd intrinsic to get the descriptor.
That way we can get the address to the entry, which is needed for
some nir builtins because extra data in the entry can be used as
shader input.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Wed, 11 Aug 2021 00:24:01 +0000 (02:24 +0200)]
radv: Add bvh node definitions to a header.
So that we can avoid some magic numbers in the pipeline creation.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sun, 1 Aug 2021 12:47:20 +0000 (14:47 +0200)]
radv: Add optimized CPU BVH builds.
This trivial sorting helps speed up bad cases (like in CTS significantly).
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sat, 31 Jul 2021 01:43:52 +0000 (03:43 +0200)]
radv: Add more acceleration structure formats.
These are required ...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Wed, 28 Jul 2021 01:04:18 +0000 (03:04 +0200)]
radv: Add accel struct build support for the object-to-world matrix.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Sat, 24 Jul 2021 12:07:17 +0000 (14:07 +0200)]
radv: Fix arrayOfPointers for instances in accel struct build.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Bas Nieuwenhuizen [Thu, 24 Jun 2021 23:23:12 +0000 (01:23 +0200)]
radv: Fix CPU AABB build.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
Martin Krastev [Tue, 30 Mar 2021 15:56:47 +0000 (18:56 +0300)]
meson: introduce option vmware-mks-stats controlling the instrumentations of gallium svga driver
The new boolean option controls the instrumentations of gallium svga driver for mksGuestStats.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit
57760b7fe4eeb80acc8d6cd8bf6ec609a11a11dc)
(cherry picked from commit
12aed00f08bd95afd605cab34c833e81a4957dbd)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12873>
Martin Krastev [Sun, 31 Jan 2021 13:34:36 +0000 (15:34 +0200)]
svga: enable DRM mks-stats via hooking to the corresponding DRM ioctls
SVGA DRM stat calls were situated but did not actually register with the mks-stats
mechanism due to absence of corresponding ioctls. The employed new ioctls in vmwgfx
are DRM_VMW_MKSSTAT_ADD and DRM_VMW_MKSSTAT_REMOVE, subject to version check.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit
be47c077cc927c27a8c36342b47697aa81719677)
(cherry picked from commit
0388afc67b830f6ab916d0839c33eb1d91d6353f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12873>
Mike Blumenkrantz [Mon, 20 Sep 2021 18:59:38 +0000 (14:59 -0400)]
build: fix nine compilation with only zink enabled as a gallium driver
fixes #5360
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12943>
Mike Blumenkrantz [Mon, 20 Sep 2021 22:31:31 +0000 (18:31 -0400)]
zink: fix regex syntax from previous ci commit
argh
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12948>
Mike Blumenkrantz [Mon, 20 Sep 2021 22:00:49 +0000 (18:00 -0400)]
zink: disable miplevel tests in ci completely for now
I still can't repro, and I'm running these regularly on multiple platforms,
so they're not going to get any worse for the time being
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12947>
Philipp Zabel [Wed, 15 Sep 2021 16:19:02 +0000 (18:19 +0200)]
etnaviv: add mov for direct depth store output from load input
If the fragment shader writes fragment depth from an ALU instruction,
the register allocator makes sure that the instruction is pointed to the
correct register and write mask (t0.__z_).
If there is no instruction emitted because the source is an input
load intrinsic, or if the source instruction does not support swizzle
and write mask, we have to add a mov instruction for this to work.
Fixes piglit test spec@glsl-1.10@execution@glsl-1.10-fragdepth.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12891>
Emma Anholt [Sat, 18 Sep 2021 02:50:12 +0000 (19:50 -0700)]
nir_to_tgsi: Remove the abs on fcsel's bool src.
While the nir fcsel opcode specifies src0 != 0.0, as the comment says,
it's only ever used on bools-as-floats, so we know that src0 is
non-negative. This saves an instruction per CMP on i915.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12921>
Emma Anholt [Mon, 20 Sep 2021 17:46:45 +0000 (10:46 -0700)]
ci/freedreno: Update restricted trace sha1s.
Rendering changed slightly recently, but the diffs look fine.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12939>
Emma Anholt [Mon, 20 Sep 2021 17:07:40 +0000 (10:07 -0700)]
ci/baremetal: Retry if our network device spontaneously fails.
Seen in https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
13824132. It's
unlikely that graphics would kill the network, so just assume it's not our
fault and keep going.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12939>
Emma Anholt [Mon, 20 Sep 2021 17:04:08 +0000 (10:04 -0700)]
ci/freedreno: Add some cubearray piglit flakes on a630 I noticed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12939>
Emma Anholt [Mon, 20 Sep 2021 18:13:44 +0000 (11:13 -0700)]
freedreno: Assert to check for the previous regression.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12942>
Emma Anholt [Mon, 20 Sep 2021 18:11:30 +0000 (11:11 -0700)]
freedreno: Fix autotune regression since batch-cache rework.
I freed the key that autotune needed a little early.
Fixes:
b2349a46715e ("freedreno: Move the batch cache to the context.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12942>
Rob Clark [Tue, 14 Sep 2021 17:06:06 +0000 (10:06 -0700)]
turnip: Fix a6xx gen4 compute shaders
Port of
74d10525374 freedreno/a6xx: ("Fix a6xx gen4 compute shaders")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5354
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856>
Rob Clark [Tue, 14 Sep 2021 16:11:38 +0000 (09:11 -0700)]
turnip: Rast updates for a6xx gen4
Port of
219e12b7f39 ("freedreno/a6xx: Rast updates for a6xx gen3")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856>
Rob Clark [Tue, 14 Sep 2021 18:16:59 +0000 (11:16 -0700)]
turnip: Fix unitialized cs->device
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856>
Rob Clark [Tue, 14 Sep 2021 18:29:00 +0000 (11:29 -0700)]
freedreno: Add info->a6xx.has_shading_rate
@flto noticed these registers seem to be related to GL_QCOM_shading_rate
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856>
Danylo Piliaiev [Fri, 17 Sep 2021 14:06:41 +0000 (17:06 +0300)]
turnip: consider multiview_mask when clearing depth-stencil attachment
Otherwise only first layer is being cleared.
Would fix several VK_EXT_multi_draw tests:
dEQP-VK.draw.multi_draw.overlapping.normal.max_draws.*.vert_only.multiview.no_offset
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12913>
Timur Kristóf [Fri, 3 Sep 2021 11:05:47 +0000 (13:05 +0200)]
nir: Exclude non-generic patch variables from get_variable_io_mask.
These are I/O variables which are not going to be removed anyway.
However, get_variable_io_mask handles their location incorrectly.
Found using the GCC undefined behavior sanitizer.
Fixes the following error:
runtime error:
shift exponent
4294967258 is too large
for 64-bit type 'long unsigned int'
Closes: #5319
Fixes:
cf5f8f55c3e25508fb975b263d6430a93442247a
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12719>
Timur Kristóf [Fri, 3 Sep 2021 10:21:47 +0000 (12:21 +0200)]
ac/nir: Fix match_mask to work correctly for VS outputs.
match_mask checks the intrinsic type and decides whether it's
per-patch or not. VS don't have per-patch outputs,
so this causes wrong behaviour there.
Found using the GCC undefined behavior sanitizer.
Fixes the following error:
runtime error:
shift exponent
18446744073709551584 is too large
for 64-bit type 'long unsigned int'
Closes: #5319
Fixes:
bf966d1c1dd968116b8b547ca2739f5113caccb5
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12719>
Emma Anholt [Fri, 17 Sep 2021 17:50:32 +0000 (10:50 -0700)]
mesa/st: Allow loops in GLSL when NIR is enabled, even if the HW can't.
The jump lowering enabled by EmitNoLoops breaks GLSL's loop unrolling on
various obviously unrollable loops, resulting in a lot of deqp-gles2 and
piglit failures. NIR will help unroll whatever GLSL doesn't, so we can
trust the driver to apply that after GLSL's unrolling, so no need to ask
GLSL to lower all loops.
Fixes: #4979
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12917>
Emma Anholt [Fri, 17 Sep 2021 00:13:48 +0000 (17:13 -0700)]
ci/i915g: Clarify failure happening in fbo-fragcoord2.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12917>
Philipp Zabel [Thu, 16 Sep 2021 16:33:51 +0000 (18:33 +0200)]
etnaviv: fix dirty bit check for baselod emission
Since baselod is stored in sampler state, not sampler view, we should
check the ETNA_DIRTY_SAMPLERS bit instead of ETNA_DIRTY_SAMPLER_VIEWS.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12916>
Zachary Michaels [Wed, 8 Sep 2021 23:34:17 +0000 (16:34 -0700)]
X11: Ensure that VK_SUBOPTIMAL_KHR propagates to user code
Commit
0245b825 switched from returning the error code VK_ERROR_OUT_OF_DATE_KHR
to returning the success code VK_SUBOPTIMAL_KHR. Prior to that commit, the error
code caused all code paths to fail immediately, but the success code does not.
Currently the success code is not recorded in some scenarios, resulting in a
result of VK_SUCCESS instead. This breaks applications that rely on the
result (per the spec) to trigger resizes.
This commit ensures that the proper VK_SUBOPTIMAL_KHR success code is set as a
sticky status (as comments indicate was intended), ensuring that it is
propagated to user code.
Fixes #5331
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12782>
Samuel Pitoiset [Wed, 18 Aug 2021 15:25:22 +0000 (17:25 +0200)]
radv: keep depth/stencil images compressed for TRANSFER_DST on compute
Only if the image is TC-compat HTILE because it can be decompressed
on compute for partial copies.
This should remove few depth/stencil decompressions for RAGE2 and Red
Dead Redemption 2 because they declare all images as concurrent but
never use the compute queue for them.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12452>
Samuel Pitoiset [Wed, 18 Aug 2021 15:22:07 +0000 (17:22 +0200)]
radv: add support for copying compressed depth/stencil images on compute
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12452>
Samuel Pitoiset [Wed, 18 Aug 2021 15:02:09 +0000 (17:02 +0200)]
radv: implement depth/stencil expand on compute
This works as long as the image is TC-compatible HTILE.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12452>
Samuel Pitoiset [Wed, 18 Aug 2021 14:48:31 +0000 (16:48 +0200)]
radv: rename radv_decompress_depth_stencil()
To radv_expand_depth_stencil() for consistency.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12452>
Boris Brezillon [Mon, 20 Sep 2021 12:43:05 +0000 (14:43 +0200)]
panfrost/ci: Skip the indirect_draw+XFB tests
We lack a dependency between the vertex job filling the indirect draw
buffers and the indirect draw compute job reading from these buffers,
leading to unreliable results (the tests pass if the vertex job is
done before the compute job starts, and fail otherwise). Let's disable
those tests until we sort it out.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12589>
Boris Brezillon [Mon, 20 Sep 2021 11:51:10 +0000 (13:51 +0200)]
panfrost: Fix collision in the indirect draw shader table
Min/max index search shaders are different for the !primitive_restart
and primitive_restart. We need to add entries for the primitive restart
cases otherwise we might retrieve a wrong shader from the cache.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12589>
Boris Brezillon [Tue, 24 Aug 2021 08:48:40 +0000 (10:48 +0200)]
panfrost: Fix indirect draws when vertex or instance count is 0
In that case we should just skip the vertex/tiler jobs as done in the
direct draw path.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12589>
Italo Nicola [Mon, 20 Sep 2021 07:18:56 +0000 (07:18 +0000)]
panfrost: fix null deref when no color buffer is attached
Do not dereference color buffer #0 in the SFBD code path if no color buffer is
attached, as with depth-only attachments. Fixes a crash running glmark2 -b
shadow on Mali T720.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Fixes:
c746747cb82 ("panfrost: fix GL_EXT_multisampled_render_to_texture regression")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12927>
Boris Brezillon [Wed, 4 Aug 2021 11:45:47 +0000 (13:45 +0200)]
panfrost: Prepare shader helpers to per-gen XML
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12935>
Boris Brezillon [Fri, 6 Aug 2021 12:24:31 +0000 (14:24 +0200)]
panfrost: Prepare texture helpers to per-gen XML
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12935>
Boris Brezillon [Fri, 6 Aug 2021 12:09:43 +0000 (14:09 +0200)]
panfrost: Prepare pan_encoder.h to per-gen XML
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12935>
Boris Brezillon [Fri, 6 Aug 2021 12:03:25 +0000 (14:03 +0200)]
panfrost: Prepare scoreboard helpers to per-gen XML
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12935>
Boris Brezillon [Fri, 6 Aug 2021 08:22:28 +0000 (10:22 +0200)]
panfrost: Prepare pandecode to per-gen XML
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12935>
Boris Brezillon [Fri, 6 Aug 2021 08:12:31 +0000 (10:12 +0200)]
panfrost: Move panfrost_major_version() to gen_macros.h
So we can use this function in decode_common.c when transitioning to
per-gen XML. While at it rename the function pan_arch().
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12935>
Boris Brezillon [Fri, 6 Aug 2021 11:31:47 +0000 (13:31 +0200)]
panfrost: Prepare pan_cs helpers to per-gen XML
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12935>
Boris Brezillon [Fri, 6 Aug 2021 09:46:20 +0000 (11:46 +0200)]
panfrost: Prepare blend helpers to per-gen XML
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12935>
Boris Brezillon [Fri, 6 Aug 2021 09:33:17 +0000 (11:33 +0200)]
panfrost: Prepare blitter helpers to per-gen XML
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12935>
Boris Brezillon [Mon, 20 Sep 2021 09:53:23 +0000 (11:53 +0200)]
panfrost: RGB332_UNORM is not a valid texture format on v6+
Cc: mesa-stable
Fixes:
c6bdd976e611 ("panfrost: Split out v6/v7 format tables")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12508>
Boris Brezillon [Tue, 7 Sep 2021 12:22:59 +0000 (14:22 +0200)]
panfrost: Drop the R and T flags on SCALED formats
Sampling from SCALED textures / rendering to SCALED FBOs is a bit tricky
(requires extra int <-> float conversions in a few places).
mesa/st only use SCALED formats as vertex formats, and those formats
are optional in Vulkan, so let's drop the RENDER/TEXTURE flags to keep
things simple.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Suggested-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12508>
Boris Brezillon [Tue, 7 Sep 2021 09:16:50 +0000 (11:16 +0200)]
panfrost: RGB10_A2_SNORM is not a valid texture format on v6+
Cc: mesa-stable
Fixes:
c6bdd976e611 ("panfrost: Split out v6/v7 format tables")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12508>
Boris Brezillon [Wed, 19 May 2021 09:38:14 +0000 (11:38 +0200)]
panfrost: Fix the Z32_S8X24 and X32_S8X24 definitions
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12508>
Boris Brezillon [Mon, 23 Aug 2021 15:46:18 +0000 (17:46 +0200)]
panfrost: Patch Z32_S8X24 format when creating a sampler view
The gallium driver always stores Z32_S8X24 textures on 2 different
planes. Let's fix the create_sampler_view() logic so we can support
single-planar Z32_S8X24 in the vulkan driver.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12508>
Timur Kristóf [Thu, 9 Sep 2021 08:33:50 +0000 (10:33 +0200)]
ac/nir: Remove byte permute from prefix sum of the repack sequence.
The byte-permute instruction v_perm_b32 is not exposed by older
LLVM releases (only available on LLVM 13 and later), therefore a new
sequence is needed which we can use with these LLVM versions too.
The prefix sum is replaced by two alternatives:
1. For GPUs that support v_dot, we shift 0x01 to the wanted byte
positions and then use v_dot to sum the results.
2. For older GPUs (Navi 10), we simply shift out the unwanted bytes
and use v_sad_u8 to produce the sum.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12786>
Timur Kristóf [Thu, 9 Sep 2021 06:27:21 +0000 (08:27 +0200)]
aco/isel: Fix emit_vop2_instruction to apply 16/24-bit flags properly.
Previously it used a builder function but didn't use the return
value from that function, so the flags were not applied.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12786>
Timur Kristóf [Thu, 9 Sep 2021 06:38:41 +0000 (08:38 +0200)]
aco: Add ability to optimize v_lshl + v_sub into v_mad_i32_i24.
Also change combine_add_lshl to use check_vop3_operands instead
of its own checks of the operands.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12786>