zink: Enable nir_lower_frexp.

This will enable GLSL to drop its frexp lowering in the frontend.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

nouveau: Enable frexp lowering in the backend.

This would be desired for NVK using this backend, but also for getting
lowering out of the GLSL frontend.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

nouveau: Add missing nir_opt_algebraic_late.

This was needed for nir_lower_frexp, but it's a win anyway.  shader-db
results:

total gpr in shared programs: 1143621 -> 1143502 (-0.01%)
gpr in affected programs: 33918 -> 33799 (-0.35%)

total instructions in shared programs: 7829415 -> 7820124 (-0.12%)
instructions in affected programs: 1204967 -> 1195676 (-0.77%)

total bytes in shared programs: 71802760 -> 71717352 (-0.12%)
bytes in affected programs: 11031888 -> 10946480 (-0.77%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

ir3: Move turnip's nir_lower_frexp to the shared compiler.

We had NIR lowering for Vulkan, and rely on GLSL's lowering in the
frontend, but this will let us drop the GLSL lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

intel: Always call nir_lower_frexp.

We have NIR lowering for Vulkan, and rely on GLSL's lowering in the
frontend, but this will let us drop the GLSL lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

state_tracker: Lower frexp before lowering doubles.

We don't have softfp64 for frexp, it has been lowered in GLSL up until
now.  I didn't bother splitting out 32 from 64 because it's not worth any
effort.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl/softfp64: Add fisfinite lowering.

This is generated by nir_lower_frexp, and if we leave fisfinite in place
then the late algebraic pass lowering it to this pattern will cause an
un-lowered fabs64 to be emitted.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl/softfp64: GC the temp vars after we lower them to SSA.

They don't serve any purpose other than taking up memory and cluttering
your compiler output at this point.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl: Retire ldexp lowering in favor of the nir lowering flag.

Compilers need to set the nir flag anyway for vulkan, so just pass ldexp
through to NIR and let that handle it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

zink: Add mapping for nir_op_ldexp, but disable it for 64-bit's sake.

We previously had GLSL do ldexp lowering to bitops, but NIR can do it
instead.  It's tempting to just pass the NIR op through to the host Vulkan
driver, but to do that we'd need to split up NIR's flag between 32 and
64-bit support, and that's not worth anyone's time for an op we've never
seen used.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl: Move ForceGLSLAbsSqrt handling to glsl-to-nir.

Cutting more GLSL lowering pass in favor of nir builder.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

radv: fix leak of nir from retained shaders

if shaders are found in the app cache above, execution will goto done:
and the nir must still be freed

Fixes: 03d2bd6042d ("radv: ensure to retain NIR shaders for GPL libs found in the cache")

fixes #8786

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22317>

panfrost: assign the correct create_for_resource from the start

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22322>

util/disk_cache: Move blob_put_cb to the async queue

Move deflate and put to the queue for the blob cache case.  This moves
the overhead out of the app thread when storing new shaders.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>

util/disk_cache: Use queue state to skip put

If we move the blob-cache path into the async queue, then
path_init_failed is no longer a good way to check if puts
should be a no-op.  But fortunately checking if the queue
is initialized is, and is a more obvious check because
what it is guarding is a util_queue_add_job().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>

util/disk_cache: Add NONE type

Add an explicit enum for the DISK_CACHE_NONE type so that we don't
confuse with the MULTI_FILE case on android when the blob-cache is
used.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>

util/disk_cache: Split out queue initialization

Split out a helper to initialize the queue, as we'll want to re-use this
for the blob-cache case.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>

intel/compiler: Support fmul_fsign opt for fp64 when int64 isn't supported

MTL support fp64, but not int64. The fsign(double(x))*FOO optimization
would try to use a 64-bit int xor operation to conditionally toggle
the sign bit off the result.

Since this only affects high bit of the result, we can do a 32-bit
move of the low dword, and a 32-bit xor on the high dword.

Fixes dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp64.input_args.modf_denorm_flush_to_zero
on MTL.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22259>

radv/amdgpu: Remove can_patch and chained submit code path.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv: Chain cmd buffers in queue code when possible, not in winsys.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Unchain CS array in queue code not in winsys.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Walk chained CS objects for BO list.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Remember which CS the current one is chained to.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Extract radv_amdgpu_add_cs_to_bo_list function.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Expose CS chain and unchain on the winsys.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Extract CS chain and unchain functions.

Also add a comment that explains what chaining means
and add a check to make sure the HW IP type supports it.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

ci: implement sections for cuttlefish

Reviewed-by: Helen Koike <helen.koike@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22005>

radv: emit the PS epilog after the graphics pipeline

Otherwise, SPI_SHADER_PGM_RSRC1_PS is overwritten when the graphics
pipeline is emitted.

Fixes: 5c362cde33b ("radv: update PS num_vgprs in case of epilogs rather than overallocating VGPRs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22310>

vc4/ci: add another sync flake

https://gitlab.freedesktop.org/mesa/mesa/-/jobs/39377396

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22312>

glthread: use id 0 for internal buffer objects

-1 is an invalid buffer index which breaks app expectations, specifically
apitrace, which checks for return value of 0 from checking buffer bindings
to determine whether to inject user vertex buffer bindings and create functional
traces

this should fix capturing traces with drivers using glthread

fixes #8383

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22293>

intel/fs: also allow vec8+ vectorization of load_global_const_block_intel

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: optimize uniform SSBO & shared loads

Using divergence analysis, figure out when SSBO & shared memory loads
are uniform and carry the data only once in register space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

nir: add 2 new intel intrinsics for uniform ssbo/shared loads

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

nir: reuse nir_component_mask() where it makes sense

Avoiding local bit field manipulations.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: factor out lsc surface descriptor settings

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: copy instruction sources in logical send lowering

Having references to inst->src[X] when you're also modifying
inst->src[X] is a receipe for disaster. Making changes to the lowering
code I've been bitten quite a few times by this take copies of all
sources to do the lowering.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: UNDEF fixup_nomask_control_flow temp register

Ensure that the register's liveness is not expanded to loops.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: don't consider fixup_nomask_control_flow SENDs predicate

Those SENDs are still doing a full register write. We just inserted
some predication for a workaround.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: run VGRF compaction just before max live register accounting

There are a number of instances of the dead code elimination pass that
could reduce the count. For some reason this also seems to affect
register allocation itself.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

anv: ignore structure types handled in vk_device_memory_create

Without that we get warning from anv_debug_ignored_stype, called in
the default case.

Fixes: 4b0b75c27a7 ("anv: Use the new vk_device_memory base struct")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22295>

broadcom/ci: run gl jobs on arm64, just like vk

These were running on armhf because that's the default in the custom
distro that Raspberry Pi provides, but arm64 is ~20% faster, and we
already run weekly tests on both arm64 & armhf, so let's keep only the
faster one in the pre-merge path.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22272>

r600/sfn: fix container allocators

This fixes leaks in TexInstr and in Shader.

Thanks to Patrick Lerda for pointing out the bug.

Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
    r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22300>

radv: fix VS prologs with GPL and static binding stride

When a graphics pipeline library is created with only the vertex input
state, the driver binds this state at pipeline bind time. Though the
vertex binding stride is not necessarily dynamic, in this case the
pipeline stride should be used.

This fixes GPU hangs with recent
dEQP-VK.pipeline.fast_linked_library.vertex_input.*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22285>

v3d,v3dv: stop trying to force 16-bit TMU output for shadow comparisons

In V3D we were doing this incorrectly by peeking into the sampler state
unconditionally, which is not correct if the TMU operations don't use
sampler state at all (like PBOs). This was causing us to fail the second
test in this sequence when both tests run back back to back in the same
process:

dEQP-GLES3.functional.texture.shadow.2d.linear.greater_or_equal_depth_component32f
dEQP-GLES3.functional.texture.specification.teximage2d_pbo.rg32f_cube

Here, the first test would setup sampler state for shadow comparisons and
the second test would setup a PBO upload, which would incorrectly pick
up the sampler state to decide about the TMU output size for the PBO
operation.

In V3DV we were doing this right looking through each texture/sampler
instruction and checking if they all involved shadow comparisons or had
relaxed precission, defaulting to 32-bit otherwise.

This special-casing for shadow comparisons also leaks from drivers
into the compiler where we are forced to emit some pieces of sampler
state for 32-bit outputs, so we had to special-case shadow instructions
there as well and we also had a fix for CS textures not having correct
sampler state representing shadow operations too. Finally,
we also had  at least a couple of bugs where forcing 32-bit TMU output
through V3D_DEBUG wasn't correctly forcing shadow comparisons to actually
be 32-bit in all the right places, leading to visual bugs with the
option enabled (Sponza being one example of this). This change eliminates
all of these issues.

Finally, the performance improvement observed from special casing shadow
comparison is negligible, and in specific scenarios it can even be
detrimental to performance due to increased register pressure (Sponza with
PCF filtering set to 4 is an example of this again).

Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8684
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22284>

vulkan/wsi/display: set pDisplay to NULL on error

the spec for vkGetDrmDisplayEXT says:

  "If there is no VkDisplayKHR corresponding to the connectorId on the
   physicalDevice, the returning display must be set to VK_NULL_HANDLE.
   The provided drmFd must correspond to the one owned by the physicalDevice.
   If not, the error code VK_ERROR_UNKNOWN must be returned. (...)
   The given connectorId must be a resource owned by the provided drmFd.
   If not, the error code VK_ERROR_UNKNOWN must be returned"

We were only setting the display pointer to VK_NULL_HANDLE if the provided
drmFd was valid, however, there are CTS tests checking that it is also set
to NULL when it is not.

Fixes the following test on all drivers exposing EXT_acquire_drm_display
(tested with Intel and V3DV):
dEQP-VK.wsi.acquire_drm_display.acquire_drm_display_invalid_fd

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22283>

v3dv: always acquire display device before checking if we can present

Usually, we postpone acquisition until a swapchain is created, but there are
some cases with display extensions (at least with EXT_acquire_drm_display)
where we need to acquire before a swapchain is ever created.

Fixes various tests in:
dEQP-VK.wsi.acquire_drm_display.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22283>

v3dv: drop unused parameter

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22283>

llvmpipe: clean-up llvmpipe_get_query_result()

Get rid of the uint64 result pointer which was used by some query
types.  Handle each switch case with self-contained code.  Remove
unneeded casts.  Use MIN2/MAX2 macros.

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>

llvmpipe: s/unsigned/enum pipe_query_type/

Note we should do the same for pipe_context::create_query()'s
query_type parameter.  That would touch quite a few files.

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>

llvmpipe: s/tabs/spaces/

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>

llvmpipe: rename some vars related to occlusion query and ps invocations

More consistent naming.

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>

llvmpipe: fix ps invocations query bug

We were not initializing the PS invocation count to zero before
computing the sum of the per-thread results.

This fixes an issue where querying the result of the query more
than once would cause the result to grow larger each time.

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>

iris: report draw count for perfetto

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22296>

ci: remove unused rules

These are no longer used.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22263>

virgl/ci: clean up manual rules for virgl

In f6c06ef2f66 ("ci: Add manual rules variations to disable irrelevant
driver jobs."), we fixed this for *most* driver. This fixes up the last
driver, hopefully removing an annoying needless button in the UI for
some MRs.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22263>

ci: move virgl-rules after intel-rules

We're about to add a dependency on stuff from the intel-rules, and
moving virgl down here allows us to depend on them without having to
move the definition out of the intel-section.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22263>

zink: rework choose_pdev (again)

there are two cases to be handled here:
* normal
* software

the latter case requires env vars based on the frontend, and if a sw
device isn't found then init should fail

the former case should (in theory) just yolo the first device and assume
that's what the user wanted based on whatever env vars and layers are
in use

fixes #7508, #7132

maybe also affects #8152

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22184>

Revert "microsoft/compiler: Use SRVs for read-only images"

This reverts commit 54c32aeba6300f5cafc2bae18020398645925969.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22289>

spirv: Assume input attachments are read-only

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22289>

spirv2dxil: Split read-only image as SRV logic into declared and inferred

Fixes: e0a090ad ("spirv2dxil: Only lower readonly images to SRVs when the option is set")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22289>

dzn: Claim fillModeNonSolid

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22277>

dzn: Handle polygon point mode

Note: The meaning of clockwise vs counter-clockwise changes after the
yz flip, therefore the determination of winding needs to be done before
the yz flip logic. Therefore the yz flip is moved to the GS and applied
as a lowering on top of the base GS.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22277>

dzn: Add a helper to generate triangle->point GS

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22277>

spirv2dxil: Expose yz flip pass to external callers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22277>

d3d12: Move forward-front-face pass to common DXIL code

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22277>

r600: fix typo that could lead to a possible crash

For instance, with "piglit/bin/arb_shader_image_load_store-host-mem-barrier --quick -auto -fbo":
==18549==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x61200000a059 at pc 0x7f65d8937b80 bp 0x7fff6ed19a00 sp 0x7fff6ed199f8
READ of size 1 at 0x61200000a059 thread T0
    #0 0x7f65d8937b7f in evergreen_set_shader_images ../src/gallium/drivers/r600/evergreen_state.c:4277
    #1 0x7f65d6b471b8 in st_bind_images ../src/mesa/state_tracker/st_atom_image.c:172
    #2 0x7f65d6b76b26 in st_validate_state ../src/mesa/state_tracker/st_util.h:129
    #3 0x7f65d6b76b26 in prepare_draw ../src/mesa/state_tracker/st_draw.c:88
    #4 0x7f65d6b77c8a in st_draw_gallium ../src/mesa/state_tracker/st_draw.c:141
    #5 0x7f65d72698a2 in _mesa_draw_arrays ../src/mesa/main/draw.c:1202

Fixes: a6b379284365 ("r600: add core pieces of image support.")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22273>

vc4/ci: add arm64 failure to flakes as it works on armhf

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22297>

gallium/pipe: change PIPE_DEFAULT_DECODER_FEEDBACK_TIMEOUT_NS to 1 second

Fixes: 5e1bd07a ("radeonsi: vcn: implement the get_decoder_fence vfunc")
The commit [5e1bd07a] puts a timeout on fence_wait which causes a 8k AV1
decoding regression on gfx940. By adding DECODER_FEEDBACK_TIMEOUT to
add fence wait time.

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22268>

docs: Claim less functionality for glsl_compiler.

It doesn't generate GPU code, just GLSL IR code.  Also, clarify where to
find the built tool, and what the options do.

Closes: #8674
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22271>

ci: Add missing dependency on doxygen sources for docs-generation jobs.

!22191 broke docs generation and marge didn't notice because of missing
 deps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22271>

docs: Update Vulkan renderpass docs for !22191

Fixes: 6ad5f885afef ("vulkan: Drop VkRenderingSelfDependencyInfoMESA")
Closes: #8773
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22271>

i915: hook new get_fd proc for drm winsys

Fixes: 853b4801f27 ("i915: Add support for `get_screen_fd`")
Signed-off-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22294>

virgl: hook new get_fd proc for drm winsys

Fixes: 2ade6917dacb ("virgl: Add support for `get_screen_fd`")
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22292>

radv: update PS num_vgprs in case of epilogs rather than overallocating VGPRs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22267>

aco: don't use shared VGPRs for shaders consisting of multiple binaries

When using multiple binaries, we don't know the required number of VGPRs beforehand,
which means we either have to over-allocate VGPRs or avoid shared VGPRs.
As bpermute is the only instructions needing shared VGPRs, we decide for the latter.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22267>

aco/ra: adjust_max_used_regs() for fixed Operands

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22267>

aco: split ps_epilog args before exporting them

This avoids some unnecessary copies from extracting from the input vectors.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22267>

anv: Drop dead code that sets the L3BypassDisable field

These helper functions will only get invoked for GFX < 11 and the
L3BypassDisable field is present starting from GFX12+.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22275>

anv: Drop unused param from add_surface_reloc

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22275>

ci/zink: Disable godot-tps-gles3 on a630.

This trace used too much memory to be run in parallel with our other
traces.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22279>

Uprev Piglit to 2391a83d1639a7ab7bbea02853b922878687b0e5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22279>

radv: enable shaders cache for libraries with GPL

This was the last missing feature for GPL. The main problem is that
the on-disk shaders cache size will increase a lot because we don't
deduplicate shaders but there is on-going work to improve that.

We also can't use the shaders cache for libraries created with the
RETAIN_LINK_TIME_OPTIMIZATION flag and module identifiers because we
don't know the SPIR-V and thus can't retain NIR shaders for linking.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: ensure to retain NIR shaders for GPL libs found in the cache

Even if we are able to get the assembly from the shaders cache for
graphics pipeline libraries, we still need to retain NIR shaders in
case the LTO pipelines won't be find in the cache.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: add VkGraphicsPipelineLibraryFlag to the graphics pipeline key

This is to generate a different key for a library created with
FRAGMENT_SHADER_BIT and no FS (ie. it would generate a noop FS) and
a library created with FRAGMENT_OUTPUT_INTERFACE with no CB attachments.

Otherwise, the same key would be generated and this would corrupt
the cache.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: remove dead code in radv_pipeline_get_nir()

We either import the NIR or the assembly, so this was never reached.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: allow to create/insert PS epilogs from/to the cache for libs

To cache PS epilogs compiled inside graphics pipeline libraries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: rely on non-NULL binaries when inserting shaders to the cache

With GPL, a stage can be imported from a library which means that the
binary is NULL (it's freed right after compilation) but the shader is
non-NULL. To avoid crashing, rely on non-NULL binaries because this
implies that the shader is non-NULL as well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

radv: only copy non-NULL shaders when loaded from the cache

With GPL, we don't necessarily load all stages from the same cache
entry and other stages might have been imported from libraries, so
don't overwrite them.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22264>

nir, spirv: Add support for VK_EXT_fragment_density_map

This involves two new system values.

Reviewed-by: Faith Ekstrand <faith@gfxstrand.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20303>

ci/zink: Drop validation exception for leaks at device destroy.

Between the recent glthread and zink fixes, we should be good to go.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

radeonsi: update test results

This test was fixed by bf910c94e06 ("glsl: fix gl_CullDistance lowering
from float[8] to vec4[2]").

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

util/vbuf: fix index_bo leak

When indices are unrolled we still have to release the index_bo
references passed to us.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8272
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

util/vbuf: clarify indirect draws handling

It wasn't obvious from the u_vbuf code alone that num_draws
is guaranteed to be 1 in the indirect case.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

mesa: fix invalid index_bo refcounting

If take_index_buffer_ownership is true, then we should reserve
enough references of index_bo or we'll get an underflow later.

Fixes: 819627041e7 ("mesa: set pipe_draw_info::index::resource directly and remove gl_bo")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8747
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22237>

zink: be explicit about separate shader dsl indexing during creation

this fixes a minor issue where a fs without a vs dsl would have the wrong
index

Fixes: e3b746e3a31 ("zink: use GPL to handle (simple) separate shader objects")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22269>

anv: check for MESA_SHADER_TESS_CTRL with get_tcs_prog_data

Fixes: 86d931724db ("anv: Implement Wa_14015297576")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22282>

anv: take primitive ID override to account Wa_14015297576

Commit ca4ec49b0e0 took primitive ID override fields in to use, this
has to be checked as part of Wa_14015297576.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22282>

zink: always store nir serialized

this saves a ton of memory and has minimal, if any cpu impact

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: store num_inlinable_uniforms separately for cs programs

compute is a special case because the zink_shader itself is created
in a thread, which means it cannot be accessed directly at bind time
since it may not have finished creating itself yet

to avoid prematurely waiting on an async fence, the one value needed
at bind time can instead be stored separately

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>

zink: move nir cloning out to callers of zink_shader_compile

this will make more sense with future changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>