Simon Pilgrim [Fri, 2 Oct 2020 17:16:55 +0000 (18:16 +0100)]
Revert rG3d14a1e982ad27 - "[InstCombine] recognizeBSwapOrBitReverseIdiom - support for 'partial' bswap patterns (PR47191)"
This reverts commit
3d14a1e982ad27111346471564d575ad5efc6419.
This is breaking on some 2stage clang buildbots
Thomas Raoux [Fri, 2 Oct 2020 17:11:22 +0000 (10:11 -0700)]
[mlir][vector] Add canonicalization patterns for extractMap/insertMap
Add basic canonicalization patterns for the extractMap/insertMap to allow them
to be folded into Transfer ops.
Also mark transferRead as memory read so that it can be removed by dead code.
Differential Revision: https://reviews.llvm.org/D88622
Simon Pilgrim [Fri, 2 Oct 2020 17:04:56 +0000 (18:04 +0100)]
[InstCombine] Add trunc(bswap(trunc/zext(x))) vector tests
Louis Dionne [Mon, 21 Sep 2020 21:08:53 +0000 (17:08 -0400)]
[libc++] Remove unnecessary usage of <iostream> in the test suite
Tests should strive to be as minimal as possible, since it makes them
relevant on platforms where <iostream> does not work.
Jonas Devlieghere [Fri, 2 Oct 2020 16:53:30 +0000 (09:53 -0700)]
[lldb] Fix bug in fallback logic for finding the resource directory.
Both of the if-clauses modify the raw_path variable and only one of them
was resetting the variable for the fallback. Avoid future bugs like that
by always resetting the variable.
Differential revision: https://reviews.llvm.org/D88704
Florian Hahn [Fri, 2 Oct 2020 16:36:22 +0000 (17:36 +0100)]
[VPlan] Use isa<> instead of directly checking VPRecipeID (NFC).
getVPRecipeID is intended to be only used in `classof` helpers. Instead
of checking it directly, use isa<> with the correct recipe type.
Nikita Popov [Thu, 1 Oct 2020 20:42:14 +0000 (22:42 +0200)]
[MemCpyOpt] Regnerate test checks (NFC)
zhanghb97 [Wed, 30 Sep 2020 06:11:46 +0000 (14:11 +0800)]
[mlir] Add Float Attribute, Integer Attribute and Bool Attribute subclasses to python bindings.
Based on PyAttribute and PyConcreteAttribute classes, this patch implements the bindings of Float Attribute, Integer Attribute and Bool Attribute subclasses.
This patch also defines the `mlirFloatAttrDoubleGetChecked` C API which is bound with the `FloatAttr.get_typed` python method.
Differential Revision: https://reviews.llvm.org/D88531
Stephen Neuendorffer [Thu, 30 Jul 2020 21:47:42 +0000 (14:47 -0700)]
[MLIR] Better message for FuncOp type mismatch
Previously the actual types were not shown, which makes the message
difficult to grok in the context of long lowering chains. Also, it
appears that there were no actual tests for this.
Differential Revision: https://reviews.llvm.org/D88318
Sanjay Patel [Fri, 2 Oct 2020 16:24:02 +0000 (12:24 -0400)]
[CostModel] move default handling after switch; NFC
We will need to add intrinsics to the switch (such as
the ones that are currently in the switch above this
one) that deal with special cases and then break to
the default handling.
Stella Stamenova [Fri, 2 Oct 2020 16:26:21 +0000 (09:26 -0700)]
Revert "[WebAssembly] Emulate v128.const efficiently"
This reverts commit
542523a61a21c13e7f244bcf821b0fdeb8c6bb24.
Simon Pilgrim [Fri, 2 Oct 2020 16:15:32 +0000 (17:15 +0100)]
[InstCombine] recognizeBSwapOrBitReverseIdiom - support for 'partial' bswap patterns (PR47191)
If we're bswap'ing some bytes and zero'ing the remainder we can perform this as a bswap+mask which helps us match 'partial' bswaps as a first step towards folding into a more complex bswap pattern.
Differential Revision: https://reviews.llvm.org/D88578
Simon Pilgrim [Fri, 2 Oct 2020 14:30:48 +0000 (15:30 +0100)]
TruncInstCombine.cpp - fix header include ordering to fix llvm-include-order clang-tidy warning. NFCI.
Simon Pilgrim [Fri, 2 Oct 2020 14:29:21 +0000 (15:29 +0100)]
TruncInstCombine.cpp - use auto * to fix llvm-qualified-auto clang-tidy warning. NFCI.
Vinay Madhusudan [Fri, 2 Oct 2020 16:11:02 +0000 (17:11 +0100)]
[AArch64] Generate dot for v16i8 sum reduction to i32
Convert VECREDUCE_ADD( EXTEND(v16i8_type) ) to VECREDUCE_ADD( DOTv16i8(v16i8_type) ) whenever the result type is i32. This gains in one of the SPECCPU 2017 benchmark.
This partially solves the bug: https://bugs.llvm.org/show_bug.cgi?id=46888
Meta ticket: https://bugs.llvm.org/show_bug.cgi?id=46929
Differential Revision: https://reviews.llvm.org/D88577
Utkarsh Saxena [Wed, 30 Sep 2020 12:57:47 +0000 (14:57 +0200)]
[clangd] Add bencmark for measuring latency of DecisionForest model.
Differential Revision: https://reviews.llvm.org/D88590
Diego Caballero [Fri, 2 Oct 2020 15:42:13 +0000 (08:42 -0700)]
[mlir] Fix call op conversion in bare-ptr calling convention
We hit an llvm_unreachable related to unranked memrefs for call ops
with scalar types. Removing the llvm_unreachable since the conversion
should gracefully bail out in the presence of unranked memrefs. Adding
tests to verify that.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D88709
Nicolas Vasilache [Fri, 2 Oct 2020 14:02:53 +0000 (10:02 -0400)]
[mlir] Attempt to appease gcc-5 const char* -> StringLiteral conversion issu
serge-sans-paille [Thu, 23 Jul 2020 14:22:48 +0000 (16:22 +0200)]
Fix interaction between stack alignment and inline-asm stack clash protection
As reported in https://github.com/rust-lang/rust/issues/70143 alignment is not
taken into account when doing the probing. Fix that by adjusting the first probe
if the stack align is small, or by extending the dynamic probing if the
alignment is large.
Differential Revision: https://reviews.llvm.org/D84419
Denis Antrushin [Thu, 1 Oct 2020 08:09:57 +0000 (15:09 +0700)]
[Statepoints][ISEL] visitGCRelocate: chain to current DAG root.
This is similar to D87251, but for CopyFromRegs nodes.
Even for local statepoint uses we generate CopyToRegs/CopyFromRegs
nodes. When generating CopyFromRegs in visitGCRelocate, we must chain
to current DAG root, not EntryNode, to ensure proper ordering of copy
w.r.t. statepoint node producing result for it.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D88639
Yaxun (Sam) Liu [Fri, 2 Oct 2020 14:32:52 +0000 (10:32 -0400)]
Fix failure in test hip-macros.hip
requires amdgpu-registered-target.
Kamil Rytarowski [Fri, 2 Oct 2020 14:13:09 +0000 (16:13 +0200)]
[compiler-rt] [netbsd] Improve the portability of ThreadSelfTlsTcb
Use __lwp_gettcb_fast() and __lwp_getprivate_fast(), as _lwp_getprivate()
can be a biased pointer and invalid for use in this function on all CPUs.
LLVM GN Syncbot [Fri, 2 Oct 2020 14:24:01 +0000 (14:24 +0000)]
[gn build] Port
0c1bb4f8851
Paul C. Anagnostopoulos [Tue, 22 Sep 2020 17:58:54 +0000 (13:58 -0400)]
[TableGen] New backend to print detailed records.
Pertinent lints are fixed.
Yaxun (Sam) Liu [Sun, 27 Sep 2020 02:28:04 +0000 (22:28 -0400)]
Emit predefined macro for wavefront size for amdgcn
Also fix the issue of multiple -m[no-]wavefrontsize64
options to make the last one wins.
Differential Revision: https://reviews.llvm.org/D88370
Haojian Wu [Fri, 2 Oct 2020 14:01:25 +0000 (16:01 +0200)]
[clangd] Extend the rename API.
several changes:
- return a structure result in rename API;
- prepareRename now returns more information (main-file occurrences);
- remove the duplicated detecting-touch-identifier code in prepareRename (which is implemented in rename API);
Differential Revision: https://reviews.llvm.org/D88634
Simon Pilgrim [Fri, 2 Oct 2020 13:55:53 +0000 (14:55 +0100)]
[Analysis] Drop local maxAPInt/minAPInt helpers. NFCI.
Use standard APIntOps::smax/smin helpers instead.
Alexandre Ganea [Fri, 2 Oct 2020 13:53:43 +0000 (09:53 -0400)]
[LLD] Fix /time formatting for very long runs. NFC.
Alexandre Ganea [Fri, 2 Oct 2020 13:36:11 +0000 (09:36 -0400)]
[LLD][COFF] Add more type record information to /summary
This adds the following two new lines to /summary:
21351 Input OBJ files (expanded from all cmd-line inputs)
61 PDB type server dependencies
38 Precomp OBJ dependencies
1420669231 Input type records <<<<
78665073382 Input type records bytes <<<<
8801393 Merged TPI records
3177158 Merged IPI records
59194 Output PDB strings
71576766 Global symbol records
25416935 Module symbol records
2103431 Public symbol records
Differential Revision: https://reviews.llvm.org/D88703
Louis Dionne [Thu, 1 Oct 2020 00:05:41 +0000 (20:05 -0400)]
[libc++] Move the weak symbols list to libc++abi
Those symbols are exported from libc++abi in the first place, so it
makes more sense to have them there.
Simon Pilgrim [Fri, 2 Oct 2020 12:56:13 +0000 (13:56 +0100)]
BlockFrequencyInfoImpl.h - use const references to avoid FrequencyData copies. NFCI.
Simon Pilgrim [Fri, 2 Oct 2020 12:53:21 +0000 (13:53 +0100)]
LoopAccessAnalysis.cpp - use const reference in for-range loops. NFCI.
Florian Hahn [Fri, 2 Oct 2020 12:31:23 +0000 (13:31 +0100)]
[SLP] Add test where reduction result is used in PHI.
Test case for PR47670.
Simon Pilgrim [Fri, 2 Oct 2020 12:19:02 +0000 (13:19 +0100)]
[InstCombine] Add partial bswap vector test from D88578
Sjoerd Meijer [Thu, 1 Oct 2020 14:47:31 +0000 (15:47 +0100)]
[AArch64] Add CPU Cortex-R82
This adds support for -mcpu=cortex-r82. Some more information about this
core can be found here:
https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r82
One note about the system register: that is a bit of a refactoring because of
small differences between v8.4-A AArch64 and v8-R AArch64.
This is based on patches from Mark Murray and Mikhail Maltsev.
Differential Revision: https://reviews.llvm.org/D88660
Sam McCall [Fri, 2 Oct 2020 10:18:31 +0000 (12:18 +0200)]
[clangd] Make PopulateSwitch a fix.
It fixes the -Wswitch warning, though we mark it as a fix even if that is off.
This makes it the "recommended" action on an incomplete switch, which seems OK.
Differential Revision: https://reviews.llvm.org/D88726
Florian Hahn [Tue, 29 Sep 2020 08:46:57 +0000 (09:46 +0100)]
[PhaseOrdering] Add test that requires peeling before vectorization.
Test case for PR47671.
Serguei Katkov [Fri, 2 Oct 2020 10:46:29 +0000 (17:46 +0700)]
[GVN LoadPRE] Add test to show an opportunty.
We can use context to prove that load can be safely executed
at a point where load is being hoisted.
George Mitenkov [Fri, 2 Oct 2020 10:17:26 +0000 (13:17 +0300)]
[MLIR][LLVM] Fixed `topologicalSort()` to iterative version
Instead of recursive helper method `topologicalSortImpl()`,
sort's implementation is moved to `topologicalSort()` function's
body directly. `llvm::ReversePostOrderTraversal` is used to create
a traversal of blocks in reverse post order.
Reviewed By: kiranchandramohan, rriddle
Differential Revision: https://reviews.llvm.org/D88544
Nicolas Vasilache [Fri, 2 Oct 2020 10:30:56 +0000 (06:30 -0400)]
[mlir] Add subtensor_insert operation
Differential revision: https://reviews.llvm.org/D88657
Kadir Cetinkaya [Fri, 2 Oct 2020 08:12:55 +0000 (10:12 +0200)]
[clangd][lit] Update document-link.test to respect custom resource-dir locations
Differential Revision: https://reviews.llvm.org/D88721
Simon Pilgrim [Fri, 2 Oct 2020 10:06:39 +0000 (11:06 +0100)]
[InstCombine] Add some basic vector bswap tests
We get the vNi16 cases already via matching as a rotate followed by the fshl -> bswap combines
Nicolas Vasilache [Fri, 2 Oct 2020 09:40:52 +0000 (05:40 -0400)]
[mlir] Add canonicalization for the `subtensor` op
Differential revision: https://reviews.llvm.org/D88656
Nicolas Vasilache [Fri, 2 Oct 2020 09:32:35 +0000 (05:32 -0400)]
[mlir] Add a subtensor operation
This revision introduces a `subtensor` op, which is the counterpart of `subview` for a tensor operand. This also refactors the relevant pieces to allow reusing the `subview` implementation where appropriate.
This operation will be used to implement tiling for Linalg on tensors.
Simon Pilgrim [Fri, 2 Oct 2020 09:34:01 +0000 (10:34 +0100)]
[InstCombine] Add partial bswap test from D88578
Meera Nakrani [Fri, 2 Oct 2020 09:28:35 +0000 (09:28 +0000)]
[ARM] Prevent constants from iCmp instruction from being hoisted if part of a min(max()) pattern
Marks constants of an ICmp instruction as free if it's only user is a select
instruction that is part of a min(max()) pattern. Ensures that in loops, in
particular when loop unrolling is turned on, SSAT will still be correctly generated.
Differential Revision: https://reviews.llvm.org/D88662
Hsiangkai Wang [Tue, 28 Jul 2020 06:45:28 +0000 (14:45 +0800)]
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
Implement vmsge{u}.vx pseudo instruction.
According to RISC-V V specification, there are different scenarios for this
pseudo instruction. I list them below.
unmasked va >= x
pseudoinstruction: vmsge{u}.vx vd, va, x
expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
masked va >= x, vd != v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
masked va >= x, vd == v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
expansion: vmslt{u}.vx vt, va, x; vmandnot.mm vd, vd, vt
Use pseudo instruction to model vmsge{u}.vx. The pseudo instruction will convert
to different expansion according to the condition.
Differential Revision: https://reviews.llvm.org/D84732
Sam McCall [Mon, 28 Sep 2020 16:12:37 +0000 (18:12 +0200)]
[clangd] Remove Tweak::Intent, use CodeAction kind directly. NFC
Intent was a nice idea but it ends up being a bit awkward/heavyweight
without adding much.
In particular, it makes it hard to implement `CodeActionParams.only` properly
(there's an inheritance hierarchy for kinds).
Differential Revision: https://reviews.llvm.org/D88427
serge-sans-paille [Wed, 30 Sep 2020 09:35:00 +0000 (11:35 +0200)]
Fix limit behavior of dynamic alloca
When the allocation size is 0, we shouldn't probe. Within [1, PAGE_SIZE], we
should probe once etc.
This fixes https://bugs.llvm.org/show_bug.cgi?id=47657
Differential Revision: https://reviews.llvm.org/D88548
Georgii Rymar [Thu, 1 Oct 2020 13:16:50 +0000 (16:16 +0300)]
[yaml2obj][elf2yaml] - Add a support for the `EntSize` field for `SHT_HASH` sections.
Specification for SHT_HASH table says (https://refspecs.linuxbase.org/elf/gabi4+/ch5.dynamic.html#hash)
that it contains Elf32_Word entries for both 32/64 bit objects.
Currently both GNU linkers and LLD sets the `sh_entsize` field to `4`.
At the same time, `yaml2obj` ignores the `EntSize` field for SHT_HASH sections.
This patch fixes this and also adds a support for obj2yaml: it will not
dump this field when the `sh_entsize` contains the default value (`4`).
Differential revision: https://reviews.llvm.org/D88652
Tres Popp [Fri, 2 Oct 2020 08:22:53 +0000 (10:22 +0200)]
Handle unused variable without asserts
Sam McCall [Fri, 2 Oct 2020 07:53:06 +0000 (09:53 +0200)]
[clangd] Drop dependence on standard library in check.test
Thomas Lively [Fri, 2 Oct 2020 07:28:06 +0000 (00:28 -0700)]
[WebAssembly] Emulate v128.const efficiently
v128.const was recently implemented in V8, but until it rolls into Chrome
stable, we can't enable it in the WebAssembly backend without breaking origin
trial users. So far we have been lowering build_vectors that would otherwise
have been lowered to v128.const to splats followed by sequences of replace_lane
instructions to initialize each lane individually. That produces large and
inefficient code, so this patch introduces new logic to lower integer vector
constants to a single i64x2.splat where possible, with at most a single
i64x2.replace_lane following it if necessary.
Adapted from a patch authored by @omnisip.
Differential Revision: https://reviews.llvm.org/D88591
David Sherwood [Wed, 30 Sep 2020 14:10:03 +0000 (15:10 +0100)]
[SVE][CodeGen] Fix implicit TypeSize->uint64_t casts in TypePromotion
The TypePromotion pass only operates on scalar types so I've fixed up
all places where we were relying upon the implicit cast from
TypeSize->uint64_t.
Differential Revision: https://reviews.llvm.org/D88575
David Sherwood [Thu, 1 Oct 2020 11:48:07 +0000 (12:48 +0100)]
[SVE][CodeGen] Add new EVT/MVT getFixedSizeInBits() functions
When we know that a particular type is always going to be fixed
width we have so far been writing code like this:
getSizeInBits().getFixedSize()
Since we are doing this in quite a few places now it seems to make
sense to add a new helper function that allows us to replace
these calls with a single getFixedSizeInBits() call.
Differential Revision: https://reviews.llvm.org/D88649
Martin Storsjö [Thu, 1 Oct 2020 07:21:24 +0000 (10:21 +0300)]
[AArch64] Omit SEH directives for the epilogue if none are needed
For these cases, we already omit the prologue directives, if
(!AFI->hasStackFrame() && !windowsRequiresStackProbe && !NumBytes).
When writing the epilogue (after the prolog has been written), if
the function doesn't have the WinCFI flag set (i.e. if no prologue
was generated), assume that no epilogue will be needed either,
and don't emit any epilog start pseudo instruction. After completing
the epilogue, make sure that it actually matched the prologue.
Previously, when epilogue start/end was generated, but no prologue,
the unwind info for such functions actually was huge; 12 bytes xdata
(4 bytes header, 4 bytes for one non-folded epilogue header, 4 bytes
for padded opcodes) and 8 bytes pdata. Because the epilog consisted of
one opcode (end) but the prolog was empty (no .seh_endprologue), the
epilogue couldn't be folded into the prologue, and thus couldn't be
considered for packed form either.
On a 6.5 MB DLL with 110 KB pdata and 166 KB xdata, this gets rid of
38 KB pdata and 62 KB xdata.
Differential Revision: https://reviews.llvm.org/D88641
Stephen Neuendorffer [Wed, 30 Sep 2020 00:14:42 +0000 (17:14 -0700)]
[MLIR] Updates around MemRef Normalization
The documentation for the NormalizeMemRefs pass and the associated MemRefsNormalizable
traits was confusing and not on the website. This update clarifies the language
around the difference between a MemRef Type, an operation that accesses the value of
MemRef Type, and better documents the limitations of the current implementation.
This patch also includes some basic debugging information for the pass so people
might have a chance of figuring out why it doesn't work on their code.
Differential Revision: https://reviews.llvm.org/D88532
Max Kazantsev [Fri, 2 Oct 2020 03:20:06 +0000 (10:20 +0700)]
[SCEV] Limited support for unsigned preds in isImpliedViaOperations
The logic there only considers `SLT/SGT` predicates. We can use the same logic
for proving `ULT/UGT` predicates if all involved values are non-negative.
Adding full-scale support for unsigned might be challenging because of code amount,
so we can consider this in the future.
Differential Revision: https://reviews.llvm.org/D88087
Reviewed By: reames
Philip Reames [Fri, 2 Oct 2020 02:17:21 +0000 (19:17 -0700)]
[gvn] Handle a corner case w/vectors of non-integral pointers
If we try to coerce a vector of non-integral pointers to a narrower type (either narrower vector or single pointer), we use inttoptr and violate the semantics of non-integral pointers. In theory, we can handle many of these cases, we just need to use a different code idiom to convert without going through inttoptr and back.
This shows up as wrong code bugs, and in some cases, crashes due to failed asserts. Modeled after a change which has lived downstream for a couple years, though completely rewritten to be more idiomatic.
Carl Ritson [Fri, 2 Oct 2020 01:52:06 +0000 (10:52 +0900)]
[AMDGPU] SIInsertSkips: Tidy block splitting to use splitAt
Convert to use new MachineBasicBlock splitAt function.
Place code in splitBlock function for reuse in future changes.
Should yield no functional change.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D88537
Jason Molenda [Fri, 2 Oct 2020 01:50:29 +0000 (18:50 -0700)]
Have kernel binary scanner load dSYMs as binary+dSYM if best thing found
lldb's PlatforDarwinKernel scans the local filesystem (well known
locations, plus user-specified directories) for kernels and kexts
when doing kernel debugging, and loads them automatically. Sometimes
kernel developers want to debug with *only* a dSYM, in which case they
give lldb the DWARF binary + the dSYM as a binary and symbol file.
This patch adds code to lldb to do this automatically if that's the
best thing lldb can find.
A few other bits of cleanup in PlatformDarwinKernel that I undertook
at the same time:
1. Remove the 'platform.plugin.darwin-kernel.search-locally-for-kexts'
setting. When I added the local filesystem index at start of kernel
debugging, I thought people might object to the cost of the search
and want a way to disable it. No one has.
2. Change the behavior of
'plugin.dynamic-loader.darwin-kernel.load-kexts' setting so it does
not disable the local filesystem scan, or use of the local filesystem
binaries.
3. PlatformDarwinKernel::GetSharedModule into GetSharedModuleKext and
GetSharedModuleKernel for easier readability & maintenance.
4. Added accounting of .dSYM.yaa files (an archive format akin to tar)
that I come across during the scan. I'm not using these for now; it
would be very expensive to expand the archives & see if the UUID matches
what I'm searching for.
<rdar://problem/
69774993>
Differential Revision: https://reviews.llvm.org/D88632
Carl Ritson [Fri, 2 Oct 2020 00:58:36 +0000 (09:58 +0900)]
CodeGen: Fix livein calculation in MachineBasicBlock splitAt
Fix and simplify computation of liveins for new block.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D88535
Esme-Yi [Fri, 2 Oct 2020 01:26:18 +0000 (01:26 +0000)]
[PowerPC] Put the CR field in low bits of GRC during copying CRRC to GRC.
Summary: How we copying the CRRC to GRC is using a single MFOCRF to copy the contents of CR field n (CR bits 4×n+32:4×n+35) into bits 4×n+32:4×n+35 of register GRC. That’s not correct because we expect the value of destination register equals to source so we have to put the the contents of CR field in the lowest 4 bits. This patch adds a RLWINM after MFOCRF to achieve that.
The problem came up when adding builtins for xvtdivdp, xvtdivsp, xvtsqrtdp, xvtsqrtsp, as posted in D88278. We need to move the outputs (in CR register) to GRC. However outputs of these instructions may not in a fixed CR# register, so we can’t directly add a rotation instruction in the .td patterns, but need to wait until the CR register is determined. Then we confirmed this should be a bug in POST-RA PSEUDO PASS.
Reviewed By: nemanjai, shchenz
Differential Revision: https://reviews.llvm.org/D88274
Joseph Huber [Wed, 30 Sep 2020 22:22:53 +0000 (18:22 -0400)]
[OpenMP] Add Missing Runtime Call for Globalization Remarks
Summary:
Add a missing runtime call to perform data globalization checks.
Reviewers: jdoerfert
Subscribers: guansong hiraditya llvm-commits sstefan1 yaxunl
Tags: #LLVM #OpenMP
Differential Revision: https://reviews.llvm.org/D88621
Valentin Clement [Fri, 2 Oct 2020 00:38:48 +0000 (20:38 -0400)]
[flang][openacc] Update loop construct lowering
Update the loop construct lowering to support multiple occurences of the same clauses
such as private. Add some utility functions used by other constructs.
Upstreaming part of https://github.com/flang-compiler/f18-llvm-project/pull/438/
Reviewed By: schweitz
Differential Revision: https://reviews.llvm.org/D88253
peter klausler [Thu, 1 Oct 2020 19:12:46 +0000 (12:12 -0700)]
[flang] Extend runtime API for PAUSE to allow a stop code
Support integer and default character stop codes on PAUSE
statements. Add length argument to STOP statement with a
character stop code.
Differential revision: https://reviews.llvm.org/D88692
peter klausler [Thu, 1 Oct 2020 17:59:09 +0000 (10:59 -0700)]
[flang] Fix actions at end of output record
It turns out that unformatted fixed-size output records
do need to be padded out if short, in order to avoid a
spurious EOF crash on a short record at the end of the file.
While here in AdvanceRecord(), move the unformatted
variable-length record header/footer writing code to here
from EndIoStatement().
Differential revision: https://reviews.llvm.org/D88685
jasonliu [Thu, 1 Oct 2020 23:35:31 +0000 (23:35 +0000)]
[XCOFF] Enable -fdata-sections on AIX
Summary:
Some design decision worth noting about:
I've noticed a recent mailing discussing about why string literal is
not affected by -fdata-sections for ELF target:
http://lists.llvm.org/pipermail/llvm-dev/2020-September/145121.html
But on AIX, our linker could not split the mergeable string like other target.
So I think it would make more sense for us to emit separate csect for
every mergeable string in -fdata-sections mode,
as there might not be other ways for linker to do garbage collection
on unused mergeable string.
Reviewed By: daltenty, hubert.reinterpretcast
Differential Revision: https://reviews.llvm.org/D88339
peter klausler [Wed, 30 Sep 2020 20:10:17 +0000 (13:10 -0700)]
[flang] Fix buffering read->write transition
The buffer needs to be Reset() after a Flush(), since the
Flush() can be a no-op after a read->write transition.
And record numbers are 1-based, not 0-based.
This fixes a bug with rewrites of records that have been
recently read.
Differential revision: https://reviews.llvm.org/D88612
peter klausler [Thu, 1 Oct 2020 19:26:10 +0000 (12:26 -0700)]
[flang][msvc] Rework a MSVC work-around to avoid clang warning
A recent MSVC work-around patch is eliciting unused variable
warnings from clang; package the lambda reference arguments
into a struct to avoid the warning.
Differential revision: https://reviews.llvm.org/D88695
Philip Reames [Thu, 1 Oct 2020 23:44:12 +0000 (16:44 -0700)]
[memcpyopt] Conservatively handle non-integral pointers
If we allow the non-integral pointers to become memset and memcpy, we loose the ability to reason about pointer propagation. This patch is modeled on changes we've carried downstream for a long time, figured it was worth being equally conservative for other users. There is room to refine the semantics and handling here if anyone is motivated.
Muhammad Asif Manzoor [Thu, 1 Oct 2020 23:39:48 +0000 (19:39 -0400)]
[AArch64][SVE] Add lowering for llvm fabs
Add the functionality to lower fabs for passthru variant
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D88679
Philip Reames [Thu, 1 Oct 2020 23:08:44 +0000 (16:08 -0700)]
Fix a bug in memset formation with vectors of non-integral pointers
We were converting the non-integral store into a integer store which is not legal.
Stanislav Mekhanoshin [Thu, 1 Oct 2020 22:44:12 +0000 (15:44 -0700)]
[AMDGPU] Allow SOP asm mnemonic to differ
Allows the creation of real SOP1 instructions with
assembler mnemonics that differ from their
pseudo-instruction mnemonics. The default behavior
keeps the mnemonics matching.
Corrects a subtarget label typo in a comment.
Authored By: Joe_Nash
Differential Revision: https://reviews.llvm.org/D88708
peter klausler [Wed, 30 Sep 2020 19:26:25 +0000 (12:26 -0700)]
[flang] Readability improvement in binary->decimal conversion
Tweak binary->decimal conversions to avoid an integer multiplication
in a hot loop to improve readability and get a minor (~5%) speed-up.
Use native integer division by constants for more readability, too,
since current build compilers seem to optimize it correctly now.
Delete the now needless temporary work-around facility in
Common/unsigned-const-division.h.
Differential revision: https://reviews.llvm.org/D88604
Jessica Paquette [Wed, 30 Sep 2020 21:01:12 +0000 (14:01 -0700)]
[GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs
Similar to the FP case in `AArch64TargetLowering::LowerBR_CC`.
Instead of emitting the csets + a tbnz, just emit a compare + bcc
(or two bccs, depending on the condition code)
This improves cases like this: https://godbolt.org/z/v8hebx
This is a 0.1% geomean code size improvement for CTMark at -O3.
Differential Revision: https://reviews.llvm.org/D88624
Jessica Paquette [Thu, 1 Oct 2020 20:46:15 +0000 (13:46 -0700)]
[AArch64][GlobalISel] Use emitTestBit in selection for G_BRCOND
Partially refactoring, partially fixing a bug.
- We shouldn't use TB(N)ZX unless the bit number is >= 32
- We can fold more than xor using emitTestBit
Also remove a check which isn't relevant anymore + update tests.
Rename select-brcond-of-not.mir to select-brcond-of-binop.mir, since it now
tests more than just G_XOR.
Differential Revision: https://reviews.llvm.org/D88702
Amara Emerson [Thu, 1 Oct 2020 21:47:58 +0000 (14:47 -0700)]
[AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP.
No need to be different here for the vast majority of rules.
Amara Emerson [Thu, 1 Oct 2020 21:28:23 +0000 (14:28 -0700)]
[AArch64][GlobalISel] Make <8 x s8> integer arithmetic ops legal.
Amara Emerson [Thu, 1 Oct 2020 21:18:38 +0000 (14:18 -0700)]
[AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support.
Amara Emerson [Thu, 1 Oct 2020 21:15:57 +0000 (14:15 -0700)]
Revert "[AArch64][GlobalISel] Make <8 x s8> shifts legal."
Accidentally pushed this.
Amara Emerson [Thu, 1 Oct 2020 21:04:54 +0000 (14:04 -0700)]
[AArch64][GlobalISel] Make <8 x s8> shifts legal.
Alexandre Ganea [Thu, 1 Oct 2020 20:11:00 +0000 (16:11 -0400)]
[LLD][COFF] Fix crash with /summary and PCH input files
Before this patch /summary was crashing with some .PCH.OBJ files, because tpiMap[srcIdx++] was reading at the wrong location. When the TpiSource depends on a .PCH.OBJ file, the types should be offset by the previously merged PCH.OBJ set of indices.
Differential Revision: https://reviews.llvm.org/D88678
Raphael Isemann [Thu, 1 Oct 2020 21:02:15 +0000 (23:02 +0200)]
[lldb] Skip unique_ptr import-std-module tests on Linux
This seems to fail on ubuntu 18.04.5 with Clang 9 due to:
Error output:
error: Couldn't lookup symbols:
std::__1::default_delete<int>::operator()(int) const
Amara Emerson [Thu, 1 Oct 2020 20:50:20 +0000 (13:50 -0700)]
[AArch64][GlobalISel] Merge G_SHL, G_ASHR and G_LSHR legalizer rules together.
There's no need for any difference between these.
Arthur Eubanks [Tue, 29 Sep 2020 23:06:32 +0000 (16:06 -0700)]
[gn build] Support building with ThinLTO
Differential Revision: https://reviews.llvm.org/D88584
Aaron Puchert [Thu, 1 Oct 2020 20:31:30 +0000 (22:31 +0200)]
libclc: Use find_package to find Python 3 and require it
The script's shebang wants Python 3, so we use FindPython3. The
original code didn't work when an unversioned python was not available.
This is explicitly allowed in PEP 394. ("Distributors may choose to set
the behavior of the python command as follows: python2, python3, not
provide python command, allow python to be configurable by an end user
or a system administrator.")
Also I think it's actually required, so let the configuration fail if we
can't find it.
Lastly remove the shebang, since the script is only run via interpreter
and doesn't have the executable bit set anyway.
Reviewed By: jvesely
Differential Revision: https://reviews.llvm.org/D88366
Amara Emerson [Wed, 23 Sep 2020 22:52:49 +0000 (15:52 -0700)]
[AArch64][GlobalISel] Use custom legalization for G_TRUNC for v8i8 vectors.
Truncating to v8i8 is a case where we want to split the source but also generate
intermediate truncates to reduce the size of the source vector before truncating
down to v8i8. This implements the same strategy as what SelectionDAG does, but
I'm not certain where if anywhere in generic code it should live.
Use it for legalization of v8s8 = G_ICMP v8s32.
Differential Revision: https://reviews.llvm.org/D88191
Amara Emerson [Thu, 1 Oct 2020 17:45:14 +0000 (10:45 -0700)]
[AArch64][GlobalISel] Camp oversize v4s64 G_FPEXT operations.
Hubert Tong [Thu, 1 Oct 2020 19:46:26 +0000 (15:46 -0400)]
[clang][Sema] Fix PR47676: Handle dependent AltiVec C-style cast
Fix premature decision in the presence of type-dependent expression
operands on whether AltiVec vector initializations from single
expressions are "splat" operations.
Verify that the instantiation is able to determine the correct cast
semantics for both the scalar type and the vector type case.
Note that, because the change only affects the single-expression
case (and the target type is an AltiVec-style vector type), the
replacement of a parenthesized list with a parenthesized expression
does not change the semantics of the program in a program-observable
manner.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D88526
Fangrui Song [Thu, 1 Oct 2020 19:36:08 +0000 (12:36 -0700)]
Raland D87318 [LLD][PowerPC] Add support for R_PPC64_GOT_TLSGD_PCREL34 used in TLS General Dynamic
Add Thread Local Storage support for the 34 bit relocation R_PPC64_GOT_TLSGD_PCREL34 used in General Dynamic.
The compiler will produce code that looks like:
```
pla r3, x@got@tlsgd@pcrel R_PPC64_GOT_TLSGD_PCREL34
bl __tls_get_addr@notoc(x@tlsgd) R_PPC64_TLSGD
R_PPC64_REL24_NOTOC
```
LLD should be able to correctly compute the relocation for R_PPC64_GOT_TLSGD_PCREL34 as well as do the following two relaxations where possible:
General Dynamic to Local Exec:
```
paddi r3, r13, x@tprel
nop
```
and General Dynamic to Initial Exec:
```
pld r3, x@got@tprel@pcrel
add r3, r3, r13
```
Note:
This patch adds support for the PC Relative (no TOC) version of General Dynamic on top of the existing support for the TOC version of General Dynamic.
The ABI does not provide any way to tell by looking only at the relocation `R_PPC64_TLSGD` when it is being used in a TOC instruction sequence or and when it is being used in a no TOC sequence. The TOC sequence should always be 4 byte aligned. This patch adds one to the offset of the relocation when it is being used in a no TOC sequence. In this way LLD can tell by looking at the alignment of the offset of `R_PPC64_TLSGD` whether or not it is being used as part of a TOC or no TOC sequence.
Reviewed By: NeHuang, sfertile, MaskRay
Differential Revision: https://reviews.llvm.org/D87318
Petr Hosek [Thu, 1 Oct 2020 19:21:01 +0000 (12:21 -0700)]
[CMake][Fuchsia] Don't set WIN32 API, rely on autodetection
We prefer autodetection here to avoid persisting this configuration
in the generated __config header which is shared across targets.
Differential Revision: https://reviews.llvm.org/D88694
Reid Kleckner [Thu, 1 Oct 2020 19:00:18 +0000 (12:00 -0700)]
[lit] Fix Python 2/3 compat in new winreg search code
This should fix the test failures on the clang win64 bot:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/18830
It has been red since Sept 23-ish.
This was subtle to debug. Windows has 'find' and 'sort' utilities in
C:\Windows\system32, but they don't support all the same flags as the
coreutils programs. I configured the buildbot above with Python 2.7
64-bit (hey, it was set up in 2016). When I installed git for Windows, I
opted to add all the Unix utilities that come with git to the system
PATH. This is *almost* enough to make the LLVM tests pass, but not
quite, because if you use the system PATH, the Windows version of find
and sort come first, but the tests that use diff, cmp, etc, will all
pass. So only a handful of tests will fail, and with cryptic error
messages.
The code changed in this CL doesn't work with Python 2. Before
Python 3.2, the winreg.OpenKey function did not accept the `access=`
keyword argument, the caller was required to pass an unused `reserved`
positional argument of 0. The try/except/pass around the OpenKey
operation masked this usage error in Python 2.
Further, the result of the registry operation has to be converted from
unicode to add it to the environment, but that was incidental.
Reid Kleckner [Wed, 30 Sep 2020 21:40:53 +0000 (14:40 -0700)]
[PDB] Use one func id DenseMap instead of per-source maps, NFC
This avoids some DenseMap copies when /Zi is in use, and results in
fewer data structures.
Differential Revision: https://reviews.llvm.org/D88617
Nikita Popov [Thu, 1 Oct 2020 18:57:09 +0000 (20:57 +0200)]
[InstCombine] Fix select operand simplification with undef (PR47696)
When replacing X == Y ? f(X) : Z with X == Y ? f(Y) : Z, make sure
that Y cannot be undef. If it may be undef, we might end up picking
a different value for undef in the comparison and the select
operand.
Petr Hosek [Mon, 28 Sep 2020 23:12:48 +0000 (16:12 -0700)]
[CMake] Use -isystem flag to access libc++ headers
This is a partial revert of D62155. Rather than copying libc++ headers
into the build directory to be later overwritten by the final headers,
use -isystem flag to access libc++ headers during CMake checks. This
should address the occasional flake we've seen, especially on Windows
builders where CMake fails to overwrite __config with the final version.
Differential Revision: https://reviews.llvm.org/D88454
Sanjay Patel [Thu, 1 Oct 2020 18:23:18 +0000 (14:23 -0400)]
[APFloat] convert SNaN to QNaN in convert() and raise Invalid signal
This is an alternate fix (see D87835) for a bug where a NaN constant
gets wrongly transformed into Infinity via truncation.
In this patch, we uniformly convert any SNaN to QNaN while raising
'invalid op'.
But we don't have a way to directly specify a 32-bit SNaN value in LLVM IR,
so those are always encoded/decoded by calling convert from/to 64-bit hex.
See D88664 for a clang fix needed to allow this change.
Differential Revision: https://reviews.llvm.org/D88238
Arthur Eubanks [Thu, 1 Oct 2020 18:27:32 +0000 (11:27 -0700)]
Revert "[CFGuard] Add address-taken IAT tables and delay-load support"
This reverts commit
ef4e971e5e18ae796466623df8f26265ba6bdfb5.
Stefan Pintilie [Thu, 1 Oct 2020 18:28:35 +0000 (13:28 -0500)]
Revert "[LLD][PowerPC] Add support for R_PPC64_GOT_TLSGD_PCREL34 used in TLS General Dynamic"
This reverts commit
79122868f9a3909cfd94d51e9bfe960917a1be05.
Stefan Pintilie [Thu, 1 Oct 2020 10:59:19 +0000 (05:59 -0500)]
[LLD][PowerPC] Add support for R_PPC64_GOT_TLSGD_PCREL34 used in TLS General Dynamic
Add Thread Local Storage support for the 34 bit relocation R_PPC64_GOT_TLSGD_PCREL34 used in General Dynamic.
The compiler will produce code that looks like:
```
pla r3, x@got@tlsgd@pcrel R_PPC64_GOT_TLSGD_PCREL34
bl __tls_get_addr@notoc(x@tlsgd) R_PPC64_TLSGD
R_PPC64_REL24_NOTOC
```
LLD should be able to correctly compute the relocation for R_PPC64_GOT_TLSGD_PCREL34 as well as do the following two relaxations where possible:
General Dynamic to Local Exec:
```
paddi r3, r13, x@tprel
nop
```
and General Dynamic to Initial Exec:
```
pld r3, x@got@tprel@pcrel
add r3, r3, r13
```
Note:
This patch adds support for the PC Relative (no TOC) version of General Dynamic on top of the existing support for the TOC version of General Dynamic.
The ABI does not provide any way to tell by looking only at the relocation `R_PPC64_TLSGD` when it is being used in a TOC instruction sequence or and when it is being used in a no TOC sequence. The TOC sequence should always be 4 byte aligned. This patch adds one to the offset of the relocation when it is being used in a no TOC sequence. In this way LLD can tell by looking at the alignment of the offset of `R_PPC64_TLSGD` whether or not it is being used as part of a TOC or no TOC sequence.
Reviewed By: NeHuang, sfertile, MaskRay
Differential Revision: https://reviews.llvm.org/D87318