Craig Topper [Fri, 23 Mar 2018 19:15:03 +0000 (19:15 +0000)]
[X86] Add itineraries to ADD.*_DB instructions to match their normal counterparts.
llvm-svn: 328352
Tony Tye [Fri, 23 Mar 2018 18:58:47 +0000 (18:58 +0000)]
[AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU
Add two additional implicit arguments for OpenCL for the AMDGPU target using the AMDHSA runtime to support device enqueue.
Differential Revision: https://reviews.llvm.org/D44697
llvm-svn: 328351
Tony Tye [Fri, 23 Mar 2018 18:51:45 +0000 (18:51 +0000)]
[AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU (CLANG)
Add two additional implicit arguments for OpenCL for the AMDGPU target using the AMDHSA runtime to support device enqueue.
Differential Revision: https://reviews.llvm.org/D44696
llvm-svn: 328350
Tony Tye [Fri, 23 Mar 2018 18:45:18 +0000 (18:45 +0000)]
[AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU
- Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target.
- Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS.
Differential Revision: https://reviews.llvm.org/D43736
llvm-svn: 328349
Zachary Turner [Fri, 23 Mar 2018 18:43:39 +0000 (18:43 +0000)]
[PDB] Make our PDBs look more like MS PDBs.
When investigating bugs in PDB generation, the first step is
often to do the same link with link.exe and then compare PDBs.
But comparing PDBs is hard because two completely different byte
sequences can both be correct, so it hampers the investigation when
you also have to spend time figuring out not just which bytes are
different, but also if the difference is meaningful.
This patch fixes a couple of cases related to string table emission,
hash table emission, and the order in which we emit strings that
makes more of our bytes the same as the bytes generated by MS PDBs.
Differential Revision: https://reviews.llvm.org/D44810
llvm-svn: 328348
Tony Tye [Fri, 23 Mar 2018 18:43:15 +0000 (18:43 +0000)]
[AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU (CLANG)
- Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target.
- Use a function attribute to communicate to the AMDGPU backend.
Differential Revision: https://reviews.llvm.org/D43735
llvm-svn: 328347
Krzysztof Parzyszek [Fri, 23 Mar 2018 18:43:09 +0000 (18:43 +0000)]
[Hexagon] Always generate mux out of predicated transfers if possible
HexagonGenMux would collapse pairs of predicated transfers if it assumed
that the predicated .new forms cannot be created. Turns out that generating
mux is preferable in almost all cases.
Introduce an option -hexagon-gen-mux-threshold that controls the minimum
distance between the instruction defining the predicate and the later of
the two transfers. If the distance is closer than the threshold, mux will
not be generated. Set the threshold to 0 by default.
llvm-svn: 328346
Jordan Rose [Fri, 23 Mar 2018 18:05:19 +0000 (18:05 +0000)]
Delete the copy constructor for llvm::yaml::Node
The nodes keep a reference back to the original document, but the
document is streamed, not read all into memory at once, and the
position is part of the state. If nodes are ever copied, the document
position can end up being advanced more than once.
This did not reveal any problems in LLVM or Clang but caught a handful
over in Swift!
llvm-svn: 328345
Krzysztof Parzyszek [Fri, 23 Mar 2018 18:00:18 +0000 (18:00 +0000)]
[Hexagon] Avoid early if-conversion for one sided branches
Patch by Anand Kodnani.
llvm-svn: 328344
Simon Pilgrim [Fri, 23 Mar 2018 17:59:22 +0000 (17:59 +0000)]
[X86][Btver2] Cleanup TEST instructions to use JFPA (+JFPX on ymms) function unit
llvm-svn: 328343
Alex Shlyapnikov [Fri, 23 Mar 2018 17:57:54 +0000 (17:57 +0000)]
[HWASan] Port HWASan to Linux x86-64 (LLVM)
Summary:
Porting HWASan to Linux x86-64, first of the three patches, LLVM part.
The approach is similar to ARM case, trap signal is used to communicate
memory tag check failure. int3 instruction is used to generate a signal,
access parameters are stored in nop [eax + offset] instruction immediately
following the int3 one.
One notable difference is that x86-64 has to untag the pointer before use
due to the lack of feature comparable to ARM's TBI (Top Byte Ignore).
Reviewers: eugenis
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D44699
llvm-svn: 328342
Ana Pazos [Fri, 23 Mar 2018 17:53:27 +0000 (17:53 +0000)]
[ARM] Fix "Constant pool entry out of range!" in Thumb1 mode
This patch fixes PR36658, "Constant pool entry out of range!" in Thumb1 mode.
In ARMConstantIslands::optimizeThumb2JumpTables() in Thumb1 mode,
adjustBBOffsetsAfter() is not calculating postOffset correctly by
properly accounting for the padding that is required for the constant pool
that immediately follows the jump table branch instruction.
Reviewers: t.p.northover, eli.friedman
Reviewed By: t.p.northover
Subscribers: chrib, tstellar, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D44709
llvm-svn: 328341
Andrea Di Biagio [Fri, 23 Mar 2018 17:53:02 +0000 (17:53 +0000)]
[llvm-mca] update the ResourcePressureView after r328335. NFC.
This should have been part of r328335. I forgot to svn add these files.
llvm-svn: 328340
Krzysztof Parzyszek [Fri, 23 Mar 2018 17:46:09 +0000 (17:46 +0000)]
[Hexagon] Two fixes in early if-conversion
- Fix checking for vector predicate registers.
- Avoid speculating llvm.lifetime.end intrinsic.
Patch by Harsha Jagasia and Brendon Cahoon.
llvm-svn: 328339
Simon Pilgrim [Fri, 23 Mar 2018 17:38:59 +0000 (17:38 +0000)]
[X86][Btver2] Cleanup MOVMSK instructions to use JFPA function unit
Add missing non-VEX and (V)PMOVMSKB instructions to the pattern
llvm-svn: 328338
Ben Langmuir [Fri, 23 Mar 2018 17:37:27 +0000 (17:37 +0000)]
[vfs] Don't bail out after a missing -ivfsoverlay file
This make -ivfsoverlay behave more like other fatal errors (e.g. missing
-include file) by skipping the missing file instead of bailing out of
the whole compilation. This makes it possible for libclang to still
provide some functionallity as well as to correctly produce the fatal
error diagnostic (previously we lost the diagnostic in libclang since
there was no TU to tie it to).
rdar://
33385423
llvm-svn: 328337
Andrew Kaylor [Fri, 23 Mar 2018 17:36:18 +0000 (17:36 +0000)]
Fix a block copying problem in LICM
Differential Revision: https://reviews.llvm.org/D44817
llvm-svn: 328336
Andrea Di Biagio [Fri, 23 Mar 2018 17:36:07 +0000 (17:36 +0000)]
[llvm-mca] Make the resource cost a double.
This is done in preparation for the fix for PR36874.
The number of cycles consumed for each pipe is now a double quantity. This
allows reuse of the resource pressure view to print out instruction tables.
llvm-svn: 328335
Fangrui Song [Fri, 23 Mar 2018 17:26:12 +0000 (17:26 +0000)]
[ADT] Simplify getMemory. NFC
llvm-svn: 328334
Krzysztof Parzyszek [Fri, 23 Mar 2018 17:22:55 +0000 (17:22 +0000)]
[Hexagon] Copy subregisters in HexagonStoreWiden
When converting an instruction to the wider version, copy any
subregisters if the original operand has a subregister.
Patch by Brendon Cahoon.
llvm-svn: 328333
Rafael Espindola [Fri, 23 Mar 2018 17:19:18 +0000 (17:19 +0000)]
Add a minimal fix for PR36878.
When looking for the output section and the output offset the
expectation was that the caller had looked at Repl. That works fine
for InputSections, but in the case of MergeInputSections the caller
doesn't have the section that is actually replaced.
The original testcase was failing because getOutputSection was
returning null. The slightly extended testcase also checks that
getOffset also checks Repl.
I will send a refactoring separetelly.
llvm-svn: 328332
Simon Pilgrim [Fri, 23 Mar 2018 16:17:56 +0000 (16:17 +0000)]
[X86][Btver2] Vector permutes use a JFPU01 scheduler pipe and JFPX/JVALU function unit
llvm-svn: 328331
Sanjay Patel [Fri, 23 Mar 2018 15:39:03 +0000 (15:39 +0000)]
[InstCombine] auto-generate checks; NFC
llvm-svn: 328329
Simon Pilgrim [Fri, 23 Mar 2018 15:35:13 +0000 (15:35 +0000)]
[X86][Btver2] Vector store instructions use a JFPU1 scheduler pipe and JSAGU/JSTC function units
llvm-svn: 328328
Sanjay Patel [Fri, 23 Mar 2018 15:31:31 +0000 (15:31 +0000)]
[InstSimplify] regenerate checks, move tests; NFC
llvm-svn: 328327
Zaara Syeda [Fri, 23 Mar 2018 15:28:15 +0000 (15:28 +0000)]
Re-commit: [MachineLICM] Add functions to MachineLICM to hoist invariant stores
This patch adds functions to allow MachineLICM to hoist invariant stores.
Currently, MachineLICM does not hoist any store instructions, however
when storing the same value to a constant spot on the stack, the store
instruction should be considered invariant and be hoisted. The function
isInvariantStore iterates each operand of the store instruction and checks
that each register operand satisfies isCallerPreservedPhysReg. The store
may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore.
This patch also adds the PowerPC changes needed to consider the stack
register as caller preserved.
Differential Revision: https://reviews.llvm.org/D40196
llvm-svn: 328326
Sanjay Patel [Fri, 23 Mar 2018 15:19:35 +0000 (15:19 +0000)]
[InstCombine] regenerate test checks; NFC
llvm-svn: 328325
Simon Pilgrim [Fri, 23 Mar 2018 15:17:50 +0000 (15:17 +0000)]
[X86][Btver2] Cleanup DPPS/DPPD instructions to use JFPA/JFPM function units
llvm-svn: 328324
Sanjay Patel [Fri, 23 Mar 2018 15:07:35 +0000 (15:07 +0000)]
[InstCombine] reduce code duplication; NFC
llvm-svn: 328323
Sanjay Patel [Fri, 23 Mar 2018 14:48:31 +0000 (14:48 +0000)]
[InstCombine] improve variable name; NFC
llvm-svn: 328322
John Brawn [Fri, 23 Mar 2018 14:47:07 +0000 (14:47 +0000)]
[AArch64] Don't reduce the width of loads if it prevents combining a shift
Loads and stores can only shift the offset register by the size of the value
being loaded, but currently the DAGCombiner will reduce the width of the load
if it's followed by a trunc making it impossible to later combine the shift.
Solve this by implementing shouldReduceLoadWidth for the AArch64 backend and
make it prevent the width reduction if this is what would happen, though do
allow it if reducing the load width will let us eliminate a later sign or zero
extend.
Differential Revision: https://reviews.llvm.org/D44794
llvm-svn: 328321
Simon Pilgrim [Fri, 23 Mar 2018 14:45:03 +0000 (14:45 +0000)]
[X86][Btver2] Fix MicroOps counts for DPPS/YMM memory folded instructions
This was due to a misunderstanding over what llvm calls a micro-op (retirement unit) is actually called a macro-op on the AMD/Jaguar target. Folded loads don't affect num macro ops.
llvm-svn: 328320
George Rimar [Fri, 23 Mar 2018 14:43:51 +0000 (14:43 +0000)]
[ELF] - Simplify. NFC.
llvm-svn: 328319
Simon Pilgrim [Fri, 23 Mar 2018 14:27:26 +0000 (14:27 +0000)]
[X86][Btver2] Cleanup SSE42 PCMPISTR/PCMPESTR string instructions to correctly use JFPU1 scheduler pipe followed by JLAGU/JSAGU/JFPA/JVALU function units
Fixes throughput to match Agner/Fam16h-SoG as well.
llvm-svn: 328318
Daniel Neilson [Fri, 23 Mar 2018 14:25:35 +0000 (14:25 +0000)]
Remove the deprecated single-alignment IRBuilder API for memcpy/memmove (NFC)
Summary:
This change is part of step six in the series of changes to remove the alignment
argument from memcpy/memmove/memset in favour of alignment attributes. At this
point all users of the IRBuilder APIs for creating a memcpy/memmove call given
a single value for alignment have been updated. We want to discourage usage of
these old APIs in favour of the newer ones that allow for separate source and
destination alignments, so this patch deletes the old API.
Specifically, we remove from IRBuilder:
CallInst *CreateMemCpy(Value *Dst, Value *Src, uint64_t Size, unsigned Align,
bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *TBAAStructTag = nullptr,
MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr)
CallInst *CreateMemCpy(Value *Dst, Value *Src, Value *Size, unsigned Align,
bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *TBAAStructTag = nullptr,
MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr)
CallInst *CreateMemMove(Value *Dst, Value *Src, uint64_t Size, unsigned Align,
bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr)
CallInst *CreateMemMove(Value *Dst, Value *Src, Value *Size, unsigned Align,
bool isVolatile = false, MDNode *TBAATag = nullptr,
MDNode *ScopeTag = nullptr,
MDNode *NoAliasTag = nullptr)
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816, rL327398, rL327421, rL328097 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
llvm-svn: 328317
Matthew Simpson [Fri, 23 Mar 2018 14:18:27 +0000 (14:18 +0000)]
[SLP] Stop counting cost of gather sequences with multiple uses
When building the SLP tree, we look for reuse among the vectorized tree
entries. However, each gather sequence is represented by a unique tree entry,
even though the sequence may be identical to another one. This means, for
example, that a gather sequence with two uses will be counted twice when
computing the cost of the tree. We should only count the cost of the definition
of a gather sequence rather than its uses. During code generation, the
redundant gather sequences are emitted, but we optimize them away with CSE. So
it looks like this problem just affects the cost model.
Differential Revision: https://reviews.llvm.org/D44742
llvm-svn: 328316
Daniel Neilson [Fri, 23 Mar 2018 14:02:54 +0000 (14:02 +0000)]
Remove deprecated MemIntrinsic methods (NFC)
Summary:
This change is part of step six in the series of changes to remove
the alignment argument from memcpy/memmove/memset in favour of
alignment attributes. At this point all uses of
MemIntrinsicInst::[get|set]Alignment() have been updated, so we now
remove these methods entirely to discourage their use.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816, rL327398, rL327421, rL328097 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
llvm-svn: 328315
Alexey Bataev [Fri, 23 Mar 2018 13:35:54 +0000 (13:35 +0000)]
[DEBUGINFO] Add flag for DWARF2 to use sections as references.
Summary:
Some targets does not support labels inside debug sections, but support
references in form `section+offset`. Patch adds initial support
for this.
Reviewers: echristo, probinson, jlebar
Subscribers: llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D43943
llvm-svn: 328314
Christof Douma [Fri, 23 Mar 2018 13:02:03 +0000 (13:02 +0000)]
[ARM] Support float literals under XO
When targeting execute-only and fp-armv8, float constants in a compare
resulted in instruction selection failures. This is now fixed by using
vmov.f32 where possible, otherwise the floating point constant is
lowered into a integer constant that is moved into a floating point
register.
This patch also restores using fpcmp with immediate 0 under fp-armv8.
Change-Id: Ie87229706f4ed879a0c0cf66631b6047ed6c6443
llvm-svn: 328313
Florian Hahn [Fri, 23 Mar 2018 12:49:39 +0000 (12:49 +0000)]
Revert r328307: [IPSCCP] Use constant range information for comparisons of parameters.
Reverted for now, due to it causing verifier failures.
llvm-svn: 328312
Amara Emerson [Fri, 23 Mar 2018 12:48:57 +0000 (12:48 +0000)]
[GlobalISel] Fix legalizer combine to not use illegal input G_EXTRACT.
This was being masked because GISel is enabled by default for -O0 and
the abort was disabled. Modified test to explicitly enable abort.
llvm-svn: 328311
Matthew Simpson [Fri, 23 Mar 2018 12:47:54 +0000 (12:47 +0000)]
[test] Allow for optional No-Op Barrier Pass in O0 pipeline
llvm-svn: 328310
Simon Pilgrim [Fri, 23 Mar 2018 12:08:23 +0000 (12:08 +0000)]
[X86][Znver1] Fix instregex entries that don't match any instructions (D44687)
Reviewed by @GGanesh and @craig.topper
llvm-svn: 328309
Simon Pilgrim [Fri, 23 Mar 2018 11:56:38 +0000 (11:56 +0000)]
[X86][SandyBridge] Fix missing comma that was causing string concatenation of 2 instregex entries
Found while updating D44687
llvm-svn: 328308
Florian Hahn [Fri, 23 Mar 2018 11:56:00 +0000 (11:56 +0000)]
[IPSCCP] Use constant range information for comparisons of parameters.
For comparisons with parameters, we can use the ParamState lattice
elements which also provide constant range information. This improves
the code for PR33253 further and gets us closer to use
ValueLatticeElement for all values.
Also, as we are using the range information in the solver directly, we
do not need tryToReplaceWithConstantRange afterwards anymore.
Reviewers: dberlin, mssimpso, davide, efriedma
Reviewed By: mssimpso
Differential Revision: https://reviews.llvm.org/D43762
llvm-svn: 328307
Andrea Di Biagio [Fri, 23 Mar 2018 11:50:43 +0000 (11:50 +0000)]
[llvm-mca] Pass the InstrBuilder to the constructor of Backend.
This is done in preparation for the fix for PR36784.
No functional change.
llvm-svn: 328306
Andrea Di Biagio [Fri, 23 Mar 2018 11:33:09 +0000 (11:33 +0000)]
[llvm-mca] Add flag -resource-pressure to enable/disable printing of the resource pressure view.
By default, the tool always enables the resource pressure view.
This flag lets user specify whether they want to add that view or not.
llvm-svn: 328305
Simon Pilgrim [Fri, 23 Mar 2018 11:27:31 +0000 (11:27 +0000)]
[X86][Btver2] Vector move/load/store instructions use a JFPU01 scheduler pipe and JFPX/JVALU function unit as well as the AGUs
llvm-svn: 328304
Florian Hahn [Fri, 23 Mar 2018 11:00:42 +0000 (11:00 +0000)]
[AArch64] Clean-up a few over-eager regexps in models.
Patch by Simon Pilgrim <llvm-dev@redking.me.uk>
That is a slightly modified version of the AArch64 changes from
Simon's D44687 .
llvm-svn: 328303
Ilya Biryukov [Fri, 23 Mar 2018 10:39:15 +0000 (10:39 +0000)]
[clangd] Remove 'static' from a function inside anonymous ns. NFC
llvm-svn: 328302
Florian Hahn [Fri, 23 Mar 2018 10:38:12 +0000 (10:38 +0000)]
[LoopUnroll] Simplify induction variables after peeling too.
Loop peeling also has an impact on the induction variables, so we should
benefit from induction variable simplification after peeling too.
Reviewers: sanjoy, bogner, mzolotukhin, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D43878
llvm-svn: 328301
Benjamin Kramer [Fri, 23 Mar 2018 10:14:19 +0000 (10:14 +0000)]
[ORC] Join materialization thread in unit test
There's are race between this thread and the destructor of the test ORC
components on the main threads. I saw flaky failures there in about 4%
of the runs of this unit test.
llvm-svn: 328300
George Rimar [Fri, 23 Mar 2018 09:18:31 +0000 (09:18 +0000)]
[ELF] - Another fix for "LLD crashes with --emit-relocs when trying to proccess .eh_frame"
This fixes PR36367 which is about segfault when --emit-relocs is
used together with .eh_frame sections which happens because
of reordering of regular and .rel[a] sections.
Path changes loop that iterates over input sections to create
relocation target sections first.
Differential revision: https://reviews.llvm.org/D44679
llvm-svn: 328299
Martin Storsjo [Fri, 23 Mar 2018 09:10:03 +0000 (09:10 +0000)]
[ARM] Error out on .arm assembler directives on windows
Windows on arm is thumb only.
Differential Revision: https://reviews.llvm.org/D43005
llvm-svn: 328298
Martin Storsjo [Fri, 23 Mar 2018 08:36:47 +0000 (08:36 +0000)]
Revert "[DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))"
This reverts commit r328252. This change broke building a number
of projects when targeting ARM and AArch64, see PR36873.
llvm-svn: 328297
Craig Topper [Fri, 23 Mar 2018 06:58:55 +0000 (06:58 +0000)]
[X86] Give VPCMPEQQ the same itinerary as its SSE counterpart.
llvm-svn: 328296
Craig Topper [Fri, 23 Mar 2018 06:41:43 +0000 (06:41 +0000)]
[X86] Correct the latencies of SNB integer vector multiplies based on Agner's data. Add missing MMX multiplies.
llvm-svn: 328295
Craig Topper [Fri, 23 Mar 2018 06:41:41 +0000 (06:41 +0000)]
[X86] Match vpblendvb/vblendvps/vblendvpd itineraries to the SSE equivalent. Change pblendvb/blendvps/blendvpd to use WriteFVarBlend
llvm-svn: 328294
Craig Topper [Fri, 23 Mar 2018 06:41:40 +0000 (06:41 +0000)]
[X86] Change VPSADBW itinerary to SSE_INTALU_ITINS_P to match the SSE version.
llvm-svn: 328293
Craig Topper [Fri, 23 Mar 2018 06:41:39 +0000 (06:41 +0000)]
[X86] Give VLDDQUrm and LDDQUrm the same itinerary.
llvm-svn: 328292
Craig Topper [Fri, 23 Mar 2018 06:41:38 +0000 (06:41 +0000)]
[X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model.
The VMOVMSKBrr was in a separate InstRW with a lower latency, but I assume they should be the same and the higher latency matches Agners table so I'm going with that.
llvm-svn: 328291
Craig Topper [Fri, 23 Mar 2018 06:41:36 +0000 (06:41 +0000)]
[X86] Add VEXTRB/W/D/Q to Zen scheduler model.
The SSE versions were present, but not the VEX version.
llvm-svn: 328290
Craig Topper [Fri, 23 Mar 2018 06:41:35 +0000 (06:41 +0000)]
[X86] Fix the itinerary for vextractps to match extractps.
llvm-svn: 328289
Rafael Espindola [Fri, 23 Mar 2018 01:36:23 +0000 (01:36 +0000)]
Bring r328238 back with a fix.
The issues was that we were setting hidden visibility if, when
processing a hidden class, we found out that we needed to emit a
reference to a vtable provided by the standard library.
Original message:
Set dso_local on vtables.
llvm-svn: 328288
Nirav Dave [Fri, 23 Mar 2018 01:22:39 +0000 (01:22 +0000)]
[DAG] Fix node id invalidation in Instruction Selection.
Invalidation should be bit negation. Add missing negation.
llvm-svn: 328287
Jordan Rose [Fri, 23 Mar 2018 01:12:09 +0000 (01:12 +0000)]
Remove problematic PrettyStackTrace entry added in r328276
I'm not sure /why/ this is causing issues for libclang, but it is.
Unbreak the buildbots since it's already consumed an hour of my time.
llvm-svn: 328286
Rafael Espindola [Fri, 23 Mar 2018 00:42:47 +0000 (00:42 +0000)]
Fix the MSVC build.
llvm-svn: 328285
Rafael Espindola [Fri, 23 Mar 2018 00:35:27 +0000 (00:35 +0000)]
Fix PR36793.
With this patch lld will iterate over compile units to find the line
tables instead of assuming there is only one at offset 0.
llvm-svn: 328284
Volodymyr Sapsai [Fri, 23 Mar 2018 00:16:06 +0000 (00:16 +0000)]
[Modules] Update test to mention it requires C++14.
llvm-svn: 328283
George Karpenkov [Fri, 23 Mar 2018 00:16:03 +0000 (00:16 +0000)]
[analyzer] Trust _Nonnull annotations for system framework
Changes the analyzer to believe that methods annotated with _Nonnull
from system frameworks indeed return non null objects.
Local methods with such annotation are still distrusted.
rdar://
24291919
Differential Revision: https://reviews.llvm.org/D44341
llvm-svn: 328282
George Karpenkov [Fri, 23 Mar 2018 00:16:02 +0000 (00:16 +0000)]
[analyzer] Extend GCDAntipatternChecker to match group_enter/group_leave pattern
rdar://
38480416
Differential Revision: https://reviews.llvm.org/D44653
llvm-svn: 328281
George Karpenkov [Fri, 23 Mar 2018 00:16:01 +0000 (00:16 +0000)]
[analyzer] [NFC] Move worklist implementation to WorkList.cpp
Current location is very confusing, especially because there is already
WorkList.h, and other code in CoreEngine.cpp is not related to work list
implementation.
Differential Revision: https://reviews.llvm.org/D44759
llvm-svn: 328280
Vitaly Buka [Fri, 23 Mar 2018 00:15:10 +0000 (00:15 +0000)]
[sanitizer] Fix PPC bot
llvm-svn: 328279
Davide Italiano [Fri, 23 Mar 2018 00:14:41 +0000 (00:14 +0000)]
[CommandObjectFrame] Remove dead code.
llvm-svn: 328278
Abderrazek Zaafrani [Fri, 23 Mar 2018 00:08:40 +0000 (00:08 +0000)]
[ARM] Add ARMv8.2-A FP16 vector intrinsic
Putting back the code in commit r327189 that was reverted in r322737. The code is being committed in three stages and this one is the last stage: 1) r327455 fp16 feature flags, 2) r327836 pass half type or i16 based on FullFP16, and 3) the code here which the front-end fp16 vector intrinsic for ARM.
Differential revision https://reviews.llvm.org/D43650
llvm-svn: 328277
Jordan Rose [Fri, 23 Mar 2018 00:07:18 +0000 (00:07 +0000)]
Sink PrettyDeclStackTrace down to the AST library
...and add some very basic stack trace entries for module building.
This would have helped track down rdar://problem/
38434694 sooner.
llvm-svn: 328276
Craig Topper [Fri, 23 Mar 2018 00:02:45 +0000 (00:02 +0000)]
[TableGen] Don't capture returned std::vectors by const reference.
The full vector is being returned not a reference. So the reference was just a to a temporary.
llvm-svn: 328275
Kevin Enderby [Thu, 22 Mar 2018 23:59:35 +0000 (23:59 +0000)]
For llvm-nm and Mach-O files also use function starts info in some
cases when printing symbols. As an improvement to:
r305733 - Change llvm-nm for Mach-O files to use dyld info in some cases when printing symbols
it could be made a bit better if it also read the function starts and faked
up nlist entries to those address not already faked up by the other
dyld info. This would help with stripped static functions.
rdar://
38761029
llvm-svn: 328274
Petr Hosek [Thu, 22 Mar 2018 23:58:37 +0000 (23:58 +0000)]
[sanitizer] zx_vmo_write on Fuchsia takes only 4 arguments now
The system call now fails when it cannot write the requested size.
Update the sanitizer runtime Fuchsia implementation accordingly.
Differential Revision: https://reviews.llvm.org/D44770
llvm-svn: 328273
Michael Zolotukhin [Thu, 22 Mar 2018 23:44:40 +0000 (23:44 +0000)]
State that CFG is preserved in 'Falkor HW Prefetch Fix Late Phase'.
That removes some redundant recomputations from the passes pipeline.
llvm-svn: 328272
Fangrui Song [Thu, 22 Mar 2018 23:40:02 +0000 (23:40 +0000)]
[Support/Parallel] Use lock_guard which has less overhead than unique_lock.
Summary: unique_lock has the overhead of tracking ownership status and the owner.
Reviewers: grimar, zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44698
llvm-svn: 328271
Julie Hockett [Thu, 22 Mar 2018 23:34:46 +0000 (23:34 +0000)]
[clang-doc] Reland "[clang-doc] Setup clang-doc frontend framework"
Fixed windows release build tests.
llvm-svn: 328270
Eric Fiselier [Thu, 22 Mar 2018 23:14:20 +0000 (23:14 +0000)]
Add temporary printouts to test to help debug failures.
Some debian libc++ bots started having failures in the locale
tests due to what I assume is a change in the locale data for fr_FR
in glibc.
This change prints the actual value from the test to help debugging.
It should be reverted once the bots cycle.
llvm-svn: 328268
Michael Zolotukhin [Thu, 22 Mar 2018 23:02:48 +0000 (23:02 +0000)]
Reapply "[test] Add tests for llc passes pipelines." with a fix for bots with expensive checks on.
llvm-svn: 328267
Rafael Espindola [Thu, 22 Mar 2018 23:02:19 +0000 (23:02 +0000)]
Set dso_local on __ImageBase.
llvm-svn: 328266
Eric Fiselier [Thu, 22 Mar 2018 23:01:08 +0000 (23:01 +0000)]
Avoid Clang error about throwing _LIBCPP_ASSERT in noexcept function.
This fixes a couple of tests which produced a warning that a 'throw'
occurred in a noexcept function (by way of _LIBCPP_ASSERT). It does
so by hiding the 'throw' across an opaque function boundary.
This fix isn't ideal, since we still have _LIBCPP_ASSERT's in functions
marked noexcept -- and this problem should be addressed in the future.
However, throwing _LIBCPP_ASSERT is really only meant to allow testing
of the assertions, and is not yet ready for general use.
llvm-svn: 328265
Stephan T. Lavavej [Thu, 22 Mar 2018 22:59:02 +0000 (22:59 +0000)]
[libcxx] [test] Strip trailing whitespace. NFC.
llvm-svn: 328264
Rafael Espindola [Thu, 22 Mar 2018 22:57:48 +0000 (22:57 +0000)]
Add a test.
This would have found the regression in r328238.
llvm-svn: 328263
David Blaikie [Thu, 22 Mar 2018 22:42:44 +0000 (22:42 +0000)]
Move SampleProfile.h into IPO along with the rest of the IPO pass headers
llvm-svn: 328262
Eric Fiselier [Thu, 22 Mar 2018 22:32:55 +0000 (22:32 +0000)]
Workaround GCC bug PR78489 - SFINAE order is not respected.
This patch works around variant test failures which are new to
GCC 8. GCC 8 either doesn't perform SFINAE in lexical order, or
it doesn't halt after encountering the first failure. This
causes hard error to occur instead of substitution failure.
See gcc.gnu.org/PR78489
llvm-svn: 328261
Craig Topper [Thu, 22 Mar 2018 22:17:11 +0000 (22:17 +0000)]
[X86] Correct the VROUND regular expressions in Znver1 scheduler model to account for r328254
llvm-svn: 328260
David Blaikie [Thu, 22 Mar 2018 22:07:53 +0000 (22:07 +0000)]
Finish moving the IPSCCP pass from Scalar to IPO - moving the registration
llvm-svn: 328259
Artem Dergachev [Thu, 22 Mar 2018 22:05:53 +0000 (22:05 +0000)]
[analyzer] Enable temporary object destructor inlining by default.
When a temporary is constructed with a proper construction context, it should
be safe to inline the destructor. We have added suppressions for some of the
common false positives caused by such inlining, so there should be - and from my
observations there indeed is - more benefit than harm from enabling destructor
inlining.
Differential Revision: https://reviews.llvm.org/D44721
llvm-svn: 328258
Evgeny Stupachenko [Thu, 22 Mar 2018 22:04:39 +0000 (22:04 +0000)]
Revert r325687 (workaround for PR36032).
Summary:
Revert r325687 workaround for PR36032 since
a fix was committed in r326154.
Reviewers: sbaranga
Differential Revision: http://reviews.llvm.org/D44768
From: Evgeny Stupachenko <evstupac@gmail.com>
<evgeny.v.stupachenko@intel.com>
llvm-svn: 328257
Rafael Espindola [Thu, 22 Mar 2018 22:04:32 +0000 (22:04 +0000)]
Add test for demangling GNU ABI tags.
Patch by Christopher James Halse Rogers!
llvm-svn: 328256
Artem Dergachev [Thu, 22 Mar 2018 22:02:38 +0000 (22:02 +0000)]
[CFG] [analyzer] Add C++17-specific ctor-initializer construction contexts.
CXXCtorInitializer-based constructors are also affected by the C++17 mandatory
copy elision, like variable constructors and return value constructors.
Extend r328248 to support those.
Differential Revision: https://reviews.llvm.org/D44763
llvm-svn: 328255
Craig Topper [Thu, 22 Mar 2018 21:55:20 +0000 (21:55 +0000)]
[X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD
This makes the Y position consistent with other instructions.
This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary.
llvm-svn: 328254
Artem Dergachev [Thu, 22 Mar 2018 21:54:48 +0000 (21:54 +0000)]
[analyzer] Remove an assertion that doesn't hold in C++17.
Function return values can be constructed directly in variables or passed
directly into return statements, without even an elidable copy in between.
This is how the C++17 mandatory copy elision AST behaves. The behavior we'll
have in such cases is the "old" behavior that we've had before we've
implemented destructor inlining and proper lifetime extension support.
Differential Revision: https://reviews.llvm.org/D44755
llvm-svn: 328253
Guozhi Wei [Thu, 22 Mar 2018 21:47:25 +0000 (21:47 +0000)]
[DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))
In our real world application, we found the following optimization is missed in DAGCombiner
(zext (and/or/xor (shl/shr (load x), cst), cst)) -> (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst))
If the user of original zext is an add, it may enable further lea optimization on x86.
This patch add a new function CombineZExtLogicopShiftLoad to do this optimization.
Differential Revision: https://reviews.llvm.org/D44402
llvm-svn: 328252
David Blaikie [Thu, 22 Mar 2018 21:41:29 +0000 (21:41 +0000)]
Fix layering between SCCP and IPO SCCP
Transforms/Scalar/SCCP.cpp implemented both the Scalar and IPO SCCP, but
this meant Transforms/Scalar including Transfroms/IPO headers, creating
a circular dependency. (IPO depends on Scalar already) - so move the IPO
SCCP shims out into IPO and the basic library implementation accessible
from Scalar/SCCP.h to be used from the IPO/SCCP.cpp implementation.
llvm-svn: 328250