Artem Dergachev [Mon, 1 Jul 2019 23:01:59 +0000 (23:01 +0000)]
[analyzer] exploded-graph-rewriter: Add support for dynamic types.
Slightly cleanup emission of horizontal lines and unhardcode the title
for generic maps.
Differential Revision: https://reviews.llvm.org/D64041
llvm-svn: 364865
Artem Dergachev [Mon, 1 Jul 2019 23:01:55 +0000 (23:01 +0000)]
[analyzer] exploded-graph-rewriter: Implement program point tags.
Keep them on a separate line for more visibility.
Differential Revision: https://reviews.llvm.org/D63965
llvm-svn: 364864
Marshall Clow [Mon, 1 Jul 2019 23:00:34 +0000 (23:00 +0000)]
Update status for bit operations
llvm-svn: 364863
Marshall Clow [Mon, 1 Jul 2019 23:00:32 +0000 (23:00 +0000)]
Bit Operations: P0556, P0553 and P1355. Reviewed as: https://reviews.llvm.org/D51262
llvm-svn: 364862
Reid Kleckner [Mon, 1 Jul 2019 22:43:39 +0000 (22:43 +0000)]
[PGO] Update ICP pass for recent byval type changes
Fixes verifier errors encountered in PR42413.
Reviewers: xur, t.p.northover, inglorion, gbiv, george.burgess.iv
Differential Revision: https://reviews.llvm.org/D63842
llvm-svn: 364861
Stella Stamenova [Mon, 1 Jul 2019 22:12:55 +0000 (22:12 +0000)]
[lldb] [lldbsuite] Use a unique class name for TestValueVarUpdate
It looks like when this test was added, it was based on TestHelloWorld and it ended up with the same class name. This is an issue because the logs associated with the tests use the class name as the identifier for the file and if two tests have the same name their logs overwrite each other. On non-windows, this just means we lose one of the logs, but on Windows this means that one of the tests will fail occasionally because the file are locked by the other test.
llvm-svn: 364860
Matt Arsenault [Mon, 1 Jul 2019 22:01:05 +0000 (22:01 +0000)]
AMDGPU: Correct properties for adjcallstack* pseudos
These should be SALU writes, and these are lowered to instructions
that def SCC.
llvm-svn: 364859
Matt Arsenault [Mon, 1 Jul 2019 22:00:59 +0000 (22:00 +0000)]
Fix broken C++ mode comment
llvm-svn: 364858
Huihui Zhang [Mon, 1 Jul 2019 22:00:32 +0000 (22:00 +0000)]
[InstCombine][NFCI] Update test cases in onehot_merge.ll
Use both one bit and signbit shifting to check for one bit merge.
Reviewers: lebedev.ri, spatel, efriedma, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63903
llvm-svn: 364857
Sanjay Patel [Mon, 1 Jul 2019 22:00:00 +0000 (22:00 +0000)]
[InstCombine] reduce more checks for power-of-2-or-zero using ctpop
Extends the transform from:
rL364341
...to include another (more common?) pattern that tests whether a
value is a power-of-2 (including or excluding zero).
llvm-svn: 364856
JF Bastien [Mon, 1 Jul 2019 21:57:31 +0000 (21:57 +0000)]
Fix breakage introduced by D60974
D60974 added tests which incorrectly assume that llvm-readelf is available. This is a bad assumption, it should instead declare the dependency explicitly in the tests.
llvm-svn: 364855
Jonas Devlieghere [Mon, 1 Jul 2019 21:25:34 +0000 (21:25 +0000)]
[Reproducer] Assert on unexpected packet
I'm not able to reproduce the reproducer flakiness we're seeing on
GreenDragon. I want to add this assert to find out if the GDB remote
packets are somehow getting out of sync when this happens.
llvm-svn: 364852
Craig Topper [Mon, 1 Jul 2019 21:25:11 +0000 (21:25 +0000)]
[X86] Use v4i32 vzloads instead of v2i64 for vpmovzx/vpmovsx patterns where only 32-bits are loaded.
v2i64 vzload defines a 64-bit memory access. It doesn't look like
we have any coverage for this either way.
Also remove some vzload usages where the instruction loads only
16-bits.
llvm-svn: 364851
Simon Atanasyan [Mon, 1 Jul 2019 21:25:04 +0000 (21:25 +0000)]
[mips] Add missing schedinfo for MIPSeh_return[32|64] instructions
llvm-svn: 364850
Simon Atanasyan [Mon, 1 Jul 2019 21:24:58 +0000 (21:24 +0000)]
[mips] Add virtualization ASE to P5600 scheduling definitions
llvm-svn: 364849
Simon Atanasyan [Mon, 1 Jul 2019 21:24:51 +0000 (21:24 +0000)]
[mips] Add missing schedinfo for LONG_BRANCH_* instructions
llvm-svn: 364848
Craig Topper [Mon, 1 Jul 2019 21:23:38 +0000 (21:23 +0000)]
[X86] Remove several bad load folding isel patterns for VPMOVZX/VPMOVSX.
These patterns all matched a v2i64 vzload which only loads 64-bits
to instructions that load a full 128-bits.
llvm-svn: 364847
Jordan Rupprecht [Mon, 1 Jul 2019 21:10:43 +0000 (21:10 +0000)]
Revert [SLP] Look-ahead operand reordering heuristic.
This reverts r364478 (git commit
574cb0eb3a7ac95e62d223a60bef891171dfe321)
The patch is causing compilation timeouts.
llvm-svn: 364846
Alex Langford [Mon, 1 Jul 2019 20:36:33 +0000 (20:36 +0000)]
[Core] Generalize ValueObject::IsRuntimeSupportValue
Summary:
Instead of falling back to ObjCLanguageRuntime, we should be falling
back to every loaded language runtime. This makes ValueObject more
language agnostic.
Reviewers: labath, compnerd, JDevlieghere, davide
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D63240
llvm-svn: 364845
Roman Lebedev [Mon, 1 Jul 2019 20:33:56 +0000 (20:33 +0000)]
[NFC][InstCombine] More commutative tests for "shift direction in bittest" (PR42466)
'and' is commutative, if we don't want to touch shift-of-const,
we still need to check the other hand of 'and'.
llvm-svn: 364844
Nilanjana Basu [Mon, 1 Jul 2019 20:27:37 +0000 (20:27 +0000)]
Testing commit access through minor formatting change
llvm-svn: 364843
Eric Fiselier [Mon, 1 Jul 2019 19:59:34 +0000 (19:59 +0000)]
Ensure bitset's string constructor doesn't poison the overload set.
llvm-svn: 364842
Matt Arsenault [Mon, 1 Jul 2019 19:36:10 +0000 (19:36 +0000)]
GlobalISel: Try to widen merges with other merges
If the requested source type an be used as a merge source type, create
a merge of merges. This avoids creating large, illegal extensions and
bit-ops directly to the result type.
llvm-svn: 364841
Marshall Clow [Mon, 1 Jul 2019 19:22:00 +0000 (19:22 +0000)]
Implement P0646R1: Erase-Like Algorithms Should Return size_type. Reviewed as https://reviews.llvm.org/D58332, and then updated because I rewrote a couple of those routines to eliminate some UB. Thanks to Zoe for tghe patch.
llvm-svn: 364840
Matt Arsenault [Mon, 1 Jul 2019 19:09:57 +0000 (19:09 +0000)]
AMDGPU: Revert accidental change to test
llvm-svn: 364839
Craig Topper [Mon, 1 Jul 2019 19:01:37 +0000 (19:01 +0000)]
[X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
These instructions only read 64-bits of memory so we shouldn't
allow a full vector width load to be pattern matched in case it
is marked volatile.
Instead allow vzload or scalar_to_vector+load.
Also add a DAG combine to turn full vector loads into vzload when
used by one of these instructions if the load isn't volatile.
This fixes another case for PR42079
llvm-svn: 364838
Alexander Kornienko [Mon, 1 Jul 2019 18:55:10 +0000 (18:55 +0000)]
Fixed two issues in clang-tidy -help.
HeaderFilter -> HeaderFilterRegex
llvm-svn: 364837
Matt Arsenault [Mon, 1 Jul 2019 18:50:50 +0000 (18:50 +0000)]
AMDGPU/GlobalISel: Handle more input argument intrinsics
llvm-svn: 364836
Matt Arsenault [Mon, 1 Jul 2019 18:49:01 +0000 (18:49 +0000)]
AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics
llvm-svn: 364835
Matt Arsenault [Mon, 1 Jul 2019 18:47:22 +0000 (18:47 +0000)]
AMDGPU/GlobalISel: Legalize workgroup ID intrinsics
llvm-svn: 364834
Matt Arsenault [Mon, 1 Jul 2019 18:45:36 +0000 (18:45 +0000)]
AMDGPU/GlobalISel: Legalize workitem ID intrinsics
Tests don't cover the masked input path since non-kernel arguments
aren't lowered yet.
Test is copied directly from the existing test, with 2 additions.
llvm-svn: 364833
Matt Arsenault [Mon, 1 Jul 2019 18:40:23 +0000 (18:40 +0000)]
AMDGPU/GlobalISel: Custom lower control flow intrinsics
Replace the brcond for the 2 cases that act as branches. For now
follow how the current system works, although I think we can
eventually get rid of the pseudos.
llvm-svn: 364832
Matt Arsenault [Mon, 1 Jul 2019 18:33:37 +0000 (18:33 +0000)]
AMDGPU/GlobalISel: Handle 16-bit SALU min/max
This needs to be extended to s32, and expanded into cmp+select. This
is relying on the fact that widenScalar happens to leave the
instruction in place, but this isn't a guaranteed property of
LegalizerHelper.
llvm-svn: 364831
Matt Arsenault [Mon, 1 Jul 2019 18:30:45 +0000 (18:30 +0000)]
AMDGPU/GlobalISel: Lower SALU min/max to cmp+select
Use a change observer to apply a register bank to the newly created
intermediate result register.
llvm-svn: 364830
Robert Lougher [Mon, 1 Jul 2019 18:28:21 +0000 (18:28 +0000)]
[X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2)
The function findPotentialBlockers may consider debug info instructions as
potential blockers and may stop searching for a store-load pair prematurely.
This patch corrects this and tests the cases where the store is separated
from the load by more than InspectionLimit debug instructions.
Patch by Chris Dawson.
Differential Revision: https://reviews.llvm.org/D62408
llvm-svn: 364829
Matt Arsenault [Mon, 1 Jul 2019 18:26:47 +0000 (18:26 +0000)]
AMDGPU/GlobalISel: Add tests for add legalization
llvm-svn: 364828
Matt Arsenault [Mon, 1 Jul 2019 18:18:55 +0000 (18:18 +0000)]
AMDGPU/GlobalISel: Legalize s16 add/sub/mul
If this is scalar, promote to s32. Use a new observer class to assign
the register bank of newly created registers.
llvm-svn: 364827
Stella Stamenova [Mon, 1 Jul 2019 18:13:20 +0000 (18:13 +0000)]
[lldb] [lldbsuite] Use a unique class name for TestBacktraceAll
It looks like when this test was added, it was based on TestBreakAfterJoin and it ended up with the same class name. This is an issue because the logs associated with the tests use the class name as the identifier for the file and if two tests have the same name their logs overwrite each other. On non-windows, this just means we lose one of the logs, but on Windows this means that one of the tests will fail occasionally because the file are locked by the other test.
llvm-svn: 364826
Matt Arsenault [Mon, 1 Jul 2019 18:13:12 +0000 (18:13 +0000)]
AMDGPU/GlobalISel: Fix allowing non-boolean conditions for G_SELECT
The condition register bank must be scc or vcc so that a copy will be
inserted, which will be lowered to a compare.
Currently greedy unnecessarily forces using a VCC select.
llvm-svn: 364825
Roman Lebedev [Mon, 1 Jul 2019 18:11:32 +0000 (18:11 +0000)]
[NFC][InstCombine] Add tests for "shift direction in bittest" (PR42466)
https://rise4fun.com/Alive/8O1
https://bugs.llvm.org/show_bug.cgi?id=42466
llvm-svn: 364824
Julian Lettner [Mon, 1 Jul 2019 18:06:31 +0000 (18:06 +0000)]
[TSan] Fix initialized and declared ‘extern’ warning
Avoid the following warning which fails a bot (via -Werror).
```
/tmp/gotsan.JfrpVPu7pG/gotsan.cc:10456:25: error: ‘_tsan_pointer_chk_guard’ initialized and declared ‘extern’ [-Werror]
extern "C" __tsan::uptr _tsan_pointer_chk_guard = 0;
^~~~~~~~~~~~~~~~~~~~~~~
```
llvm-svn: 364823
Matt Arsenault [Mon, 1 Jul 2019 18:01:35 +0000 (18:01 +0000)]
GlobalISel: Verify G_MERGE_VALUES operand sizes
llvm-svn: 364822
Aditya Nandakumar [Mon, 1 Jul 2019 17:53:50 +0000 (17:53 +0000)]
[GlobalISel]: Allow backends to custom legalize Intrinsics
https://reviews.llvm.org/D31359
Add a hook "legalizeInstrinsic" to allow backends to override this
and custom lower/legalize intrinsics.
llvm-svn: 364821
Alexey Bataev [Mon, 1 Jul 2019 17:46:52 +0000 (17:46 +0000)]
[OPENMP]Fix handling of lambda captures in target regions.
Previously, lambda captures were processed in the function called during
capturing the variables. It leads to the recursive functions calls and
may result in the compiler crash.
llvm-svn: 364820
Matt Arsenault [Mon, 1 Jul 2019 17:40:18 +0000 (17:40 +0000)]
AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghalt
llvm-svn: 364819
Julian Lettner [Mon, 1 Jul 2019 17:39:39 +0000 (17:39 +0000)]
[TSan] Improve handling of stack pointer mangling in {set,long}jmp, pt.2
Switch `LongJmp` over to lookup JmpBuf via plain old (unmangled) SP.
This makes the computation of mangled SPs in the TSan assembly files
unnecessary, which will be cleaned up in follow-up revisions.
Reviewed By: dvyukov
Differential Revision: https://reviews.llvm.org/D63942
llvm-svn: 364818
Matt Arsenault [Mon, 1 Jul 2019 17:35:53 +0000 (17:35 +0000)]
AMDGPU/GlobalISel: Legalize s16 fcmp
llvm-svn: 364817
Matt Arsenault [Mon, 1 Jul 2019 17:18:03 +0000 (17:18 +0000)]
GlobalISel: Implement lower for min/max
llvm-svn: 364816
Nicolai Haehnle [Mon, 1 Jul 2019 17:17:52 +0000 (17:17 +0000)]
AMDGPU/GFX10: implement ds_ordered_count changes
Summary:
ds_ordered_count can now simultaneously operate on up to 4 dwords
in a single instruction, which are taken from (and returned to)
lanes 0..3 of a single VGPR.
Change-Id: I19b6e7b0732b617c10a779a7f9c0303eec7dd276
Reviewers: mareko, arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63716
llvm-svn: 364815
Nicolai Haehnle [Mon, 1 Jul 2019 17:17:45 +0000 (17:17 +0000)]
AMDGPU: Support GDS atomics
Summary:
Original patch by Marek Olšák
Change-Id: Ia97d5d685a63a377d86e82942436d1fe6e429bab
Reviewers: mareko, arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63452
llvm-svn: 364814
Fangrui Song [Mon, 1 Jul 2019 17:12:26 +0000 (17:12 +0000)]
[ELF][RISCV] Support GD/LD/IE/LE TLS models
RISC-V psABI doesn't specify TLS relaxation. It can be handled the same
way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use
the same relocation type.
Reviewed By: jrtc27, ruiu
Differential Revision: https://reviews.llvm.org/D63220
llvm-svn: 364813
Fangrui Song [Mon, 1 Jul 2019 17:12:18 +0000 (17:12 +0000)]
[ELF][RISCV] Support PLT, GOT, copy and relative relocations
* Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20.
* Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT.
* Define SymbolRel as R_RISCV_{32,64}
* Generate PLT header: it is used by lazy binding PLT in glibc.
* R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT".
This behavior is different from ld.bfd but it is agreed the current lld behavior is favored.
I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see:
https://github.com/riscv/riscv-elf-psabi-doc/issues/98
https://sourceware.org/bugzilla/show_bug.cgi?id=24685
Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch.
Reviewed By: jrtc27
Differential Revision: https://reviews.llvm.org/D63076
llvm-svn: 364812
Matt Arsenault [Mon, 1 Jul 2019 17:04:57 +0000 (17:04 +0000)]
AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap
llvm-svn: 364811
Matt Arsenault [Mon, 1 Jul 2019 17:02:24 +0000 (17:02 +0000)]
AArch64/GlobalISel: Fix trying to select invalid MIR
Physical registers are not allowed to be a phi operand.
llvm-svn: 364810
Shaurya Gupta [Mon, 1 Jul 2019 16:55:29 +0000 (16:55 +0000)]
Summary: [Clangd] Added hidden command line option -tweaks to specify which tweaks to enable
- Only for development purposes
- Disabled tweaks in fixits-duplications test
Reviewers: sammccall, kadircet
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D63989
llvm-svn: 364809
Matt Arsenault [Mon, 1 Jul 2019 16:41:36 +0000 (16:41 +0000)]
AMDGPU/GlobalISel: RegBankSelect for amdgcn.writelane
llvm-svn: 364808
Matt Arsenault [Mon, 1 Jul 2019 16:36:39 +0000 (16:36 +0000)]
AMDGPU/GlobalISel: Fail instead of assert when selecting loads
llvm-svn: 364807
Matt Arsenault [Mon, 1 Jul 2019 16:34:48 +0000 (16:34 +0000)]
AMDGPU/GlobalISel: Complete implementation of G_GEP
Also works around tablegen defect in selecting add with unused carry,
but if we have to manually select GEP, might as well handle add
manually.
llvm-svn: 364806
Matt Arsenault [Mon, 1 Jul 2019 16:32:47 +0000 (16:32 +0000)]
AMDGPU/GlobalISel: Select G_PHI
llvm-svn: 364805
Matt Arsenault [Mon, 1 Jul 2019 16:27:32 +0000 (16:27 +0000)]
AMDGPU/GlobalISel: Try to select VOP3 form of add
There are several things broken, but at least emit the right thing for
gfx9.
The import of the pattern with the unused carry out seems to not
work. Needs a special class for clamp, because OperandWithDefaultOps
doesn't really work.
llvm-svn: 364804
Simon Pilgrim [Mon, 1 Jul 2019 16:20:47 +0000 (16:20 +0000)]
[X86] Add widenSubVector to size in bits helper. NFCI.
We can already widenSubVector to a specific type (of the same scalar type) - this variant just specifies the target vector size.
This will be useful when CombineShuffleWithExtract relaxes the need to have the same scalar type for all shuffle operand subvector sources.
llvm-svn: 364803
Marshall Clow [Mon, 1 Jul 2019 16:20:25 +0000 (16:20 +0000)]
Implement LWG2221: 'Formatted output for nullptr_t' Reviewed as: https://reviews.llvm.org/D63053
llvm-svn: 364802
Matt Arsenault [Mon, 1 Jul 2019 16:19:39 +0000 (16:19 +0000)]
AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane
llvm-svn: 364801
James Henderson [Mon, 1 Jul 2019 16:18:57 +0000 (16:18 +0000)]
[docs][llvm-readelf] Expand llvm-readelf documentation
Previously, the llvm-readelf documentation was essentially just a list
of differences to llvm-readobj. Since llvm-readelf is the more likely
goto tool for many people migrating to the LLVM toolchain, it seems like
it would be helpful to document all the switches in the llvm-readelf
document too. This change expands the options listed accordingly.
Additionally, they are unlikely to care what the differences are to
llvm-readobj, since they won't be familiar with the latter as there is
no GNU equivalent, so this change moves the "differences" section to
llvm-readobj's documentation.
Reviewed by: peter.smith
Differential Revision: https://reviews.llvm.org/D63826
llvm-svn: 364800
Bruce Mitchener [Mon, 1 Jul 2019 16:18:38 +0000 (16:18 +0000)]
__threading_support: Remove (void) in favor of ().
Summary:
This fixes a clang-tidy warning when building something that uses
this file.
Reviewers: mclow.lists, EricWF
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D43226
llvm-svn: 364799
Bruce Mitchener [Mon, 1 Jul 2019 16:13:31 +0000 (16:13 +0000)]
Fix -Wdouble-promotion warnings.
Reviewers: mclow.lists
Subscribers: christof, ldionne, cfe-commits, libcxx-commits
Differential Revision: https://reviews.llvm.org/D62782
llvm-svn: 364798
Tom Stellard [Mon, 1 Jul 2019 16:09:33 +0000 (16:09 +0000)]
AMDGPU/GlobalISel: Implement select for 32-bit G_ADD
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58804
llvm-svn: 364797
Mikhail Maltsev [Mon, 1 Jul 2019 16:07:58 +0000 (16:07 +0000)]
[ARM] Fix MVE_VQxDMLxDH instruction class
Summary:
According to the ARMARM, the VQDMLADH, VQRDMLADH, VQDMLSDH and
VQRDMLSDH instructions handle their results as follows: "The base
variant writes the results into the lower element of each pair of
elements in the destination register, whereas the exchange variant
writes to the upper element in each pair". I.e., the initial content
of the output register affects the result, as usual, we model this
with an additional input.
Also, for 32-bit variants Qd is not allowed to be the same register as
Qm and Qn, we use @earlyclobber to indicate this.
This patch also changes vpred_r to vpred_n because the instructions
don't have an explicit 'inactive' operand.
Reviewers: dmgreen, ostannard, simon_tatham
Reviewed By: simon_tatham
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64007
llvm-svn: 364796
Matt Arsenault [Mon, 1 Jul 2019 16:06:02 +0000 (16:06 +0000)]
AMDGPU/GlobalISel: Select G_BRCOND for vcc
llvm-svn: 364795
Mikhail Maltsev [Mon, 1 Jul 2019 16:05:23 +0000 (16:05 +0000)]
[ARM] MVE: support QQPRRegClass and QQQQPRRegClass
Summary:
QQPRRegClass and QQQQPRRegClass are used by the
interleaving/deinterleaving loads/stores to represent sequences of
consecutive SIMD registers.
Reviewers: ostannard, simon_tatham, dmgreen
Reviewed By: simon_tatham
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64009
llvm-svn: 364794
Krzysztof Parzyszek [Mon, 1 Jul 2019 16:01:15 +0000 (16:01 +0000)]
Update email address in CODE_OWNERS
llvm-svn: 364793
Roman Lebedev [Mon, 1 Jul 2019 15:55:24 +0000 (15:55 +0000)]
[InstCombine] (Y + ~X) + 1 --> Y - X fold (PR42459)
Summary:
To be noted, this pattern is not unhandled by instcombine per-se,
it is somehow does end up being folded when one runs opt -O3,
but not if it's just -instcombine. Regardless, that fold is
indirect, depends on some other folds, and is thus blind
when there are extra uses.
This does address the regression being exposed in D63992.
https://godbolt.org/z/7DGltU
https://rise4fun.com/Alive/EPO0
Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=42459 | PR42459 ]]
Reviewers: spatel, nikic, huihuiz
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63993
llvm-svn: 364792
Roman Lebedev [Mon, 1 Jul 2019 15:55:15 +0000 (15:55 +0000)]
[InstCombine] Shift amount reassociation in bittest (PR42399)
Summary:
Given pattern:
`icmp eq/ne (and ((x shift Q), (y oppositeshift K))), 0`
we should move shifts to the same hand of 'and', i.e. rewrite as
`icmp eq/ne (and (x shift (Q+K)), y), 0` iff `(Q+K) u< bitwidth(x)`
It might be tempting to not restrict this to situations where we know
we'd fold two shifts together, but i'm not sure what rules should there be
to avoid endless combine loops.
We pick the same shift that was originally used to shift the variable we picked to shift:
https://rise4fun.com/Alive/6x1v
Should fix [[ https://bugs.llvm.org/show_bug.cgi?id=42399 | PR42399]].
Reviewers: spatel, nikic, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63829
llvm-svn: 364791
Krzysztof Parzyszek [Mon, 1 Jul 2019 15:50:09 +0000 (15:50 +0000)]
[Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1)
llvm-svn: 364790
Matt Arsenault [Mon, 1 Jul 2019 15:48:18 +0000 (15:48 +0000)]
AMDGPU/GlobalISel: Select G_FRAME_INDEX
llvm-svn: 364789
Nicolai Haehnle [Mon, 1 Jul 2019 15:43:00 +0000 (15:43 +0000)]
AMDGPU/GFX10: fix scratch resource descriptor
Summary:
The stride should depend on the wave size, not the hardware generation.
Also, the 32_FLOAT format is 0x16, not 16; though that shouldn't be
relevant.
Change-Id: I088f93bf6708974d085d1c50967f119061da6dc6
Reviewers: arsenm, rampitec, mareko
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63808
llvm-svn: 364788
Matt Arsenault [Mon, 1 Jul 2019 15:42:47 +0000 (15:42 +0000)]
AMDGPU/GlobalISel: Make s16 select legal
This is easy to handle and avoids legalization artifacts which are
likely to obscure combines.
llvm-svn: 364787
Matt Arsenault [Mon, 1 Jul 2019 15:39:27 +0000 (15:39 +0000)]
AMDGPU/GlobalISel: Select G_BRCOND for scc conditions
llvm-svn: 364786
Gabor Marton [Mon, 1 Jul 2019 15:37:07 +0000 (15:37 +0000)]
[ASTImporter] Mark erroneous nodes in shared st
Summary:
Now we store the errors for the Decls in the "to" context too. For
that, however, we have to put these errors in a shared state (among all
the ASTImporter objects which handle the same "to" context but different
"from" contexts).
After a series of imports from different "from" TUs we have a "to" context
which may have erroneous nodes in it. (Remember, the AST is immutable so
there is no way to delete a node once we had created it and we realized
the error later.) All these erroneous nodes are marked in
ASTImporterSharedState::ImportErrors. Clients of the ASTImporter may
use this as an input. E.g. the static analyzer engine may not try to
analyze a function if that is marked as erroneous (it can be queried via
ASTImporterSharedState::getImportDeclErrorIfAny()).
Reviewers: a_sidorin, a.sidorin, shafik
Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D62376
llvm-svn: 364785
Matt Arsenault [Mon, 1 Jul 2019 15:23:04 +0000 (15:23 +0000)]
AMDGPU/GlobalISel: Tolerate copies with no type set
isVCC has the same bug, but isn't used in a context where it can cause
a problem.
llvm-svn: 364784
Matt Arsenault [Mon, 1 Jul 2019 15:23:03 +0000 (15:23 +0000)]
AMDGPU: Fix tests using the default alloca address space
llvm-svn: 364783
Matt Arsenault [Mon, 1 Jul 2019 15:18:56 +0000 (15:18 +0000)]
AMDGPU/GlobalISel: Select src modifiers
llvm-svn: 364782
Michal Gorny [Mon, 1 Jul 2019 15:11:42 +0000 (15:11 +0000)]
[lldb] [Process/NetBSD] Use global enable bits for watchpoints
Set global enable bits (i.e. bits 1, 3, 5, 7) to enable watchpoints
on NetBSD rather than the local enable bits (0, 2, 4, 6). The former
are necessary for watchpoints to be correctly recognized by the NetBSD
kernel. The latter cause them to be reported as trace points.
Differential Revision: https://reviews.llvm.org/D63792
llvm-svn: 364781
Michal Gorny [Mon, 1 Jul 2019 15:11:10 +0000 (15:11 +0000)]
[lldb] [Process/NetBSD] Fix segfault when handling watchpoint
Fix the watchpoint/breakpoint code to search for matching thread entry
in m_threads explicitly rather than assuming that it will be present
at specified index. The previous code segfault since it wrongly assumed
that the index will match LWP ID which was incorrect even for a single
thread (where index was 0 and LWP ID was 1).
While fixing that off-by-one error would help for this specific task,
I believe it is better to be explicit in what we are searching for.
Differential Revision: https://reviews.llvm.org/D63791
llvm-svn: 364780
Michal Gorny [Mon, 1 Jul 2019 15:11:04 +0000 (15:11 +0000)]
[lldb] [Process/NetBSD] Support reading YMM registers via PT_*XSTATE
Provide a (conditional) support for the new PT_GETXSTATE
and PT_SETXSTATE ptrace() requests, and use them to implement getting
and setting YMM registers. The functions used for splitting
and recombining YMM register data are based on matching functions
in FreeBSD plugin, with some simplification and updates to match NetBSD
structures.
Differential Revision: https://reviews.llvm.org/D63545
llvm-svn: 364779
Diana Picus [Mon, 1 Jul 2019 15:07:38 +0000 (15:07 +0000)]
Fixup r364512
Fix stack-use-after-scope errors from r364512. One instance was already
fixed in r364611 - this patch simplifies that fix and addresses one more
instance of similar code.
Discussed in: https://reviews.llvm.org/D63905
llvm-svn: 364778
Sam Elliott [Mon, 1 Jul 2019 14:53:56 +0000 (14:53 +0000)]
[RISCV] Avoid save-restore target feature warning
Summary:
LLVM issues a warning if passed unknown target features. Neither I nor
@asb noticed this until after https://reviews.llvm.org/D63498 landed.
This patch stops passing the (unknown) "save-restore" target feature to
the LLVM backend, but continues to emit a warning if a driver asks for
`-msave-restore`. The default of assuming `-mno-save-restore` (and
emitting no warnings) remains.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, cfe-commits, asb
Tags: #clang
Differential Revision: https://reviews.llvm.org/D64008
llvm-svn: 364777
Michal Gorny [Mon, 1 Jul 2019 14:38:47 +0000 (14:38 +0000)]
Revert "[lldb] [Process/NetBSD] Fix constructor after r363707"
Now that r364751 has been reverted, we need to revert this fixup
as well.
llvm-svn: 364776
Jinsong Ji [Mon, 1 Jul 2019 14:37:48 +0000 (14:37 +0000)]
[UpdateTestChecks][PowerPC] Avoid empty string when scrubbing loop comments
Summary:
SCRUB_LOOP_COMMENT_RE was introduced in https://reviews.llvm.org/D31285
This works for some loops.
However, we may generate lines with loop comments only.
And since we don't scrub leading white spaces, this will leave an empty
line there, and FileCheck will complain it.
eg: llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll:27:15:
error: found empty check string with prefix 'CHECK:'
; CHECK-NEXT:
This prevented us from using the `update_llc_test_checks.py` for quite some cases.
We should still keep the comment token there, so that we can safely
scrub the loop comment without breaking FileCheck.
Reviewers: timshen, hfinkel, lebedev.ri, RKSimon
Subscribers: nemanjai, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63957
llvm-svn: 364775
Benjamin Kramer [Mon, 1 Jul 2019 14:33:26 +0000 (14:33 +0000)]
[ASTImporter] Silence unused variable warning in Release builds. NFC.
llvm-svn: 364774
Jan Kratochvil [Mon, 1 Jul 2019 14:31:26 +0000 (14:31 +0000)]
Fix lookup of symbols at the same address with no size vs. size
This fixes a failing testcase on Fedora 30 x86_64 (regression Fedora 29->30):
PASS:
./bin/lldb ./lldb-test-build.noindex/functionalities/unwind/noreturn/TestNoreturnUnwind.test_dwarf/a.out -o 'settings set symbols.enable-external-lookup false' -o r -o bt -o quit
* frame #0: 0x00007ffff7aa6e75 libc.so.6`__GI_raise + 325
frame #1: 0x00007ffff7a91895 libc.so.6`__GI_abort + 295
frame #2: 0x0000000000401140 a.out`func_c at main.c:12:2
frame #3: 0x000000000040113a a.out`func_b at main.c:18:2
frame #4: 0x0000000000401134 a.out`func_a at main.c:26:2
frame #5: 0x000000000040112e a.out`main(argc=<unavailable>, argv=<unavailable>) at main.c:32:2
frame #6: 0x00007ffff7a92f33 libc.so.6`__libc_start_main + 243
frame #7: 0x000000000040106e a.out`_start + 46
vs.
FAIL - unrecognized abort() function:
./bin/lldb ./lldb-test-build.noindex/functionalities/unwind/noreturn/TestNoreturnUnwind.test_dwarf/a.out -o 'settings set symbols.enable-external-lookup false' -o r -o bt -o quit
* frame #0: 0x00007ffff7aa6e75 libc.so.6`.annobin_raise.c + 325
frame #1: 0x00007ffff7a91895 libc.so.6`.annobin_loadmsgcat.c_end.unlikely + 295
frame #2: 0x0000000000401140 a.out`func_c at main.c:12:2
frame #3: 0x000000000040113a a.out`func_b at main.c:18:2
frame #4: 0x0000000000401134 a.out`func_a at main.c:26:2
frame #5: 0x000000000040112e a.out`main(argc=<unavailable>, argv=<unavailable>) at main.c:32:2
frame #6: 0x00007ffff7a92f33 libc.so.6`.annobin_libc_start.c + 243
frame #7: 0x000000000040106e a.out`.annobin_init.c.hot + 46
The extra ELF symbols are there due to Annobin (I did not investigate why this problem happened specifically since F-30 and not since F-28).
It is due to:
Symbol table '.dynsym' contains 2361 entries:
Valu e Size Type Bind Vis Name
0000000000022769 5 FUNC LOCAL DEFAULT _nl_load_domain.cold
000000000002276e 0 NOTYPE LOCAL HIDDEN .annobin_abort.c.unlikely
...
000000000002276e 0 NOTYPE LOCAL HIDDEN .annobin_loadmsgcat.c_end.unlikely
...
000000000002276e 0 NOTYPE LOCAL HIDDEN .annobin_textdomain.c_end.unlikely
000000000002276e 548 FUNC GLOBAL DEFAULT abort
000000000002276e 548 FUNC GLOBAL DEFAULT abort@@GLIBC_2.2.5
000000000002276e 548 FUNC LOCAL DEFAULT __GI_abort
0000000000022992 0 NOTYPE LOCAL HIDDEN .annobin_abort.c_end.unlikely
Differential Revision: https://reviews.llvm.org/D63540
llvm-svn: 364773
Roman Lebedev [Mon, 1 Jul 2019 14:28:24 +0000 (14:28 +0000)]
[NFC][InstCombine] Better commutative tests for "shift amount reassociation in bittest" pattern.
As discussed in https://reviews.llvm.org/D63829
*if* *both* shifts are one-use, we'd most likely want to produce `lshr`,
and not rely on ordering.
Also, there should likely be a *separate* fold to do this reordering.
llvm-svn: 364772
Gabor Marton [Mon, 1 Jul 2019 14:19:53 +0000 (14:19 +0000)]
[ASTImporter] Mark erroneous nodes in from ctx
Summary:
During import of a specific Decl D, it may happen that some AST nodes
had already been created before we recognize an error. In this case we
signal back the error to the caller, but the "to" context remains
polluted with those nodes which had been created. Ideally, those nodes
should not had been created, but that time we did not know about the
error, the error happened later. Since the AST is immutable (most of
the cases we can't remove existing nodes) we choose to mark these nodes
as erroneous.
Here are the steps of the algorithm:
1) We keep track of the nodes which we visit during the import of D: See
ImportPathTy.
2) If a Decl is already imported and it is already on the import path
(we have a cycle) then we copy/store the relevant part of the import
path. We store these cycles for each Decl.
3) When we recognize an error during the import of D then we set up this
error to all Decls in the stored cycles for D and we clear the stored
cycles.
Reviewers: a_sidorin, a.sidorin, shafik
Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D62375
llvm-svn: 364771
Krzysztof Parzyszek [Mon, 1 Jul 2019 13:50:47 +0000 (13:50 +0000)]
[Hexagon] Rework VLCR algorithm
Add code to catch pattern for commutative instructions for VLCR.
Patch by Suyog Sarda.
llvm-svn: 364770
Matt Arsenault [Mon, 1 Jul 2019 13:44:46 +0000 (13:44 +0000)]
AMDGPU: Convert some places to Register
llvm-svn: 364769
Matt Arsenault [Mon, 1 Jul 2019 13:40:18 +0000 (13:40 +0000)]
AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE
llvm-svn: 364768
Matt Arsenault [Mon, 1 Jul 2019 13:40:17 +0000 (13:40 +0000)]
AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR
llvm-svn: 364767
Matt Arsenault [Mon, 1 Jul 2019 13:37:39 +0000 (13:37 +0000)]
AMDGPU/GlobalISel: Fail on store to 32-bit address space
llvm-svn: 364766
Matt Arsenault [Mon, 1 Jul 2019 13:34:26 +0000 (13:34 +0000)]
AMDGPU/GlobalISel: Improve icmp selection coverage.
Select s64 eq/ne scalar icmp.
llvm-svn: 364765
Roman Lebedev [Mon, 1 Jul 2019 13:31:06 +0000 (13:31 +0000)]
[NFC][InstCombine] Improve test coverage for ((~x) + y) + 1 -> y - x fold fold (PR42459)
So we indeed to have this fold, but only if +1 is not the last operation..
llvm-svn: 364764