Kazu Hirata [Thu, 22 Dec 2022 00:15:09 +0000 (16:15 -0800)]
[mlir] Fix a warning
This patch fixes:
mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp:33:12:
error: variable 'foundDynamicDim' set but not used
[-Werror,-Wunused-but-set-variable]
Roman Lebedev [Thu, 22 Dec 2022 00:12:17 +0000 (03:12 +0300)]
[NFC][SROA] More tests for variable indexed promotion
Kazu Hirata [Thu, 22 Dec 2022 00:10:28 +0000 (16:10 -0800)]
[mlir] Fix a warning
This patch fixes:
mlir/include/mlir/Analysis/AliasAnalysis/LocalAliasAnalysis.h:24:7:
error: 'mlir::LocalAliasAnalysis' has virtual functions but
non-virtual destructor [-Werror,-Wnon-virtual-dtor]
Michael Jones [Wed, 21 Dec 2022 23:22:27 +0000 (15:22 -0800)]
[libc][obvious] fix bazel after removing vector
The vector class was removed from the source code and cmake but not from
the bazel which caused bazel issues. This patch fixes that.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D140510
LLVM GN Syncbot [Wed, 21 Dec 2022 23:32:10 +0000 (23:32 +0000)]
[gn build] Port
ec11388b3342
Nico Weber [Wed, 21 Dec 2022 23:31:39 +0000 (18:31 -0500)]
[gn] another fixup for
47df55f3ef5 -- LoongArch is experimental, not RISCV
Nico Weber [Wed, 21 Dec 2022 23:25:45 +0000 (18:25 -0500)]
[gn] fixup for
47df55f3ef5
Nico Weber [Wed, 21 Dec 2022 23:23:47 +0000 (18:23 -0500)]
[gn] Don't include RISCV in targets build for 'all'
RISCV build and tests are often broken.
You can use `llvm_targets_to_build = "experimental"` to enable
_all_ targets, including the experimental ones. If RISCV is listed
in llvm_targets_to_build, it's built as before.
Nilay Vaish [Wed, 21 Dec 2022 22:54:25 +0000 (14:54 -0800)]
[NFC] test commit
Heejin Ahn [Thu, 15 Dec 2022 21:58:51 +0000 (13:58 -0800)]
[LiveDebugValues] Remove LexicalScope param from VarLoc (NFC)
It doesn't seem to be used anymore.
Reviewed By: dschuff
Differential Revision: https://reviews.llvm.org/D140258
Matt Arsenault [Thu, 8 Dec 2022 03:48:27 +0000 (22:48 -0500)]
clang: Add __builtin_elementwise canonicalize and copysign
Just copy paste from the other functions. I also need fma, but
the current code seems to assume 1 or 2 arguments.
Jacques Pienaar [Wed, 21 Dec 2022 22:53:12 +0000 (14:53 -0800)]
Revert "[mlir][py] Enable building ops with raw inputs"
Reverting to fix build bot.
This reverts commit
3781b7905d8d808e5d4e97d597263f8ac48541b8.
Roman Lebedev [Wed, 21 Dec 2022 22:35:23 +0000 (01:35 +0300)]
[NFC][SROA] More tests for variable indexed promotion
Sam McCall [Wed, 21 Dec 2022 18:16:14 +0000 (19:16 +0100)]
[clangd] Fix crashing race in ClangdServer shutdown with stdlib indexing
In principle it's OK for stdlib-indexing tasks to run after the TUScheduler is
destroyed, as mostly they just update the dynamic index. We do drain the
stdlib-indexing queue before destroying the index.
However the task captures references to the PreambleCallbacks object, which is
owned by the TUScheduler. Once this is destroyed (explicitly, early in
~ClangdServer) an outstanding stdlib-indexing task may use-after-free.
The fix here is to avoid capturing references to the PreambleCallbacks.
Alternatives would be to have TUScheduler (exclusively) not own its callbacks
so they could live longer, or explicitly stopping the TUScheduler instead of
early-destroying it. These both seem more invasive.
See https://reviews.llvm.org/D115232 for some more context.
Differential Revision: https://reviews.llvm.org/D140486
Jez Ng [Wed, 21 Dec 2022 22:26:02 +0000 (17:26 -0500)]
[lld-macho] Emit map file entries for more synthetic sections
We now handle the GOT, TLV, and stubs/lazy pointer sections.
Reviewed By: #lld-macho, thevinster, thakis
Differential Revision: https://reviews.llvm.org/D139762
Matt Arsenault [Wed, 21 Dec 2022 22:24:59 +0000 (17:24 -0500)]
LoongArch: Update for MachineFunctionInfo construction change
Roman Lebedev [Wed, 21 Dec 2022 21:59:56 +0000 (00:59 +0300)]
[NFC][SROA] More tests for promotion with variable index
Also, delete the InstCombine test, it's not going to be relevant.
Florian Hahn [Wed, 21 Dec 2022 22:02:31 +0000 (22:02 +0000)]
[LV] Add createTripCountSCEV helper (NFC).
Split off helper function in preparation for D135017.
Michal Paszkowski [Wed, 21 Dec 2022 21:51:59 +0000 (22:51 +0100)]
[SPIR-V] Add atomic_flag builtin implementation
This change provides implementation details for atomic_flag builtins and
adds an extended atomic_flag.ll test from the LLVM SPIR-V Translator.
Differential Revision: https://reviews.llvm.org/D136310
Roman Lebedev [Wed, 21 Dec 2022 21:08:16 +0000 (00:08 +0300)]
Reland "[NFC][SROA] `speculateSelectInstLoads()`: play nice with typed pointers for now"
This reverts commit
bf88ba0f8718c1e89e28e977839ad0a6186d44fe,
relands
9f27f4536e19e93349b0662338408efe6d1cb2fd, but without a bug:
we *REALLY* should not be defaulting to address space 0
when address space is not specified...
Nick Desaulniers [Wed, 21 Dec 2022 21:11:36 +0000 (13:11 -0800)]
[llvm][SelectionDAGISel] support -{start|stop}-{before|after}= for remaining targets
Follow up to the series:
1. https://reviews.llvm.org/D140161
2. https://reviews.llvm.org/D140349
3. https://reviews.llvm.org/D140331
4. https://reviews.llvm.org/D140323
Completes the work from the previous two for remaining targets.
This creates the following named passes that can be run via
`llc -{start|stop}-{before|after}`:
- arc-isel
- arm-isel
- avr-isel
- bpf-isel
- csky-isel
- hexagon-isel
- lanai-isel
- loongarch-isel
- m68k-isel
- msp430-isel
- mips-isel
- nvptx-isel
- ppc-codegen
- riscv-isel
- sparc-isel
- systemz-isel
- ve-isel
- wasm-isel
- xcore-isel
A nice way to write tests for SelectionDAGISel might be to use a RUN:
line like:
llc -mtriple=<triple> -start-before=<arch>-isel -stop-after=finalize-isel -o -
Fixes: https://github.com/llvm/llvm-project/issues/59538
Reviewed By: asb, zixuan-wu
Differential Revision: https://reviews.llvm.org/D140364
Sylvain Audi [Thu, 15 Dec 2022 15:56:47 +0000 (10:56 -0500)]
[lld][COFF] Fix lld-link crash when several .obj files built with /Zi refer to a .pdb file that failed to load
This patch relaxes the constraints on the error message saved in PDBInputFile when failing to load a pdb file.
Storing an `Error` member infers that it must be accessed exactly once, which doesn't fit in several scenarios:
- If an invalid PDB file is provided as input file but never used, a loading error is created but never handled, causing an assert at shutdown.
- PDB file created using MSVC's `/Zi` option : The loading error message must be displayed once per obj file.
Also, the state of `PDBInputFile` was altered when reading (taking) the `Error` member, causing issues:
- accessing it (taking the `Error`) makes the object look valid whereas it's not properly initialized
- read vs write concurrency on a same `PDBInputFile` in the ghash parallel algorithm
The solution adopted here was to instead store an optional error string, and generate Error objects from it on demand.
Differential Revision: https://reviews.llvm.org/D140333
Siva Chandra Reddy [Wed, 21 Dec 2022 21:10:42 +0000 (21:10 +0000)]
[libc][Obvious] Fix an off-by-one error introduced by
eb9cc253cb048b6dbf2fcd73ac55b5eda0184ed3.
Nick Desaulniers [Wed, 21 Dec 2022 20:28:37 +0000 (12:28 -0800)]
[llvm][AArch64ISelDAGToDAG] support -{start|stop}-{before|after}=aarch64-isel
Follow a similar pattern as AMDGPUDAGToDAGISel's constructor so that we
can use INITIALIZE_PASS to register a pass. This allows for more fine
grain testability of SelectionDAGISel via:
llc -stop-{before,after}=aarch64-isel
Link: https://github.com/llvm/llvm-project/issues/59538
See also: https://reviews.llvm.org/D140323
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D140331
Siva Chandra Reddy [Wed, 21 Dec 2022 07:27:08 +0000 (07:27 +0000)]
[libc] Gracefully handle allocation failures around BlockStore.
Reviewed By: lntue
Differential Revision: https://reviews.llvm.org/D140459
Siva Chandra Reddy [Wed, 21 Dec 2022 07:36:23 +0000 (07:36 +0000)]
[libc][NFC] Use the custom operator new from strndup.
Reviewed By: lntue
Differential Revision: https://reviews.llvm.org/D140461
Craig Topper [Wed, 21 Dec 2022 20:50:10 +0000 (12:50 -0800)]
[RISCV] Check the sign bits of the input of RISCVISD::ABSW in computeNumSignBitsForTargetNode.
We created a SIGN_EXTEND_INREG when we created the ABSW so the
input should have 33 sign bits, but check it to be safe.
Craig Topper [Wed, 21 Dec 2022 20:08:07 +0000 (12:08 -0800)]
[RISCV] Add test cases for i8/i16 abs followed by zext.
The andi, zext.h and slli+srli shift pairs at the end of the generated
output are unnecessary if the input is sign extended.
Nick Desaulniers [Wed, 21 Dec 2022 20:22:22 +0000 (12:22 -0800)]
sort some method declarations. NFC
Precommit sort and format of methods from D140331.
Link: https://reviews.llvm.org/D140331
Link: https://github.com/llvm/llvm-project/issues/59538
Roman Lebedev [Wed, 21 Dec 2022 20:13:17 +0000 (23:13 +0300)]
[NFC][SROA] Add tests for alloca promotion in presence of variably-indexed load
Xiang Li [Mon, 12 Dec 2022 17:51:33 +0000 (12:51 -0500)]
[DIrectX backend] emit metadata for entry.
New named metadata "dx.entryPoints" is added to save all entries.
Each entry is in format of
!{ptr to function, name, signature, resource table, extra}
For compute shader, the extra will save num of threads in format of {i32 x, i32 y, i32 z}
For library profile, an empty entry will be added to save the resource table for the library.
Signature and resource table metadata is not generated yet.
Differential Revision: https://reviews.llvm.org/D131807
Jacques Pienaar [Wed, 21 Dec 2022 19:43:03 +0000 (11:43 -0800)]
[mlir] Clear running passes in crashreporter
Clear active contexts and running passes whenever finalizing crash
report message. Ran into segfault where a failure in dynamic pipeline
resulted in querying a pass whose passmanager had already been destroyed
come time for creating summary of running passes. Conservatively clear
both running states as I don't think there is recovery intended from
pass pipeline failure.
Additionally restrict to one reproducer per report - else we end up
clobbering the same reproducer file over and over again. So instead of
ending with last reproducer we now end up with the first reproducer
while not creating and clobbering reproducers over and over again.
Differential Revision: https://reviews.llvm.org/D140488
Peter Steinfeld [Fri, 16 Dec 2022 20:05:16 +0000 (12:05 -0800)]
[Flang] Reword the overview document
I brought the overview document up to date and added information for
most compilation phases to dump out the reeults of the phase.
Differential Revision: https://reviews.llvm.org/D140241
Saleem Abdulrasool [Wed, 21 Dec 2022 16:45:28 +0000 (16:45 +0000)]
Headers: further refine the `stdatomic.h` MSVC inclusion
The `stdatomic.h` header cannot be included under MSVC when in C++ mode
as the toolsets prior to 17.5.0 Preview 2 do not support the C11
atomics. However, some toolsets prior to the aforementioned version
support the atomics under the C++ mode. In these versions the MSVC
toolset protects against the contamination by entirely eliding the
declarations, resulting in build failures in some cases. Unfortunately,
e0c3142af075e2ef89395dbed5939071345eb622 accidentally regressed the C
case when fixing the C++ support.
Unfortunately, we cannot test this reliably as we need to inject a
header after the resource path as a system header path, which we do not
have a reliable means of doing.
Fixes: #59640
Mingming Liu [Tue, 20 Dec 2022 21:53:34 +0000 (13:53 -0800)]
[AArch64] Guard {vmull_p64, vmull_high_p64} with 'aes' target guard.
The 'aes' target guard includes both FEAT_AES and FEAT_PMULL currently.
In this way, cpp code that uses these intrinsics without specifying the required extension gets better hint.
- Before, compile crashes with LLVM ISel internal message (see issue [[ https://github.com/llvm/llvm-project/issues/59599 | 59599 ]]).
- After, clang hints that target 'aes' is required in the command.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D140432
Craig Topper [Wed, 21 Dec 2022 18:39:41 +0000 (10:39 -0800)]
[RISCV] Add DAG combine to fold (select C, (add X, Y), Y) -> (add (select C, X, 0), Y).
Similar for sub, or, and xor. These are all operations that have 0
as a neutral value. This is based on a similar tranform in InstCombine.
This allows us to remove some XVentanaCondOps patterns and
some code from DAGCombine for RISCVISD::SELECT_CC.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D140465
Shafik Yaghmour [Wed, 21 Dec 2022 18:47:52 +0000 (10:47 -0800)]
[Clang] Modify sanity check assert in AggExprEmitter::VisitInitListExpr to cover anonymous struct in a union GNU extension
AggExprEmitter::VisitInitListExpr sanity checks that an empty union is really
empty and not a semantic analysis failure. The assert is missing that we allow
anonymous structs as a GNU extension. I have updated the assert to take that into account.
This fixes: https://github.com/llvm/llvm-project/issues/58800
Differential Revision: https://reviews.llvm.org/D139261
Amir Ayupov [Wed, 21 Dec 2022 18:09:46 +0000 (10:09 -0800)]
[BOLT][NFC] Make DWOId std::optional
Reviewed By: #bolt, ayermolo
Differential Revision: https://reviews.llvm.org/D140450
Craig Topper [Wed, 21 Dec 2022 18:20:59 +0000 (10:20 -0800)]
[RISCV] Add more test cases to select.ll. NFC
These are test for select (and (x , 0x1) == 0), (z ^ y), y ) and select (and (x , 0x1) == 0), (z | y), y )
These can be made branchless by using ((x-1) & z ) ^ y.
Fangrui Song [Wed, 21 Dec 2022 18:35:05 +0000 (10:35 -0800)]
[ARC] Fix build after createMachineFunctionInfo change
69e75ae695d9ef1360a2a1fbefd6e0e0456c3f7b
David Green [Wed, 21 Dec 2022 18:32:52 +0000 (18:32 +0000)]
[AArch64] Additional RSHRN pattern tests. NFC
Michał Górny [Sun, 4 Dec 2022 06:39:41 +0000 (07:39 +0100)]
[libc++] Rename __tuple to __tuple_dir to avoid file collision
Rename the `__tuple` directory in libc++ headers to `__tuple_dir`
to avoid file collision when installing. Historically, `__tuple` has
been a file and it has been replaced by a directory
in
2d52c6bfae801b016dd3627b8c0e7c4a99405549. Replacing a regular file
with a directory (or more importantly, the other way around when
downgrading) is not universally supported. Since this is an internal
header, its actual name should not matter, so just rename it to avoid
problems.
Differential Revision: https://reviews.llvm.org/D139270
Jacques Pienaar [Wed, 21 Dec 2022 18:10:31 +0000 (10:10 -0800)]
[mlir][py] Enable building ops with raw inputs
For cases where we can automatically construct the Attribute allow for more
user-friendly input. This is consistent with C++ builder generation as well
choice of which single builder to generate here (most
specialized/user-friendly).
Registration of attribute builders from more pythonic input is all Python side.
The downside is that
* extra checking to see if user provided a custom builder in op builders,
* the ODS attribute name is load bearing
upside is that
* easily change these/register dialect specific ones in downstream projects,
* adding support/changing to different convenience builders are all along with
the rest of the convenience functions in Python (and no additional changes
to tablegen file or recompilation needed);
Allow for both building with Attributes as well as raw inputs. This change
should therefore be backwards compatible as well as allow for avoiding
recreating Attribute where already available.
Differential Revision: https://reviews.llvm.org/D139568
Slava Zakharin [Wed, 21 Dec 2022 01:13:25 +0000 (17:13 -0800)]
[flang] Use Assign() runtime for copy-in/copy-out.
The loops generated under IsContiguous check for copy-in/copy-out
result in LLVM backend spending too much time optimizing them.
At the same time, the copy loops do not provide any optimization
opportunities with the surrounding code (since they are executed
under runtime IsContiguous check), so the copy code may be optimized
on its own and this can be done in runtime.
I thought I could implement and use new APIs for packing/unpacking
non-contiguous data (interfaces added in D136378), but then I found
that Assign() is already doing what is needed. If performance
becomes an issue for these loops, we can optimize code in Assign()
rather than creating new APIs.
Thus, this change makes use of Assign() for copy-in/copy-out
of boxed objects, and this is done only if the objects
are non-contiguous during execution. Copies for non-boxed
objects (e.g. for passing as VALUE dummy argument) are still
done inline, because they can potentially be optimized with
surrounding loops.
I added internal -inline-copyinout-for-boxes option to revert to the old
behavior just to make it easier to triage performance regressions,
if any appear after the change.
CPU2017/521.wrf compiles for 2179 seconds without the change and
the module_dm.f90 compiled with -O0 (without -O0 this single
module compiles for 5775 seconds). With the change total compilation
time of the benchmark reduces to 722 seconds.
Differential Revision: https://reviews.llvm.org/D140446
Jacques Pienaar [Wed, 21 Dec 2022 17:49:18 +0000 (09:49 -0800)]
[mlir] Fix SameOperandsAndResultType to check encoding.
Encoding was accidentally left out here even though it forms part of the type.
This is small tightening step and I'll look at follow on to tighten more.
Differential Revision: https://reviews.llvm.org/D140445
Ramkumar Ramachandra [Tue, 13 Dec 2022 16:43:36 +0000 (17:43 +0100)]
mlir/LinalgOps: fix name of generated .yamlgen in comments
Signed-off-by: Ramkumar Ramachandra <r@artagnon.com>
Differential Revision: https://reviews.llvm.org/D139946
Paul Robinson [Wed, 21 Dec 2022 17:36:36 +0000 (09:36 -0800)]
[Driver] Fix tests not to fail randomly on Windows
These used a regex that didn't guard against backslashes, so
getting "lucky" with a temp dir name could make them fail.
Mitch Phillips [Wed, 21 Dec 2022 17:18:01 +0000 (09:18 -0800)]
Revert "BEGIN_PUBLIC"
This reverts commit
a6d6d40d8bd062514fc379a6bf70fb1b7220be6f.
Reason: Broke the ASan/MSan bots. More information in phabricator:
https://reviews.llvm.org/D140406
Ed Maste [Tue, 20 Dec 2022 20:21:11 +0000 (15:21 -0500)]
[libc++] Add FreeBSD ABI list
Generated via `nina generate-cxx-abilist`.
Reviewed By: Mordante, ldionne, philnik
Differential Revision: https://reviews.llvm.org/D140431
Mark de Wever [Thu, 1 Dec 2022 17:56:40 +0000 (18:56 +0100)]
[NFC][libc++][chrono] Improves test coverage.
The function year_month_weekday::sys_days should work properly with a
weekday index of 0 per [time.cal.ymwd.members]/20. This adds a test for
this case.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D139126
Jeremy Morse [Wed, 21 Dec 2022 16:42:34 +0000 (16:42 +0000)]
[NFC] Add --check-globals to an autogen test cmdline
In
c6d7e80ec4c17 this test was converted from hand written to autogenerated,
during which the relevant metadata CHECKs were dropped. In D85172 the intention
of the CHECK lines is to ensure that for two dbg.declares with different
inlining scopes, attached to the same alloca, two sets of dbg.values will be
generated with the same set of inlining scopes. Without metadata checks, a
single DILocation can match the !dbg CHECKs.
Paul Robinson [Wed, 21 Dec 2022 16:41:38 +0000 (08:41 -0800)]
[docs] Update an example
Paul Robinson [Wed, 21 Dec 2022 15:09:35 +0000 (07:09 -0800)]
[docs] Add tips on writing test constraints
Mark de Wever [Tue, 20 Dec 2022 17:02:36 +0000 (18:02 +0100)]
[libc++] Adds __cpp_lib_constexpr_algorithms to utility.
Implements:
- LWG3792 __cpp_lib_constexpr_algorithms should also be defined in <utility>
Depends on D140407
Reviewed By: #libc, philnik, ldionne
Differential Revision: https://reviews.llvm.org/D140413
Mark de Wever [Tue, 20 Dec 2022 06:59:11 +0000 (07:59 +0100)]
[libc++][doc] Adds Kona plenary papers and issues.
Directly marked entries with Nothing to do where applicable.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D140407
Alan Zhao [Mon, 19 Dec 2022 18:04:06 +0000 (10:04 -0800)]
[clang] Remove overly restrictive aggregate paren init logic
Previously, we would only attempt to perform a parenthesized aggregate
initialization if constructor initialization failed for only the default
constructor, default copy constructor, and default move constructor. The
original intent of this logic was to reject initializing objects that
have failed resolving a user-defined constructor. However, this check is
redundant because we check for isAggregate() before attempting to
perform a parenthesized aggregate initialization, and classes that have
user-defined or user-declared constructors are not aggregates.
Furthermore, this check is too restrictive - the following valid
examples fail:
* Aggregate class with user-defined destructor - fails because default
move constructors are not generated for classes with user-defined
destructors
(https://github.com/llvm/llvm-project/issues/54040#issuecomment-
1356926048)
* Concept-guarded conversion operator on an aggregate's member:
(https://github.com/llvm/llvm-project/issues/54040#issuecomment-
1356931745)
The solution therefore is to remove this logic; existing tests still
pass, and the previously failing examples now compile.
Reviewed By: ilya-biryukov
Differential Revision: https://reviews.llvm.org/D140327
Paul Walker [Mon, 17 Oct 2022 13:45:09 +0000 (14:45 +0100)]
[InstCombine] Bubble vector.reverse of binop operands to their result.
This mirrors a similar shufflevector transformation so the same
effect is obtained for scalable vectors. The transformation is
only performed when it can be proven the number of resulting
reversals is not increased. By bubbling the reversals from operand
to result this should typically be the case and ideally leads to
back-back shuffles that can be elimitated entirely.
Differential Revision: https://reviews.llvm.org/D139342
Paul Walker [Mon, 17 Oct 2022 13:45:09 +0000 (14:45 +0100)]
[InstCombine] Bubble vector.reverse of select operands to their result.
This mirrors a similar shufflevector transformation so the same
effect is obtained for scalable vectors. The transformation is
only performed when it can be proven the number of resulting
reversals is not increased. By bubbling the reversals from operand
to result this should typically be the case and ideally leads to
back-back shuffles that can be elimitated entirely.
Differential Revision: https://reviews.llvm.org/D139339
Paul Walker [Mon, 17 Oct 2022 13:45:09 +0000 (14:45 +0100)]
[InstCombine] Bubble vector.reverse of compare operands to their result.
This mirrors a similar shufflevector transformation so the same
effect is obtained for scalable vectors. The transformation is
only performed when it can be proven the number of resulting
reversals is not increased. By bubbling the reversals from operand
to result this should typically be the case and ideally leads to
back-back shuffles that can be elimitated entirely.
Differential Revision: https://reviews.llvm.org/D139340
Matt Arsenault [Wed, 21 Dec 2022 15:46:23 +0000 (10:46 -0500)]
llvm-reduce: Remove test dependence on registered targets
This reverts
e4b126cc2d33033a5538d72a88f6aa153ac8b757 and
e57ab8fe91f06e71d3de2df07e6c7efd2f0c6078.
This previously depended on where the target happened to construct (or
not) the MachineFunctionInfo during the initial MIR construction. Now
that the MachineFunctionInfo is consistently constructed at
MachineFunction construction time, this should always work.
Matt Arsenault [Thu, 18 Jun 2020 13:00:16 +0000 (09:00 -0400)]
CodeGen: Don't lazily construct MachineFunctionInfo
This fixes what I consider to be an API flaw I've tripped over
multiple times. The point this is constructed isn't well defined, so
depending on where this is first called, you can conclude different
information based on the MachineFunction. For example, the AMDGPU
implementation inspected the MachineFrameInfo on construction for the
stack objects and if the frame has calls. This kind of worked in
SelectionDAG which visited all allocas up front, but broke in
GlobalISel which hasn't visited any of the IR when arguments are
lowered.
I've run into similar problems before with the MIR parser and trying
to make use of other MachineFunction fields, so I think it's best to
just categorically disallow dependency on the MachineFunction state in
the constructor and to always construct this at the same time as the
MachineFunction itself.
A missing feature I still could use is a way to access an custom
analysis pass on the IR here.
Lei Huang [Tue, 20 Dec 2022 16:11:55 +0000 (10:11 -0600)]
[PowerPC] Implement P10 Byte Reverse Insructions
Generate brh, brw and brd instructions for byte-swap operations
on P10 and generating a single instruction for a 32-bit swap followed
by a 16-bit right shift.
Reviewed By: stefanp
Differential Revision: https://reviews.llvm.org/D140414
David Green [Wed, 21 Dec 2022 14:59:59 +0000 (14:59 +0000)]
[AArch64] Combine Trunc(DUP) -> DUP
This adds a simple fold of TRUNCATE(AArch64ISD::DUP) -> AArch64ISD::DUP,
which can help generate more optimal UMULL sequences, and seems useful
in general.
Differential Revision: https://reviews.llvm.org/D140289
Nikita Popov [Wed, 21 Dec 2022 14:41:54 +0000 (15:41 +0100)]
[InstCombine] Recursively replace select value equivalence
In the X == C ? f(X) : Y -> X == C ? f(C) : Y fold, perform the
replacement in f(X) recursively. For now, this just goes two
instructions up rather than one instruction up.
luxufan [Wed, 21 Dec 2022 14:47:12 +0000 (22:47 +0800)]
[InstCombine] Combine ZExt (B - A) + ZExt(A) to ZExt(B)
Combine ZExt (B - A) + ZExt(A) to ZExt(B)
https://alive2.llvm.org/ce/z/ESUwPi
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D139930
Florian Hahn [Wed, 21 Dec 2022 14:36:24 +0000 (14:36 +0000)]
[LV] Move SCEV caching workaround to executePlan (NFC).
As suggested by @Ayal in D92132.
This avoids having to duplicate the workaround in multiple places.
Nikita Popov [Wed, 21 Dec 2022 14:46:51 +0000 (15:46 +0100)]
[InstCombine] Add additional tests for select value equivalence fold (NFC)
Nikolas Klauser [Tue, 20 Dec 2022 19:21:31 +0000 (20:21 +0100)]
[libc++] Also install libclang in the Docker image
This is now everything that is required for clang-tidy checks.
Reviewed By: #libc, ldionne
Spies: libcxx-commits, arichardson
Differential Revision: https://reviews.llvm.org/D140424
Matt Arsenault [Tue, 20 Dec 2022 13:20:28 +0000 (08:20 -0500)]
SCCPSolver: Remove unnecessary set empty check
Hans Wennborg [Wed, 21 Dec 2022 14:21:04 +0000 (15:21 +0100)]
Revert "Reland "[pgo] Avoid introducing relocations by using private alias""
This caused lld on mac to assert when building instrumented clang (or
instrumented code in general). See comment on the code review for
reproducer.
> In many cases, we can use an alias to avoid a symbolic relocations,
> instead of using the public, interposable symbol. When the instrumented
> function is in a COMDAT, we can use a hidden alias, and still avoid
> references to discarded sections.
>
> New compiler-rt tests are Linux only for now.
>
> Previous versions of this patch allowed the compiler to name the
> generated alias, but that would only be valid when the functions were
> local. Since the alias may be used across TUs we use a more
> deterministic naming convention, and add a `.local` suffix to the alias
> name just as we do for relative vtables aliases.
>
> Reviewed By: phosek
>
> Differential Revision: https://reviews.llvm.org/D137982
This reverts commit
c42e50fede53bbcce79095e7c8115f26826c81ae.
Mirko Brkusanin [Wed, 21 Dec 2022 14:05:30 +0000 (15:05 +0100)]
[AMDGPU][GlobalISel] Fix mapping G_FREEZE
Differential Revision: https://reviews.llvm.org/D140416
Peter Waller [Mon, 12 Dec 2022 15:49:58 +0000 (15:49 +0000)]
[AArch64][SVE][CodeGen] Prefer ld1r* over indexed-load when consumed by a splat
If a load is consumed by a single splat, don't consider indexed loads.
This is an alternative implementation to D138581.
Depends on D139637.
Differential Revision: https://reviews.llvm.org/D139850
Alexey Bataev [Tue, 13 Dec 2022 20:45:16 +0000 (12:45 -0800)]
[SLP]Integrate looking through shuffles logic into ShuffleInstructionBuilder.
Added BaseShuffleAnalysis as a base class for ShuffleInstructionBuilder
and integrated shuffle logic from shuffles for externally used scalars
into this class. This class is used as the main container that
implements smart shuffle instruction builder logic.
ShuffleInstructionBuilder uses this logic.
ShuffleInstructionBuilder is also used in building of the shuffle for
the externally used scalars instead of lambdas, which are now part of BaseShuffleAnalysis class.
Differential Revision: https://reviews.llvm.org/D140100
Paul Robinson [Mon, 12 Dec 2022 19:51:41 +0000 (11:51 -0800)]
[lit] Document the 'target=<triple>' feature
Differential Revision: https://reviews.llvm.org/D139869
Florian Hahn [Wed, 21 Dec 2022 13:58:50 +0000 (13:58 +0000)]
[LV] Support widened induction variables in epilogue vectorization.
Code generation now uses the start VPValue of induction recipes.
This makes it possible to adjust the start value of the epilogue
vector loop to use the 'resume' value of the main vector loop.
Fixes #59459.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D92132
Yingchi Long [Sat, 10 Dec 2022 15:03:26 +0000 (23:03 +0800)]
[JT] check xor operand is exactly the same in processBranchOnXOR
Reproducer:
; RUN: opt -S -jump-threading < %s
define void @test() {
entry:
br i1 false, label %loop, label %exit
loop:
%bool = phi i1 [ %xor, %loop.latch ], [ false, %entry ]
%cmp = icmp eq i16 0, 1
%xor = xor i1 %cmp, %bool
br i1 %bool, label %loop.latch, label %exit
loop.latch:
%dummy = phi i16 [ 0, %loop ]
br label %loop
exit:
ret void
}
On this occassion, phi node %bool is actually %xor, and doing substitution causes assertion failure.
Fixes: https://github.com/llvm/llvm-project/issues/58812
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D139783
Paul Robinson [Wed, 21 Dec 2022 13:41:00 +0000 (05:41 -0800)]
[hwasan] Convert tests to check 'target=...'
Part of the project to eliminate special handling for triples in lit
expressions.
Aliia Khasanova [Wed, 21 Dec 2022 13:37:25 +0000 (14:37 +0100)]
BEGIN_PUBLIC
Add a shortened printing/parsing form for linalg.map and linalg.reduce.
END_PUBLIC
Differential Revision: https://reviews.llvm.org/D140406
Paul Robinson [Wed, 21 Dec 2022 13:31:38 +0000 (05:31 -0800)]
[compiler-rt] Simplify lit test thumb checks
Matt Arsenault [Wed, 21 Dec 2022 13:09:56 +0000 (08:09 -0500)]
clang: Respect function address space for __builtin_function_start
Fixes assertion.
Matt Arsenault [Wed, 21 Dec 2022 12:57:49 +0000 (07:57 -0500)]
clang: Fix another assert from not respecting function address spaces
Matt Arsenault [Wed, 21 Dec 2022 12:33:18 +0000 (07:33 -0500)]
clang: Use correct address space for redeclared functions
Fixes assert/verifier error with AVR.
Florian Hahn [Wed, 21 Dec 2022 13:23:25 +0000 (13:23 +0000)]
[LV] Add test for #59459.
Paul Robinson [Wed, 21 Dec 2022 13:22:10 +0000 (05:22 -0800)]
[libcxxabi] Use 'target=' consistently
Paul Robinson [Wed, 21 Dec 2022 13:17:56 +0000 (05:17 -0800)]
[clang/xray] Convert tests to check 'target=...'
Part of the project to eliminate special handling for triples in lit
expressions.
Ivan Butygin [Mon, 19 Dec 2022 21:26:07 +0000 (22:26 +0100)]
[mlir] Make `LocalAliasAnalysis` extesible
This is an alternative to https://reviews.llvm.org/D138761 . Instead of adding ad-hoc attributes to existing `LocalAliasAnalysis`, expose `aliasImpl` method so user can override it.
Differential Revision: https://reviews.llvm.org/D140348
Alexey Lapshin [Fri, 23 Sep 2022 06:34:26 +0000 (09:34 +0300)]
[DWARFv4][DWARFv5][DWARFLinker] support debug_macinfo/debug_macro tables.
This patch adds handling of debug_macinfo/debug_macro tables to the DWARFLinker.
It uses already existing code for reading tables from DWARFDebugMacro.h.
It adds new code writing tables into the DwarfStreamer::emitMacroTables.
Differential Revision: https://reviews.llvm.org/D140223
Ben Shi [Tue, 13 Dec 2022 04:07:40 +0000 (12:07 +0800)]
[clang] Do not extend i8 return values to i16 on AVR.
Reviewed By: Miss_Grape, aykevl
Differential Revision: https://reviews.llvm.org/D139908
Evgenii Kudriashov [Wed, 21 Dec 2022 11:58:25 +0000 (19:58 +0800)]
[X86] combine-and.ll - add 256 and 512 bit test coverage for scalar broadcast
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D139991
Matthias Springer [Wed, 21 Dec 2022 11:39:19 +0000 (12:39 +0100)]
[mlir][bufferize] Fix tensor copy insertion for dynamic tensors
TensorCopyInsertion inserts bufferization.alloc_tensor ops in case of RaW conflicts. If such a tensor is dynamically shaped, tensor.dim ops are inserted. There is an optimization for ops such as tensor.extract_slice: A copy of the result is created instead of the operand. Afterwards, all uses of the result are updated. E.g.:
```
%0 = tensor.extract_slice ... : tensor<?xf32> to tensor<?xf32>
%1 = tensor.dim %0, %c0 : tensor<?xf32>
%2 = bufferization.alloc_tensor(%dim) : tensor<?xf32>
```
All uses of %0, except for tensor.dim and bufferization.alloc_tensor (if any), should be replaced. Before this change, the use in tensor.dim was also replaced, resulting in IR that had a dominance error.
Note: There is no test case for this fix because the bug cannot be triggered with tensor.extract_slice, which implements an interface to reify result shapes. This bug appeared in an external project with a tensor.extract_slice-like op that does not implement that interface, in which case tensor.dim ops must be created. We do not have such an op in MLIR to trigger this bug.
Differential Revision: https://reviews.llvm.org/D140471
Nikita Popov [Wed, 21 Dec 2022 11:36:15 +0000 (12:36 +0100)]
[ARM] Convert some tests to opaque pointers (NFC)
Nikita Popov [Wed, 21 Dec 2022 11:32:56 +0000 (12:32 +0100)]
[ARM] Regenerate test checks (NFC)
Ties Stuij [Wed, 21 Dec 2022 11:08:55 +0000 (11:08 +0000)]
[AArch64] GlobalIsel codegen for gpr CTZ
If feature CSSC is available, CTTZ intrinsics are lowered using the CTZ
instruction when using GlobalIsel.
spec:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/CTZ--Count-Trailing-Zeros-
Reviewed By: paquette
Differential Revision: https://reviews.llvm.org/D139418
Elena Lepilkina [Wed, 14 Dec 2022 15:37:44 +0000 (18:37 +0300)]
[RISCV] Omit SRA in case of setlt or setge with zero constant
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D140206
Elena Lepilkina [Fri, 16 Dec 2022 06:49:11 +0000 (09:49 +0300)]
[Precommit][RISCV] Test folding for RISCVISD::BR_CC node
Precommit test for https://reviews.llvm.org/D140206
bipmis [Wed, 21 Dec 2022 11:14:45 +0000 (11:14 +0000)]
[AAch64] Optimize muls with operands having enough zero bits.
Fix the regression in the reported test case lagarith-preproc.c.
Specfic to the incorrect umsubl generation.
Differential Revision: https://reviews.llvm.org/D139411
Max Kazantsev [Wed, 21 Dec 2022 05:47:36 +0000 (12:47 +0700)]
[SCEV] Help getLoopInvariantExitCondDuringFirstIterations deal with complex `umin` exit counts. PR59615
Recent improvements in symbolic exit count computation revealed some problems with
SCEV's ability to find invariant predicate during first iterations. Ultimately it is based on its
ability to prove some facts for value on the last iteration. This last value, when it includes
`umin` as part of exit count, isn't always simplified enough. The motivating example is following:
https://github.com/llvm/llvm-project/issues/59615
Could not prove:
```
Pred = 36, LHS = (-1 + (-1 * (
2147483645 umin (-1 + %var)<nsw>))<nsw> + %var), RHS = %var
FoundPred = 36, FoundLHS = {1,+,1}<nuw><nsw><%bb3>, FoundRHS = %var
```
Can prove:
```
Pred = 36, LHS = (-1 + (-1 * (-1 + %var)<nsw>)<nsw> + %var), RHS = %var
FoundPred = 36, FoundLHS = {1,+,1}<nuw><nsw><%bb3>, FoundRHS = %var
```
Here ` (
2147483645 umin (-1 + %var)<nsw>)` is exit count composed of two parts from
two different exits: `
2147483645 ` and `(-1 + %var)<nsw>`. When it was only one (latter)
analyzeable exit, for it everything was easily provable. Unfortunately, in general case `umin`
in one of `add`'s operands doesn't guarantee that the whole sum reduces, especially in presence
of negative steps and lack of `nuw`. I don't think there is a generic legal way to somehow play
around this `umin`.
So the ad-hoc solution is following: if we failed to find an equivalent predicate that is invariant
during first `MaxIter` iterations, and `MaxIter = umin(a, b, c...)`, try to find solution for at least one
of `a`, `b`, `c`... Because they all are `uge` than `MaxIter`, whatever is true during `a (b, c)` iterations
is also true during `MaxIter` iterations.
Differential Revision: https://reviews.llvm.org/D140456
Reviewed By: nikic
Ties Stuij [Wed, 21 Dec 2022 10:08:19 +0000 (10:08 +0000)]
[lld][ARM] support absolute thunks for Armv4T Thumb and interworking
changes:
- BLX: The Arm architecture versions that support the branch and link
instruction (BLX), can rewrite BLs in place when a state change from Arm<->Thumb
is required. Armv4T does not have BLX and so needs thunks for state changes.
- v4T Thumb long branches needed their own thunk. We could have used the v6M
implementation, but v6M doesn't have Arm state and must resolve to rather
inefficient stack reshuffling. We also can't reuse v7 thumb thunks as they use
MOVV/MOVT, which wasn't available yet for v4T.
- Remove the `lack of BLX' warning. LLVM only supports Arm Architecture versions
upwards of v4, which we now all support in LLD.
- renamed existing thunks to better reflect their use:
ARMV5ABSLongThunk -> ARMV5LongLdrPcThunk,
ARMV5PILongThunk -> ARMV4PILongThunk
- removed isCompatibleWith method from ARMV5ABSLongThunk and ARMV5PILongThunk,
as they were identical to the ARMThunk parent class implementation.
Support for (efficient) position independent thunks for v4T will be added in a
follow-up patch, including possible related thunk renaming and code comment
cleanup.
Reviewed By: MaskRay, peter.smith
Differential Revision: https://reviews.llvm.org/D139888
Christudasan Devadasan [Wed, 21 Dec 2022 10:41:30 +0000 (16:11 +0530)]
Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"
This reverts commit
40ba0942e2ab1107f83aa5a0ee5ae2980bf47b1a.
Jay Foad [Tue, 20 Dec 2022 17:19:01 +0000 (17:19 +0000)]
[SelectionDAG] Fix EmitCopyFromReg for cloned nodes
Change EmitCopyFromReg to check all users of cloned nodes (as well as
non-cloned nodes) instead of assuming that they all copy the defined
value back to the same physical register.
This partially reverts
968e2e7b3db1 (svn r62356) which claimed:
CreateVirtualRegisters does trivial copy coalescing. If a node def is
used by a single CopyToReg, it reuses the virtual register assigned to
the CopyToReg. This won't work for SDNode that is a clone or is itself
cloned. Disable this optimization for those nodes or it can end up
with non-SSA machine instructions.
This is true for CreateVirtualRegisters but r62356 also updated
EmitCopyFromReg where it is not true. Firstly EmitCopyFromReg only
coalesces physical register copies, so the concern about SSA form does
not apply. Secondly making the loop over users in EmitCopyFromReg
conditional on `!IsClone && !IsCloned` breaks the handling of cloned
nodes, because it leaves MatchReg set to true by default, so it assumes
that all users will copy the defined value back to the same physical
register instead of actually checking.
Differential Revision: https://reviews.llvm.org/D140417