Arnd Bergmann [Tue, 22 Nov 2022 22:02:24 +0000 (23:02 +0100)]
Merge tag 'tegra-for-6.2-arm64-dt-v2' of git://git./linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v6.2-rc1
This contains many new additions, primarily for Tegra234, as well as a
slew of cleanups for issues flagged by the DT validation tools.
* tag 'tegra-for-6.2-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits)
arm64: tegra: Remove unneeded clock-names for Tegra132 PWM
arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234
arm64: tegra: Remove unused reset-names for QSPI
arm64: tegra: Fixup pinmux node names
arm64: tegra: Remove reset-names for QSPI
arm64: tegra: Use correct compatible string for Tegra234 HDA
arm64: tegra: Use correct compatible string for Tegra194 HDA
arm64: tegra: Use vbus-gpios property
arm64: tegra: Restructure Tegra210 PMC pinmux nodes
arm64: tegra: Update cache properties
arm64: tegra: Remove 'enable-active-low'
arm64: tegra: Add dma-channel-mask in GPCDMA node
arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller
arm64: tegra: Add missing compatible string to Ethernet USB device
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
arm64: tegra: Add ECAM aperture info for all the PCIe controllers
arm64: tegra: Remove clock-names from PWM nodes
arm64: tegra: Enable GTE nodes
arm64: tegra: Update console for Jetson Xavier and Orin
arm64: tegra: Enable PWM users on Jetson AGX Orin
...
Link: https://lore.kernel.org/r/20221121171239.2041835-7-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 22 Nov 2022 22:00:52 +0000 (23:00 +0100)]
Merge tag 'tegra-for-6.2-dt-bindings-v2' of git://git./linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v6.2-rc1
New memory client IDs and IOMMU stream IDs, as well as new compatible
strings are introduced to support more hardware on Tegra234. Some device
tree bindings are converted to json-schema to allow formal validation.
* tag 'tegra-for-6.2-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: usb: tegra-xusb: Convert to json-schema
dt-bindings: pwm: tegra: Convert to json-schema
dt-bindings: pinctrl: tegra194: Separate instances
dt-bindings: pinctrl: tegra: Convert to json-schema
dt-bindings: PCI: tegra234: Add ECAM support
dt-bindings: pwm: tegra: Document Tegra234 PWM
dt-bindings: Add bindings for Tegra234 NVDEC
dt-bindings: tegra: Update headers for Tegra234
dt-bindings: Add headers for NVDEC on Tegra234
Link: https://lore.kernel.org/r/20221121171239.2041835-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 22 Nov 2022 22:00:03 +0000 (23:00 +0100)]
Merge tag 'socfpga_dts_updates_for_v6.2' of git://git./linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA dts updates for v6.2
- Use the "clk-phase-sd-hs" property for SDMMC
- Remove the "clk-phase" fom the sdmmc_clk that is no longer used
- Clean dtschema for mmc node
- Increase NAND partition for Arria10
* tag 'socfpga_dts_updates_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
arm: dts: socfpga: remove "clk-phase" in sdmmc_clk
arm: dts: socfpga: align mmc node names with dtschema
ARM: dts: socfpga: arria10: Increase NAND boot partition size
Link: https://lore.kernel.org/r/20221121163259.341974-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 22 Nov 2022 21:57:53 +0000 (22:57 +0100)]
Merge tag 'riscv-dt-for-v6.2-mw0' of https://git./linux/kernel/git/conor/linux into soc/dt
RISC-V DeviceTrees for v6.2
dt-bindings:
- new compatibles to support the StarFive VisionFive & thead CPU cores
- a fix for the PolarFire SoC's pwm binding, merged through my tree as
suggested by the PWM maintainers
Microchip:
- Non-urgent fix for the node address not matches the reg in a way that
the checkers don't complain about
- Add GPIO controlled LEDs for Icicle
- Support for the "CCC" clocks in the FPGA fabric. Previously these
used fixed-frequency clocks in the dt, but if which CCC is in use is
known, as in the v2022.09 Icicle Kit Reference Design, the rates can
be read dynamically. It's an "is known" as it *can* be set via
constraints in the FPGA tooling but does not have to be.
- A fix for the Icicle's pwm-cells
- Removal of some unused PCI clocks
StarFive:
- Addition of the VisionFive DT, which has been a long time coming!
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
riscv: dts: microchip: remove unused pcie clocks
riscv: dts: microchip: remove pcie node from the sev kit
riscv: dts: microchip: fix the icicle's #pwm-cells
dt-bindings: pwm: fix microchip corePWM's pwm-cells
riscv: dts: starfive: Add StarFive VisionFive V1 device tree
riscv: dts: starfive: Add common DT for JH7100 based boards
dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board
riscv: dts: microchip: fix memory node unit address for icicle
riscv: dts: microchip: icicle: Add GPIO controlled LEDs
riscv: dts: microchip: add the mpfs' fabric clock control
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:56:08 +0000 (11:56 +0100)]
Merge tag 'renesas-arm-dt-for-v6.2-tag2' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas ARM DT updates for v6.2 (take two)
- Timer (TMU and CMT) and quad Cortex-A76 CPU topology support for
the R-Car V4H SoC,
- Watchdog, L2 cache, and system controller support for the RZ/V2M
SoC on the RZ/V2M Evaluation Kit 2.0,
- Ethernet Switch and SERDES supports for the R-Car S4-8 SoC and the
Spider development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits)
arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDES
arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
arm64: dts: renesas: r9a09g011: Add system controller node
arm64: dts: renesas: r8a779g0: Add CA76 operating points
arm64: dts: renesas: r8a779g0: Add CPU core clocks
arm64: dts: renesas: r8a779g0: Add CPUIdle support
arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores
arm64: dts: renesas: r8a779g0: Add L3 cache controller
arm64: dts: renesas: r9a09g011: Add L2 Cache node
arm64: dts: renesas: rzv2mevk2: Enable watchdog
arm64: dts: renesas: r9a09g011: Add watchdog node
arm64: dts: renesas: spider-cpu: Switch from SCIF3 to HSCIF0
arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes
arm64: dts: renesas: r9a09g011: Fix I2C SoC specific strings
arm64: dts: renesas: rzg2l: Add missing cache-level properties
arm64: dts: renesas: r8a779g0: Add CMT node
arm64: dts: renesas: r9a09g011: Fix unit address format error
arm64: dts: renesas: white-hawk-cpu: Sort RWDT entry correctly
arm64: dts: renesas: r8a779g0: Add TMU nodes
arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock
...
Link: https://lore.kernel.org/r/cover.1668788921.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:53:45 +0000 (11:53 +0100)]
Merge tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas RISC-V DT updates for v6.2
- Add initial support for the Renesas RZ/Five SoC and the Renesas
RZ/Five SMARC EVK development board.
* tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
MAINTAINERS: Add entry for Renesas RISC-V
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
Link: https://lore.kernel.org/r/cover.1668788930.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:53:09 +0000 (11:53 +0100)]
Merge tag 'renesas-dt-bindings-for-v6.2-tag2' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DT binding updates for v6.2 (take two)
- Document support for the Andes Technology AX45MP RISC-V CPU Core, as
used on the Renesas RZ/Five SoC,
- Document support for the Renesas RZ/V2M System Configuration.
* tag 'renesas-dt-bindings-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
dt-bindings: riscv: Add Andes AX45MP core to the list
dt-bindings: riscv: Sort the CPU core list alphabetically
Link: https://lore.kernel.org/r/cover.1668788927.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:44:13 +0000 (11:44 +0100)]
Merge tag 'stm32-dt-for-v6.2-1' of git://git./linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.2, round 1
Highlights:
----------
- MPU:
- ST boards:
- Add MCP23017 IO expander support on stm32mp135f-dk board.
- Add stm32g0 support for USB typeC on stm32mp135f-dk
- Add USB (EHCI / OTG) on stm32mp135f-dk
- Add ADC support on stm32mp135f-dk
- Add USB2514B onboard hub on stm32mp157c-ev1
- DH:
- Fix severals Yaml DT validation issues
* tag 'stm32-dt-for-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (28 commits)
ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench board
ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk
ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13
ARM: dts: stm32: enable USB OTG in dual role mode on stm32mp135f-dk
ARM: dts: stm32: add pins for stm32g0 typec controller on stm32mp13
ARM: dts: stm32: enable USB Host EHCI on stm32mp135f-dk
ARM: dts: stm32: enable USB HS phys on stm32mp135f-dk
ARM: dts: stm32: add fixed regulators to support usb on stm32mp135f-dk
ARM: dts: stm32: add USB OTG HS support on stm32mp131
ARM: dts: stm32: add UBSH EHCI and OHCI support on stm32mp131
ARM: dts: stm32: add USBPHYC and dual USB HS PHY support on stm32mp131
ARM: dts: stm32: add PWR fixed regulators on stm32mp131
ARM: dts: stm32: Fix AV96 WLAN regulator gpio property
ARM: dts: stm32: add adc support on stm32mp135f-dk
ARM: dts: stm32: add dummy vdd_adc regulator on stm32mp135f-dk
ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk
ARM: dts: stm32: add adc support to stm32mp13
ARM: dts: stm32: Drop MMCI interrupt-names
ARM: dts: stm32: update vbus-supply of usbphyc_port0 on stm32mp157c-ev1
ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp157c-ev1
...
Link: https://lore.kernel.org/r/3235e5be-d89f-f76c-5e25-5d1210feb857@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:43:39 +0000 (11:43 +0100)]
Merge tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi into soc/dt
ARM64: DT: HiSilicon ARM64 DT updates for 6.2
- Add missing cache-level properties
* tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi:
arm64: dts: Update cache properties for hisilicon
Link: https://lore.kernel.org/r/63744D38.9010700@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:40:29 +0000 (11:40 +0100)]
Merge tag 'imx-dt64-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm64 device tree update for 6.2:
- New device trees for i.MX8MM based Cloos PHG and WB15 SoM/EVK.
- A set of tqma8mpql/mba8mpxl changes, adding USB Host, PCIe, PWM fan
support.
- Rename DTB overlay source files from .dts to .dtso.
- A series from Frank Li to add USB, ADC, FlexSPI, LPSPI support for
i.MX8DXL.
- A couple of librem5-devkit changes, switching LED to use PWM and using
function and color properties for LED.
- Enable wakeup-source for USB PHY for i.MX8MM/N EVK.
- A set of random changes from Marcel Ziswiler to improve i.MX8M based
Verdin device trees.
- A series from Marek Vasut to update Data Modul i.MX8M Mini eDM SBC and
DH electronics i.MX8M Plus DHCOM, modeling PMIC to SNVS RTC clock
path, dropping QCA clk_out setup, adding bluetooth UART, etc.
- A bunch of changes from Peng Fan to add LPSPI, TPM etc for i.MX93,
update i.MX8MP/N EVK with UART, I2C addition.
- Update cache properties per DeviceTree Specification v0.3.
- Add gpio-ranges property for i.MX8DXL and i.MX8Q LSIO Subsystem.
- Misc small and random changes.
* tag 'imx-dt64-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (60 commits)
arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtso
arm64: dts: imx8mm-evk: add vcc supply for pca6416
arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator
arm64: dts: imx8mn-evk: enable uart1
arm64: dts: imx8mn-evk: add i2c gpio recovery settings
arm64: dts: imx8mn-evk: set off-on-delay-us in regulator
arm64: dts: imx8mn-evk: update vdd_soc dvs voltage
arm64: dts: imx8mp-evk: enable I2C2 node
arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk
arm64: dts: imx8mp-evk: enable uart1/3 ports
ARM64: dts: imx8mp-evk: add pwm support
arm64: dts: imx8mp: add mlmix power domain
arm64: dts: imx8mq: fix dtschema warning for imx7-csi
arm64: dts: Update cache properties for freescale
arm64: dts: imx8mm-phg: Add initial board support
arm64: dts: imx8qxp-ss-lsio: add gpio-ranges property
arm64: dts: imx8qm-ss-lsio: add gpio-ranges property
arm64: dts: imx8dxl-ss-lsio: add gpio-ranges property
arm64: dts: imx8dxl_evk: add lpspi0 support
arm64: dts: imx8dxl: add lpspi support
...
Link: https://lore.kernel.org/r/20221119125733.32719-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:08:01 +0000 (11:08 +0100)]
Merge tag 'imx-dt-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm device tree update for 6.2:
- New device tree for Kobo Aura 2 E-Boot reader which is built on i.MX6SL
SoC.
- Enable backlight and boost support for imx6sl-tolino-shine2hd.
- Enable CYTTSP5 touchscreen support for E60K02.
- Enable Silergy SY7636A EPD PMIC on imx7d-remarkable2 epaper tablet.
- Add watchdog property 'fsl,suspend-in-wait' for i.MX6UL Phytec Phycore
SoM to avoid watchdog triggering in 'freeze' low power mode.
- Correct the polarity of AT86RF233 reset line for vf610-zii-dev-rev-c
board.
- A bunch of Colibri device tree updates from Marcel Ziswiler and Philippe
Schenker, correct USBH_PEN property, remove spurious debounce property,
add USB dual-role switching, and some cosmetic change.
- Other small and random changes.
* tag 'imx-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: colibri-imx6ull: Enable dual-role switching
ARM: dts: imx: e60k02: Add touchscreen
ARM: dts: imx6qdl-sabre: Add mmc aliases
ARM: dts: imx6ul/ull: suspend i.MX6UL watchdog in wait mode
ARM: dts: imx7d-remarkable2: Enable silergy,sy7636a
ARM: dts: imx6sl-tolino-shine2hd: Add backlight boost
ARM: dts: imx6sl-tolino-shine2hd: Add backlight
ARM: dts: colibri-imx7: fix confusing naming
ARM: dts: colibri-imx6ull: add -hog to gpio hogs
ARM: dts: colibri-imx6ull: enable default peripherals
ARM: dts: colibri-imx6ull: keep peripherals disabled
ARM: dts: ls1021: correct indentation
ARM: dts: vf610-zii-dev-rev-c: fix polarity of at86rf233 reset line
ARM: dts: imx7-colibri: remove spurious debounce property
ARM: dts: colibri-imx6: specify usbh_pen gpio being active-low
ARM: dts: colibri-imx6: move vbus-supply to module level device tree
ARM: dts: colibri-imx6: usb dual-role switching
ARM: dts: imx: Add devicetree for Kobo Aura 2
Link: https://lore.kernel.org/r/20221119125733.32719-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:06:42 +0000 (11:06 +0100)]
Merge tag 'imx-bindings-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX dt-bindings update for 6.2:
- New vendor prefix for Cloos and InnoComm.
- New compatible for Cloos PHG board, InnoComm WB15 EVK and Kobo Aura 2.
- Improve snvs-lpgpr bindings schema regarding i.MX8M SNVS LPGRP
compatible strings.
- Improve fsl-imx-cspi bindings schema for i.MX8MP ECSPI.
- Add bindings schema for i.MX8M ANATOP device.
- Update SCU firmware resource ID header by syncing with the latest
available SCFW kit version 1.13.0.
* tag 'imx-bindings-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: arm: fsl: Add an entry for Cloos PHG board
dt-bindings: vendor-prefixes: Add an entry for Cloos
dt-bindings: nvmem: snvs-lpgpr: Fix i.MX8M compatible strings
dt-bindings: spi: fsl-imx-cspi: update i.MX8MP binding
dt-bindings: arm: fsl: add compatible string for Kobo Aura 2
dt-bindings: clock: add i.MX8M Anatop
dt-bindings: arm: fsl: Add InnoComm WB15 EVK
dt-bindings: vendor-prefixes: Add prefix for InnoComm
dt-bindings: firmware: imx: sync with SCFW kit v1.13.0
Link: https://lore.kernel.org/r/20221119125733.32719-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Thierry Reding [Thu, 17 Nov 2022 08:32:41 +0000 (09:32 +0100)]
arm64: tegra: Remove unneeded clock-names for Tegra132 PWM
There's only a single clock for this IP block, so it doesn't need a
clock-names property.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 12:38:34 +0000 (13:38 +0100)]
arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234
The compatible string list for SDHCI on Tegra234 should be
"nvidia,tegra234-sdhci", followed by the "nvidia,tegra186-sdhci"
fallback. Use that consistently for all SDHCI controllers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 12:35:57 +0000 (13:35 +0100)]
arm64: tegra: Remove unused reset-names for QSPI
The Tegra QSPI controller uses a single reset line, so there's no need
for a reset-names property. Remove such properties.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 12:35:08 +0000 (13:35 +0100)]
arm64: tegra: Fixup pinmux node names
Pinmux node names should have a pinmux- prefix and not use underscores.
Fix up some cases that didn't follow those rules.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 5 Sep 2022 16:08:55 +0000 (18:08 +0200)]
arm64: tegra: Remove reset-names for QSPI
The Tegra QSPI controllers use a single reset control, so reset-names is
not necessary and therefore not specified in the DT bindings. Drop the
property from device tree files to avoid validation warnings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 13:14:16 +0000 (14:14 +0100)]
arm64: tegra: Use correct compatible string for Tegra234 HDA
The Tegra234 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 13:11:04 +0000 (14:11 +0100)]
arm64: tegra: Use correct compatible string for Tegra194 HDA
The Tegra194 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 13:10:17 +0000 (14:10 +0100)]
arm64: tegra: Use vbus-gpios property
Instead of using the deprecated vbus-gpio property, switch to using the
more standard vbus-gpios property.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 14:03:41 +0000 (15:03 +0100)]
arm64: tegra: Restructure Tegra210 PMC pinmux nodes
The PMC pinmux configuration nodes need to be part of a top-level pinmux
node. Add that new "pinmux" node and move the configuration nodes into
it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Pierre Gondois [Mon, 7 Nov 2022 15:57:08 +0000 (16:57 +0100)]
arm64: tegra: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Fabio Estevam [Mon, 19 Sep 2022 10:43:50 +0000 (07:43 -0300)]
arm64: tegra: Remove 'enable-active-low'
The 'enable-active-low' property is not a valid one.
Only 'enable-active-high' is valid, and when this property is absent
the gpio regulator will act as active low by default.
Remove the invalid 'enable-active-low' property.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Akhil R [Thu, 10 Nov 2022 17:17:47 +0000 (22:47 +0530)]
arm64: tegra: Add dma-channel-mask in GPCDMA node
Add dma-channel-mask property in Tegra GPCDMA device tree node.
The property would help to specify the channels to be used in
kernel and reserve few for the firmware. This was previously
achieved by limiting the channel number to 31 in the driver.
This is wrong and does not align with the hardware. Correct this
and update the interrupts property to list all 32 interrupts.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Vidya Sagar [Tue, 25 Oct 2022 18:25:08 +0000 (23:55 +0530)]
arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller
Fix the starting address of the non-prefetchable aperture of PCIe C3
controller.
Fixes:
ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Thu, 3 Nov 2022 11:35:48 +0000 (12:35 +0100)]
arm64: tegra: Add missing compatible string to Ethernet USB device
According to the DT schema in usb-device.yaml, each USB device node
needs a compatible string, so add one for the built-in USB Ethernet
device on Jetson TX1.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 14:23:45 +0000 (15:23 +0100)]
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
The registers for the AON pinmux reside in a partition different from
the registers for the main pinmux. Instead of treating them as one and
the same device, split them up so that they are each their own devices.
Also add gpio-ranges properties to the corresponding GPIO controllers
such that the pinmux and GPIO controllers can be paired up properly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Vidya Sagar [Mon, 14 Nov 2022 15:53:33 +0000 (15:53 +0000)]
arm64: tegra: Add ECAM aperture info for all the PCIe controllers
Add the ECAM aperture information for all the PCIe controllers of
Tegra234.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 11:43:49 +0000 (12:43 +0100)]
arm64: tegra: Remove clock-names from PWM nodes
The Tegra PWFM controllers use a single clock, so there's no need for a
clock-names property.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dipen Patel [Thu, 3 Nov 2022 17:45:22 +0000 (10:45 -0700)]
arm64: tegra: Enable GTE nodes
Add and enable AON and LIC GTE nodes by default.
Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Fri, 28 Oct 2022 12:35:56 +0000 (13:35 +0100)]
arm64: tegra: Update console for Jetson Xavier and Orin
The Tegra Combined UART (TCU) is the default serial interface for Jetson
Xavier and Orin platforms and so update the bootargs for these platforms
to use the TCU.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sandipan Patra [Mon, 19 Sep 2022 14:14:55 +0000 (19:44 +0530)]
arm64: tegra: Enable PWM users on Jetson AGX Orin
Enable additional PWM controllers in device tree so that the PWM pins on
the Jetson AGX Orin Developer Kit 40-pin header can be used.
Signed-off-by: Sandipan Patra <spatra@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 24 Oct 2022 14:05:57 +0000 (16:05 +0200)]
arm64: tegra: Add missing whitespace
The unit-address of a node should be separated from the opening brace by
a space.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 24 Oct 2022 14:05:16 +0000 (16:05 +0200)]
arm64: tegra: Sort nodes by unit-address
The P2U nodes that were recently added were not added in the correct
order. Sort them in the right place by unit-address.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Prathamesh Shete [Fri, 7 Oct 2022 16:59:41 +0000 (22:29 +0530)]
arm64: tegra: Add Tegra234 SDMMC1 device tree node
Add device tree node for Tegra234 SDMMC1 instance.
Add and enable SD card instance in device tree.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 19 Oct 2022 14:47:00 +0000 (15:47 +0100)]
arm64: tegra: Add SBSA UART for Tegra234
Populate the SBSA UART for Tegra234 and enable this UART for Jetson AGX
Orin.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 19 Oct 2022 13:29:03 +0000 (14:29 +0100)]
arm64: tegra: Add PWM fan for Jetson AGX Orin
Add the PWM fan node for the Tegra234 Jetson AGX Orin platform.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 19 Oct 2022 13:29:02 +0000 (14:29 +0100)]
arm64: tegra: Populate Tegra234 PWMs
Populate all the PWM devices for Tegra234. Finally, update the
compatible string for the existing 'pwm1' node to just be 'tegra194-pwm'
and remove the fallback to 'tegra186-pwm', which aligns with the
binding documentation.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 19 Oct 2022 13:16:13 +0000 (14:16 +0100)]
arm64: tegra: Remove unused property for I2C
Commit
156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes")
populated the I2C device nodes for Tegra234. One of these nodes
contains the property 'nvidia,hw-instance-id' which is neither
documented or used. Remove this unused property.
Fixes:
156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Vidya Sagar [Wed, 28 Sep 2022 06:27:31 +0000 (11:57 +0530)]
arm64: tegra: Fix Prefetchable aperture ranges of Tegra234 PCIe controllers
commit
edf408b946d3 ("PCI: dwc: Validate iATU outbound mappings against
hardware constraints") exposes an issue with the existing partitioning of
the aperture space where the Prefetchable apertures of controllers
C5, C7 and C9 in Tegra234 cross the 32GB boundary hardware constraint.
This patch makes sure that the Prefetchable region doesn't spill over
the 32GB boundary.
Fixes:
ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Tue, 20 Sep 2022 08:11:59 +0000 (11:11 +0300)]
arm64: tegra: Add NVDEC on Tegra234
Add a device tree node for NVDEC on Tegra234.
Booting the firmware requires some information regarding offsets
within the firmware binary. These are passed through the device
tree, but since the values vary depending on the firmware version,
and the firmware itself is not available to the OS, the flasher is
expected to provide a device tree overlay with values corresponding
to the firmware it is flashing. The overlay then replaces the
placeholder values here.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Tue, 6 Sep 2022 11:01:34 +0000 (14:01 +0300)]
arm64: tegra: Fix ranges for host1x nodes
The currently specified 'ranges' properties don't actually include
all devices under the host1x bus on Tegra194 and Tegra234. Expand
them appropriately.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 21 Nov 2022 12:29:45 +0000 (13:29 +0100)]
Merge branch for-6.2/dt-bindings into for-6.2/arm64/dt
Thierry Reding [Mon, 22 Nov 2021 16:23:26 +0000 (17:23 +0100)]
dt-bindings: usb: tegra-xusb: Convert to json-schema
Convert the Tegra XUSB controller bindings from the free-form text
format to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Thu, 17 Nov 2022 21:42:48 +0000 (22:42 +0100)]
dt-bindings: pwm: tegra: Convert to json-schema
Convert the Tegra PWFM bindings from the free-form text format to
json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 1 Jul 2022 14:52:24 +0000 (16:52 +0200)]
dt-bindings: pinctrl: tegra194: Separate instances
Tegra194 has two separate instances of the pin controller, one called
AON (in the always-on domain) and another called "main". Instead of
treating them as a single pin controller, split them up into two
separate controllers. Doing so allows the mapping between the pinmux and
GPIO controllers to be trivial identity mappings and more cleanly
separates the AON from the main IP blocks.
Note that while this changes the DT node in an incompatible way, this
doesn't have any practical implications for backwards-compatibility. The
reason for this is that device trees have only reconfigured a very
narrow subset of pins of the main controller, so the new driver will
remain backwards-compatible with old device trees.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 22 Nov 2021 12:28:40 +0000 (13:28 +0100)]
dt-bindings: pinctrl: tegra: Convert to json-schema
Convert the NVIDIA Tegra pinmux controller bindings from the free-form
text format to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Vidya Sagar [Mon, 14 Nov 2022 15:53:32 +0000 (15:53 +0000)]
dt-bindings: PCI: tegra234: Add ECAM support
Add support for ECAM aperture that is only supported for Tegra234
devices.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Co-developed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sandipan Patra [Mon, 19 Sep 2022 14:14:53 +0000 (19:44 +0530)]
dt-bindings: pwm: tegra: Document Tegra234 PWM
Add compatible for nvidia,tegra234-pwm with nvidia,tegra194-pwm as a
fallback. The PWM controller blocks are identical to the ones found on
the Tegra194 SoC. No driver changes are required and compatible string
"nvidia,tegra194-pwm" will be used as a fallback.
Signed-off-by: Sandipan Patra <spatra@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Tue, 20 Sep 2022 08:11:58 +0000 (11:11 +0300)]
dt-bindings: Add bindings for Tegra234 NVDEC
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware from a secure carveout configured by
the bootloader.
For the latter, we need to add a phandle to the memory controller
to query the location of this carveout, and several other properties
containing offsets into the firmware inside the carveout. This
carveout is not accessible by the CPU, but is needed by NVDEC,
so we need this information to be relayed from the bootloader.
As the binding was getting large with many conditional properties,
also split the Tegra234 version out into a separate file.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Mon, 3 Oct 2022 12:51:41 +0000 (13:51 +0100)]
dt-bindings: tegra: Update headers for Tegra234
Update the device-tree clock, memory, power and reset headers for
Tegra234 by adding the definitions for all the various devices.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Arnd Bergmann [Mon, 21 Nov 2022 10:01:48 +0000 (11:01 +0100)]
Merge branch 'dt/dtbo-rename' of git://git./linux/kernel/git/robh/linux into soc/dt
* 'dt/dtbo-rename' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
kbuild: Cleanup DT Overlay intermediate files as appropriate
staging: pi433: overlay: Rename overlay source file from .dts to .dtso
of: overlay: rename overlay source files from .dts to .dtso
kbuild: Allow DTB overlays to built into .dtbo.S files
kbuild: Allow DTB overlays to built from .dtso named source files
Link: https://lore.kernel.org/r/20221118211103.GA1334449-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 09:57:29 +0000 (10:57 +0100)]
Merge tag 'sunxi-dt-for-6.2-1' of https://git./linux/kernel/git/sunxi/linux into soc/dt
- Added H616 USB node
- Enabled bluetooth on Pinebook A64
- Added f1c100s PWM, I2C, CIR and LRADC nodes
- Added USB HCI0 PHYs property to H3/H5
* tag 'sunxi-dt-for-6.2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0
ARM: dts: suniv: f1c100s: add LRADC node
ARM: dts: suniv: f1c100s: add CIR DT node
dt-bindings: media: IR: Add F1C100s IR compatible string
ARM: dts: suniv: f1c100s: add I2C DT nodes
ARM: dts: suniv: f1c100s: add PWM node
dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
arm64: dts: allwinner: a64: enable Bluetooth on Pinebook
arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
arm64: dts: allwinner: h616: Add USB nodes
dt-bindings: usb: Add H616 compatible string
ARM: dts: axp22x/axp809: Add GPIO controller nodes
ARM: dts: axp803/axp81x: Drop GPIO LDO pinctrl nodes
Link: https://lore.kernel.org/r/Y3fuAosinWbrj+Dy@jernej-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 09:56:43 +0000 (10:56 +0100)]
Merge tag 'at91-dt-6.2-2' of https://git./linux/kernel/git/at91/linux into soc/dt
AT91 DT for 6.2 #2
It contains:
- one typo fix for a SAMA7G5 pin; the pin is not used anywhere in the
device trees.
* tag 'at91-dt-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sama7g5: fix signal name of pin PD8
Link: https://lore.kernel.org/r/20221118131214.301678-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kunihiko Hayashi [Thu, 17 Nov 2022 16:32:19 +0000 (01:32 +0900)]
ARM: dts: uniphier: Add Pro5 board support
Initial version of devicetree sources for Pro5 EPCORE and ProEX boards.
These boards have UART, I2C, USB, eMMC and PCI endpoint in common.
Pro5 EPCORE board is a kind of Pro5 reference board with PCIe endpoint
card edge connector.
ProEX board shares peripherals with Linux and other systems, and some
of these ports are available in Linux.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221117163219.3673-3-hayashi.kunihiko@socionext.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kunihiko Hayashi [Thu, 17 Nov 2022 16:32:18 +0000 (01:32 +0900)]
dt-bindings: arm: uniphier: Add Pro5 boards
Add compatible string for Pro5 EP-Core board and ProEX board support.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221117163219.3673-2-hayashi.kunihiko@socionext.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 09:53:52 +0000 (10:53 +0100)]
Merge tag 'samsung-dt64-6.2' of https://git./linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.2
Correct pin drive strength macros (names) and values used on Tesla FSD
SoC.
* tag 'samsung-dt64-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: fsd: fix drive strength values as per FSD HW UM
arm64: dts: fsd: fix drive strength macros as per FSD HW UM
Link: https://lore.kernel.org/r/20221116093010.18515-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Aakarsh Jain [Wed, 16 Nov 2022 09:30:09 +0000 (10:30 +0100)]
ARM: dts: exynos: Add new SoC specific compatible string for Exynos3250 SoC
Exynos3250 and Exynos5420 are using same compatible string for MFC codec
device but they have different clock hierarchy and complexity. Add new
compatible string followed by mfc-v7 fallback for Exynos3250 SoC.
Suggested-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Aakarsh Jain <aakarsh.jain@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Link: https://lore.kernel.org/r/20221114115024.69591-4-aakarsh.jain@samsung.com
Link: https://lore.kernel.org/r/20221116093010.18515-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Conor Dooley [Sun, 20 Nov 2022 11:12:13 +0000 (11:12 +0000)]
Merge branch 'riscv-thead_c9xx' into riscv-dt-for-next
The bouffalolabs stuff is going to need the thead,c906 compatible too,
so there is no point waiting the D1 stuff to land for it.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Samuel Holland [Mon, 15 Aug 2022 05:08:05 +0000 (00:08 -0500)]
dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C906 core is used in the Allwinner D1 SoC.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Andrew Davis [Mon, 24 Oct 2022 17:34:31 +0000 (12:34 -0500)]
arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtso
DTB Overlays (.dtbo) can now be built from source files with the
extension (.dtso). This makes it clear what is the content of the files
and differentiates them from base DTB source files.
Convert the DTB overlay source files in the arm64/freescale directory.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shawn Guo [Sat, 19 Nov 2022 06:29:30 +0000 (14:29 +0800)]
Merge remote-tracking branch 'robh/dt/dtbo-rename' into imx/dt64
Adrian Alonso [Thu, 17 Nov 2022 09:54:03 +0000 (17:54 +0800)]
arm64: dts: imx8mm-evk: add vcc supply for pca6416
pca6146 requires vcc-supply to work on i.MX8MM-EVK board.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Haibo Chen [Thu, 17 Nov 2022 09:54:02 +0000 (17:54 +0800)]
arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator
Some SD Card controller and power circuitry has increased capacitance,
so the usual toggling of regulator to power the card off and on
is insufficient.
According to SD spec, for sd card power reset operation, the sd card
supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
next time power back the sd card supply voltage to 3.3v, sd card can't
support SD3.0 mode again.
This patch add the off-on-delay-us, make sure the sd power reset behavior
is align with the specification. Without this patch, when do quick system
suspend/resume test, some sd card can't work at SD3.0 mode after system
resume back.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:54:01 +0000 (17:54 +0800)]
arm64: dts: imx8mn-evk: enable uart1
Enable uart1 for BT usage
Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:54:00 +0000 (17:54 +0800)]
arm64: dts: imx8mn-evk: add i2c gpio recovery settings
Add I2C gpio recovery iomuxc settings
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:59 +0000 (17:53 +0800)]
arm64: dts: imx8mn-evk: set off-on-delay-us in regulator
Some SD Card controller and power circuitry has increased capacitance,
so the usual toggling of regulator to power the card off and on
is insufficient.
According to SD spec, for sd card power reset operation, the sd card
supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
next time power back the sd card supply voltage to 3.3v, sd card can't
support SD3.0 mode again.
This patch add the off-on-delay-us, make sure the sd power reset behavior
is align with the specification. Without this patch, when do quick system
suspend/resume test, some sd card can't work at SD3.0 mode after system
resume back.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:58 +0000 (17:53 +0800)]
arm64: dts: imx8mn-evk: update vdd_soc dvs voltage
Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The nxp,dvs-run-voltage
and nxp,dvs-standby-voltage need set for BUCK1, not BUCK2.
BUCK2 is for A53, which is handled by DVFS, so no need dvs property.
nxp,dvs-run-voltage is not needed, since bootloader must configure
voltage to make system boot well.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:57 +0000 (17:53 +0800)]
arm64: dts: imx8mp-evk: enable I2C2 node
Enable I2C node for i.MX8MP-EVK
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Han Xu [Thu, 17 Nov 2022 09:53:56 +0000 (17:53 +0800)]
arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk
enable fspi nor on imx8mp evk dts
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:55 +0000 (17:53 +0800)]
arm64: dts: imx8mp-evk: enable uart1/3 ports
Enable uart1/3 ports for evk board.
Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Clark Wang [Thu, 17 Nov 2022 09:53:54 +0000 (17:53 +0800)]
ARM64: dts: imx8mp-evk: add pwm support
Enable pwm1/2/4 support.
Enable pwm1 on pin GPIO1_IO01 for DSI_BL_PWM
pwm2 on pin GPIO1_IO11 for LVDS_BL_PWM
pwm4 on pin SAI5_RXFS for J21-32
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Thu, 17 Nov 2022 09:53:52 +0000 (17:53 +0800)]
arm64: dts: imx8mp: add mlmix power domain
Add mlmix power domain
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Philippe Schenker [Tue, 15 Nov 2022 18:05:54 +0000 (19:05 +0100)]
ARM: dts: colibri-imx6ull: Enable dual-role switching
The Colibri standard provides a GPIO called USBC_DET to switch from
USB Host to USB Device and back. Make use of this GPIO by adding it
with usb-connector framework.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Martin Kepplinger [Fri, 9 Sep 2022 08:39:40 +0000 (10:39 +0200)]
arm64: dts: imx8mq: fix dtschema warning for imx7-csi
According to dtschema for the csi bridge, compatible is an enum and
only one must be used. Fixing this removes the following warning:
compatible: 'oneOf' conditional failed, one must be fixed
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Andrew Davis [Mon, 14 Nov 2022 20:59:39 +0000 (14:59 -0600)]
kbuild: Cleanup DT Overlay intermediate files as appropriate
%.dtbo.o and %.dtbo.S files are used to build-in DT Overlay. They should
should not be removed by Make or the kernel will be needlessly rebuilt.
These should be removed by "clean" and ignored by git like other
intermediate files.
Reported-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Fixes:
941214a512d8 ("kbuild: Allow DTB overlays to built into .dtbo.S files")
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Masahiro Yamada <masahiroy@kernel.org>
Link: https://lore.kernel.org/r/20221114205939.27994-1-afd@ti.com
Signed-off-by: Rob Herring <robh@kernel.org>
Dinh Nguyen [Fri, 16 Sep 2022 01:45:37 +0000 (20:45 -0500)]
arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh Nguyen [Mon, 3 Oct 2022 18:26:50 +0000 (13:26 -0500)]
arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh Nguyen [Tue, 4 Oct 2022 17:53:28 +0000 (12:53 -0500)]
arm: dts: socfpga: remove "clk-phase" in sdmmc_clk
Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't
need the clk-phase in the sdmmc_clk anymore.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh Nguyen [Thu, 20 Oct 2022 17:44:21 +0000 (12:44 -0500)]
arm: dts: socfpga: align mmc node names with dtschema
dwmmc0@
ff704000: $nodename:0: 'dwmmc0@
ff704000' does not match '^mmc(@.*)?$'
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Yoshihiro Shimoda [Fri, 18 Nov 2022 12:09:52 +0000 (21:09 +0900)]
arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDES
Enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221118120953.1186392-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yoshihiro Shimoda [Fri, 18 Nov 2022 12:09:51 +0000 (21:09 +0900)]
arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221118120953.1186392-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Tue, 15 Nov 2022 10:51:35 +0000 (10:51 +0000)]
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
Enable CANFD and I2C on RZ/Five SMARC EVK.
Note, these blocks are enabled in RZ/G2UL SMARC EVK DTSI [0] hence
deleting these disabled nodes from RZ/Five SMARC EVK DTSI enables them
here too as we include [0] in RZ/Five SMARC EVK DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221115105135.1180490-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Tue, 15 Nov 2022 10:51:34 +0000 (10:51 +0000)]
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM:
- ADC
- OPP
- Thermal Zones
- TSU
Note, these blocks are enabled in RZ/G2UL SMARC SoM DTSI [0] hence
deleting these disabled nodes from RZ/Five SMARC SoM DTSI enables them
here too as we include [0] in RZ/Five SMARC SoM DTSI.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Biju Das [Wed, 16 Nov 2022 10:21:40 +0000 (10:21 +0000)]
arm64: dts: renesas: r9a09g011: Add system controller node
Add system controller node to RZ/V2M SoC dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221116102140.852889-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:04 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add CA76 operating points
Add operating points for running the Cortex-A76 CPU cores on R-Car V4H
at various speeds, up to the Normal (1.7 GHz) performance mode.
Based on a patch in the BSP by Tho Vu.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/8afb32f5dc123ebf2b941703483152ff0992191d.1668429870.git.geert+renesas@glider.be
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:03 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add CPU core clocks
Describe the clocks for the four Cortex-A76 CPU cores.
CA76 Sub-Systems 0/1 (both clusters / all CPU cores) are clocked by Z0φ.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/aa6e9ae21e451ebd40d54d986bd0296571128d5b.1668429870.git.geert+renesas@glider.be
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:02 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add CPUIdle support
Support CPUIdle for ARM Cortex-A76 on R-Car V4H.
Based on patches in the BSP by Tho Vu and Vincent Bryce.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f6d4076983eb45cf23595a045747f28cbdcdf4e6.1668429870.git.geert+renesas@glider.be
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:01 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores
Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4H (R8A779G0) SoC, including CPU
topology and PSCI support for enabling CPU cores.
R-Car V4H has 4 Cortex-A76 cores, grouped in 2 clusters.
Based on a patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ccb55458bd87f8ba70d28c61bcc254f22184824c.1668429870.git.geert+renesas@glider.be
Geert Uytterhoeven [Mon, 14 Nov 2022 12:49:00 +0000 (13:49 +0100)]
arm64: dts: renesas: r8a779g0: Add L3 cache controller
Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.
Extracted from a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
Conor Dooley [Tue, 15 Nov 2022 15:25:47 +0000 (15:25 +0000)]
riscv: dts: microchip: remove unused pcie clocks
The PCIe root port in the designs that ship with the PolarBerry and
M100PFSEVP are connected via one, not two Fabric Interface Controllers
(FIC). The one at 0x20_0000_0000 is fic0, so remove the fic1 clocks from
the dt node.
The same clock provides both, so this is harmless but inaccurate.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Conor Dooley [Tue, 15 Nov 2022 15:25:46 +0000 (15:25 +0000)]
riscv: dts: microchip: remove pcie node from the sev kit
The SEV kit reference design does not hook up the PCIe root port to the
core complex including it is misleading.
The entry is a re-use mistake - I was not aware of this when I moved
the PCIe node out of mpfs.dtsi so that individual bistreams could
connect it to different fics etc.
The node is disabled, so there should be no functional change here.
Fixes:
978a17d1a688 ("riscv: dts: microchip: add sevkit device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Phil Edworthy [Wed, 16 Nov 2022 10:21:38 +0000 (10:21 +0000)]
dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
Add DT binding documentation for System Configuration (SYS) found on
RZ/V2M SoC's.
SYS block contains the SYS_VERSION register which can be used to retrieve
SoC version information.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221116102140.852889-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Mihai Sain [Thu, 17 Nov 2022 13:30:18 +0000 (15:30 +0200)]
ARM: dts: at91: sama7g5: fix signal name of pin PD8
The signal name of pin PD8 with function D is A22_NANDCLE
as it is defined in the datasheet.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
[claudiu.beznea: rebased on top of 6.1-rc1, removed fixes tag]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20221114151035.2926-1-mihai.sain@microchip.com
Marek Vasut [Thu, 27 Oct 2022 18:38:26 +0000 (20:38 +0200)]
ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench board
Replace "mdio0" node with "mdio" to match mdio.yaml DT schema.
Fixes:
c8ce0dd75515b ("ARM: dts: stm32: Add DHCOR based Testbench board")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Amelie Delaunay [Mon, 24 Oct 2022 09:46:48 +0000 (11:46 +0200)]
ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk
MCP23017 is an IO expander offering 16 input/output port expander with
interrupt output.
On stm32mp135f-dk, only INTA is routed (on PG12), but MCP23017 can mirror
the bank B interrupts on INTA, that's why the property microchip,irq-mirror
is used.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Amelie Delaunay [Mon, 24 Oct 2022 09:46:47 +0000 (11:46 +0200)]
ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13
MCP23017 interrupt line (routed on PG12) requires to be pulled-up.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Andre Przywara [Thu, 10 Nov 2022 00:55:07 +0000 (00:55 +0000)]
ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0
As many other Allwinner SoCs from the last years, the first USB host
controller pair in the Allwinner H3 and H5 chips share a USB PHY with
the MUSB OTG controller. This is probably the reason why we didn't have
a "phys" property in those host controller nodes.
This works fine as long as the MUSB controller driver is loaded, as this
takes care of the proper PHY setup, including the muxing between MUSB
and the HCI.
However this requires the MUSB driver to be enabled and loaded, and also
upsets U-Boot, which cannot use a HCI port without a "phys" property.
Similar to what we did in commit
cc72570747e4 ("arm64: dts: allwinner:
A64: properly connect USB PHY to port 0"), add the "phys" property to
the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file.
This is not only the proper description of the hardware, but also avoids
a nasty error message in U-Boot triggered by a recent patch. (The port
never worked in host mode, but the error was suppressed due to a bug.)
When using the MUSB port in OTG mode, this also fixes host mode
switching, so people can use OTG adapters to connect a USB device to
port 0.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221110005507.19464-1-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Mon, 7 Nov 2022 00:54:30 +0000 (00:54 +0000)]
ARM: dts: suniv: f1c100s: add LRADC node
The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC)
compatible to the version in other SoCs.
The manual doesn't mention the ratio of the input voltage that is used,
but comparing actual measurements with the values in the register
suggests that it is 3/4 of Vref.
Add the DT node describing the base address and interrupt. As in the
older SoCs, there is no explicit reset or clock gate, also there is a
dedicated, non-multiplexed pin, so need for more properties.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-8-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Mon, 7 Nov 2022 00:54:29 +0000 (00:54 +0000)]
ARM: dts: suniv: f1c100s: add CIR DT node
The CIR (infrared receiver) controller in the Allwinner F1C100s series
of SoCs is compatible to the ones used in other Allwinner SoCs.
Add the DT node describing the resources of the controller.
There are multiple possible pinmuxes, but none as them seem to be an
obvious choice, so refrain from adding any pincontroller subnodes for
now.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-7-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
projects / platform / kernel / linux-starfive.git / log