radeonsi/sqtt: implement offset workaround for gfx11

Based on PAL and Samuel's code from !20338.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20529>

radeonsi/sqtt: update registers for gfx11

Based on registers delta and PAL.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20529>

radeonsi/sqtt: disable SE1+ on GFX11

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20529>

radeonsi/sqtt: don't read results for disabled SEs

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20529>

ac: add TC_OP_ATOMIC_SUB_32

This will be used by SQTT to implement a workaround on GFX11

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20529>

v3dv: enable shaderStorageImageReadWithoutFormat

Note that as we are enabling the feature, we need to set the
VK_FORMAT_FEATURE_2_STORAGE_READ_WITHOUT_FORMAT_BIT_KHR for any format
that supports STORAGE_IMAGE_BIT, from spec:

   "An implementation that supports
   VK_FORMAT_FEATURE_STORAGE_IMAGE_BIT for any format from the given
   list of formats and supports shaderStorageImageReadWithoutFormat
   must support VK_FORMAT_FEATURE_2_STORAGE_READ_WITHOUT_FORMAT_BIT
   for that same format if Vulkan 1.3 or the
   VK_KHR_format_feature_flags2 extension is supported."

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20744>

broadcom/compiler: treat PIPE_FORMAT_NONE as 32-bit formats for output type

Needed to support Vulkan feature shaderStorageImageReadWithoutFormat.

With that enabled we could receive a NONE format on a load image. For
those we treat them as 32-bit formats, that would mean that the
lowering would not need to do any format-specific unpacking.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20744>

broadcom/compiler: v3d_nir_lower_txf_ms doesn't need v3d_compile

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20744>

intel/blorp: Lower base_workgroup_id to zero

We don't use a base workgroup ID for BLOCS.  It needs to be lowered, or
else we'll assert fail when compiling the compute shader.

(Note for stable: this patch doesn't fix a bug in 4abdecce226
specifically, but rather is a missing patch that needed to go along with
the rest of MR 20068, on whichever branches it exists on.)

Fixes: 4abdecce226 ("iris: Lower load_base_workgroup_id to zero")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20750>

freedreno: add support for markers.

Signed-off-by: amber@igalia.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20727>

util/u_trace: pass utrace context to marker functions.

This is needed later by freedreno in order to get
more device information in trace functions.

Signed-off-by: amber@igalia.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20727>

radv: Advertise rt pipelines for Control (DX12)

The game has been working on radv since basically forever.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20729>

zink: remove depth_clip_control_missing workaround

The ANV bug this was meant to represent has been long fixed, and the
workaround has just been a proxy for EXT_depth_clip_control for a while
now.

Let's simplify things a bit, by removing this flag.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20740>

zink: fix depth-clip disable cap

We use EXT_depth_clip_enable for this, not EXT_depth_clip_control, which
is what depth_clip_control_missing is a proxy for.

Fixes: 721f33cd0fc ("zink: fix return for PIPE_CAP_DEPTH_CLIP_DISABLE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20740>

zink: whitespace fixup

This just cleans up some indentation, no functional changes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20745>

ac/nir: clear unused components before storing XFB outputs to LDS

Shader variables don't always exactly match intrinsics and they might
contain unused slots.

Fixes a bunch of regressions with RADV_PERFTEST=ngg_streamout on RDNA2,
and also fixes RDNA3 NGG streamout.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8099
Fixes: cd22bf90e79 ("ac/nir/ngg: refine nogs outputs handling")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20735>

zink: skip implicit feedback loop layout changes if feedback loop not present

if a resource is bound as both a framebuffer attachment and a sampler but
isn't actually used as a sampler, it's just a framebuffer attachment, and it
should retain its layout as a framebuffer attachment without any barriers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20674>

zink: make implicit feedback loop application stricter

in many cases, a texture may be bound as both a framebuffer attachment
and a samplerview without the latter actually being used by a shader

this avoids unnecessary feedback loop tagging, which should improve
perf and avoid spurious warning messages on drivers that don't support
the feedback loop ext

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20674>

zink: outdent code in add_implicit_color_feedback_loop()

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20674>

zink: set textures_used in analyze_io

this is otherwise not usable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20674>

zink: break out implicit feedback loop detection into separate function

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20674>

freedreno: Restore GL_VENDOR string

We cannot change this, as it has already been communicated to app
partners.  Also this breaks chrome's GPU quirk matching (which in some
cases is non-gpu-related, but when all you have is a hammer, everything
looks like a nail).

Fixes: 9c1fbc076af ("Return 'Mesa' for GL_VENDOR for community drivers")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20757>

vulkan/format: add a 10-bit video format

This adds support to the generic vulkan format code for
VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16
which is used for 10-bit H265.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
(Updated version acked by Lynne on irc)

v2: disable these for freedreno

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20389>

vulkan/video: add common h264/h265 parameter set management code.

The video session and video session parameters objects can have a common
base class the drivers can inherit from if needed.

This creates code to parse the h264/h265 parameter sets into common
structs.

v2: add h265 VPS, add a macro for FIND/ADD generations, changes the API
to make generation easier.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20389>

freedreno/a6xx: Expose SSBO/image for all shader stages

Now that we've removed the limitation of a single bindful IBO state, we
can expose IBO support on all shader stages.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/a6xx: Move tex state building

Now that it is only called from fd6_texture, move it there where it more
rightly belongs.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/a6xx: Move compute to tex state group

This lets compute shaders hit the shader state cache as well, and
unifies 3d and cs state emit allowing for more code sharing.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/a6xx: Remove tex fb_read state

Now that fb_read is using a bindless descriptor slot, we can remove the
dependency of the TEX state on the PROG state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/a6xx: Removing munging of tex state for IBO

Now that we use bindless descriptors for SSBO/image, lowering to isam
means we can use the existing descriptor.  Avoiding the need to smash in
extra bindful sampler state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/a6xx: Remove bindfull IBO state

Now that it is unused.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/a6xx: Switch over to bindless IBO

This allows support for SSBOs/images in all shader stages.  And also,
unlike the bindful IBO state, does not introduce a dependency on the
program state.  With bindless descriptors, SSBO and image fetch lowered
to isam can re-use the same descriptor.  This will let us remove the
TEX state dependency on PROG state (in a following cleanup commit).

Note, this does not yet switch the pipe caps to reflect that we can
support SSBOs/images in other shader stages.. because ir3 still tells us
nibo>0 even though we are using bindless and that triggers an assert in
the build_ibo() path.  Probably we want ir3 to be more clever.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/a6xx: Add bindless state

This will be used when we switch over to lowering image/SSBO to
bindless.

Note that it also starts using CP_SET_DRAW_STATE in the compute path.
Subsequent cleanup will switch texture and eventually other state over
as well (which will make more sense when we get more clever than
emitting all state for every compute grid, but for now simplifies
re-using the same code between 3d and compute).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/a6xx: Pre-bake IBO descriptor sets

Pre-bake IBO descriptor sets at the time that images/SSBOs are bound,
and re-use the pre-baked descriptors at draw time when we emit state.

This starts putting in place the state tracking we'll use when switching
over to bindless IBO state, without yet changing the shaders (lowering
to bindless) or changing the actual state emitted (other than switching
to use the storage descriptor for image reads via isam, like tu does).

Note that this even pre-bakes the iova into the descriptor, rather than
relying on OUT_RELOC() to do the bo tracking, so we need to manually
attach the bo to the ring.  But we already require FD_BO_NO_HARDPIN for
a6xx.  This makes the state emit a straight memcpy, and will simplify
things when it comes to generating the bindless descriptor set (which
due to the desc_size field in the low bits of the BINDLESS_BASE regs
would be awkward to construct as a ring rather than a bo).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/ir3: Add descriptor set lowering

Add support to lower IBO (image/SSBO) and fb-read to use bindless
descriptors.  This will be used by a6xx to avoid having to merge image
and SSBO state into a single compact IBO descriptor, and also simplify
enabling image and SSBO support for additional shader stages (since each
stage can use it's own descriptor set).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno: Track image/SSBO usage for all stages

Once a6xx enables image/SSBO for all shader stages, we have to care
about more than just frag shader in the 3d path.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/ir3: Let driver specify fb-read descriptor

Let the driver control where the shader should look for fb-read
descriptor.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

freedreno/ir3: Stop copying options

Just copy the entire ir3_compiler_options into ir3_compiler, to make it
easier to add new options.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>

radeonsi: update nir xfb info after medium io lowering

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

nir/xfb_info: nir_gather_xfb_info_from_intrinsics update nir xfb_info

Use this function to update nir_shader->xfb_info.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

gallium/aux: remove nir_helpers

Not used by anyone.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: move gfx10_ngg_export_vertex to si_shader_llvm.c

It's now also used by non-ngg pipeline and older GPUs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: replace llvm legacy gs code with nir lowering

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: remove llvm gs copy shader generate

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: replace llvm gs copy shader generation with nir

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: build legacy gs output info when shader compile

To be used by both legacy gs lowering and gs copy shader
generation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: add nir implementation of gs copy shader generation

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: use ac_nir_lower_legacy_vs to replace si_llvm_vs_build_end

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: use nir_print_xfb_info to replace si_dump_streamout

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: lower nir streamout intrinsics in abi

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: implement nir_load_ring_gs2vs_offset_amd

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

radeonsi: implement nir_load_ring_gsvs_amd

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>

ci: Enable building the testing drivers with perfetto.

We've talked about being able to capture perfetto traces from CI jobs for
a while, and this would be a step toward that.  Mostly it's that we
occasionally break the perfetto build, so let's make sure we don't do
that.

Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>

freedreno/pps: Fix a signed/unsigned complaint.

../src/freedreno/ds/fd_pps_driver.cc:656:44: error: comparison of integer expressions of different signedness: '__gnu_cxx::__alloc_traits<std::allocator<int>, int>::value_type' {aka 'int'} and 'const unsigned int' [-Werror=sign-compare]
  656 |             assert(d->assigned_counters[i] < g->num_counters);
cc1plus: all warnings being treated as errors

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>

ci/freedreno: Add glx-swap-event-async as a flake.

It's only happened a few times in the last year (used to be more popular),
but it just took out a merge.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>

freedreno: Skip CPU/GPU timestamp sync when not supported.

Fixes immediate segfaults in perfetto-enabled builds on pre-a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>

ci/zink: Add more blit conversion xfails for a618.

Popular cases in this group recently:

      1 dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_r16ui
      1 dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_rgb10_a2ui
      1 dEQP-GLES3.functional.fbo.blit.conversion.rgb5_a1_to_rgb5_a1
      3 dEQP-GLES3.functional.fbo.blit.conversion.rgba4_to_r32f
      4 dEQP-GLES3.functional.fbo.blit.conversion.rgb565_to_rgba8
      5 dEQP-GLES3.functional.fbo.blit.conversion.rgba4_to_rg16f

There's pretty clearly something common with blitting from 16-bit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>

ci/iris: Generalize the 8888_pbuffer EGL known flakes and share with GLK.

It seems to be this whole group of tests, on both boards that run EGL
tests by default (aml-y is manual-only).  Make them a regex until someone
comes up with a fix.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>

ci/iris: Add known flakes for skqp.

We've had a lot more jobs run since I landed the CI, and these seem to be
the common flakes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>

ci/llvmpipe: Drop dEQP-EGL.functional.sharing.*.link.7 flakes.

These appear to have been resolved by !20458 -- went from typically
multiple per day to none since then.  The link.19 fails to seem to still
happen, though.

Closes: #7759
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>

gallium,util: Pull u_indices and u_primconvert back into gallium

This was moved in !13741 but doing so created a link-time dependency
between util and gallium which causes problems for Vulkan drivers.
Meanwhile, having mesa/main depend on gallium is fine now that we don't
have any classic drivers.  It's a bit circular but should be harmless.

Fixes: 97ba2f2fd486 ("move util/indices to core util")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8098
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20734>

radeonsi: Fix distortion for yuv422 format for GFX10.

For yuv422 format camera show blur output for GFX10.

Signed-off-by: Ikshwaku Chauhan <ikshwaku.chauhan@amd.com>
Reviewed-by: Marek Olšák marek.olsak@amd.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20610>

ci/venus: Remove failure now passing

It has been fixed either in the CTS or in llvmpipe itself but this now passes when running
in CI.

We haven't seen it in CI yet as we are only running a subset of the Vulkan CTS.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20743>

zink: prune old swapchains on present

pruning old swapchains is challenging because there's no way to definitively
know when to destroy them without VK_EXT_swapchain_maintenance1 which isn't
supported yet

initially, I handled it by only pruning on shutdown and whenever a new swapchain
was created since those are both safe points, but this leads to scenarios where
a dead swapchain can exist for the entire lifetime of an application
if the swapinterval is changed

to avoid such ballooning, check whether the current swapchain has ever presented
on each present queue and then prune based on this

fixes #7529

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20588>

dri2: Fix exposing robustness with swkms.

In the original change I noticed that missing robustness on swkms seemed
to be an oversight, since it was enabled on sw-non-kms, so I exposed the
ext based on the underlying pipe query.  However it turns out that there
is a dri_screen flag for allowing robust contexts that exists to do error
checking for GLX, which was under an !swkms check.  So we would expose the
ext, but then throw an error if you tried to create one.

Fixes: e6285ea55fb2 ("egl: Replace the robustness DRI2 ext check with a pipe cap query.")
Closes: #8066
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20679>

dzn: Remove cmdbuf query 'wait' list

From the Vulkan spec, the WAIT flag on vkCmdCopyQueryPoolResults only
serves to increase the first synchronization scope to include query end
commands, but either way, the synchronization scope only includes
commands that occur earlier in submission order. In other words, we
don't need to enforce queue ordering, a pipeline barrier is all that's
needed.

Fixes deadlocks in the timestamp.misc_tests.two_cmd_buffers_primary test.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>

dzn: Fix format support checks for storage/uniform texel buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>

dzn: Disable depth when the rasterizer is disabled due to no position output

D3D considers the rasterizer enabled if there's a pixel shader *or* if
depth is enabled, since you can do depth-only rendering. After parsing
shaders, if we find that there was supposed to be a pixel shader, but
we removed it because there was no output position, disable depth too.

Also, store this info in the cache, since we might not even load the
nir shaders if we'd seen this pipeline before.

Fixes dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>

dzn: Add a zeroed zsa state when depth or raster is disabled

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>

dzn: Always align cached pipeline header size to input element align

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>

dzn: Support unnormalized coordinate samplers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>

dzn: Support root signature 1.2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>

dzn: Define a symbol that was present in older D3D headers

D3D12_BARRIER_SYNC_INPUT_ASSEMBLER was renamed to D3D12_BARRIER_SYNC_INDEX_INPUT,
so conditionally define the old name based on the version of the headers that are
being used.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>

v3d: expose more drm formats with SAND128 modifier

Adds four more PIPE_FORMATs that expose BROADCOM_SAND128. This allows mpv
to do hardware decoding on the Raspberry Pi 4.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7944
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20510>

freedreno/a6xx: Rework barrier handling

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>

freedreno: Don't re-install a flushed batch

The compute path does this save/restore dance with the current batch, so
various things called to emit state can assume ctx->batch is the current
thing.  But during resource tracking, which could have flushed what was
previously the current batch.  Fixes a problem that surfaces in the next
patch when we stop just flushing batches for all the barriers.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>

freedreno/a6xx: Workaround for no pos/psize

The hw seems unhappy if there are zero outputs from the last geometry
stage.  So add a dummy varying as a workaround.  Turnip got a similar
workaround in commit d6d75fcd915 ("tu: Fix hangs for DS with no output")

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>

freedreno: Fix tracking of enabled SSBOs

Clearing all of the modified bits an relying on OR'ing the needed bits
back in the loop below doesn't quite work out, Because of early continue
if the SSBO has not changed.

Fixes: 0ed053f03d9 ("freedreno: simplify fd_set_shader_buffers(..)")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>

freedreno/drm: Remove assert

We can hit this scenario if there is a GPU hang before the userspace
fence writeback happens.  Since we have asserts enabled in CI, just
remove this assert.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>

r600/sfn: Do a bit of cleanup with the secondary read port validation

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>

r600/sfn: Fix readport check

We have to take multi-slot instructions into account, and we don't fail
when there are still possible bank swizzle values to be checked.

For clarity also rename the bank swizzle iterator iterator.

Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>

radv/gfx11: expose shaderBufferFloat32AtomicAdd

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>

radv: load ssbo_atomic_fadd descriptor

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>

aco: add support for fp32 addition atomics

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>

ac/llvm: add support for fp32 addition atomics

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>

anv: Move anv_device_check_status() code to i915/anv_device.c

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>

anv: Split i915 code from anv_batch_chain.c

There is no change in behavior here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>

anv: Export anv_exec_batch_debug() and chain_command_buffers()

This functions will be used by i915 and Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>

anv: Start to move i915 specific code from anv_device to i915/anv_device

More code re-organization to separate i915_drm.h specific code from
the rest.

No behavior changes here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>

virgl: drop the separable flag for cases that can't be handled

The host can't assign more than 32 locations explicitly, and we
exhaust this already when we handle patches and generics. So
drop the separable flag in cases when we have other IO that
uses generated names that will have to be matched by name.

v2: skip tests for VS input and FS outputs

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20738>

freedreno/ci: Add an a618 flake

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>

Revert "freedreno/ci: Switch a630 jobs over to manual"

This reverts commit 0cc3701338178bf45f4e6d2d496646b6dec7b297.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>

Revert "freedreno/ci: Switch also performance a630 job to manual"

This reverts commit 3be7a28b24256e4bdc4fe4ba6428ef767c7bd287.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>

intel: use a shared UUID with other drivers

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20408>

intel/compiler: add cpp_std=c++17 when building tests

Otherwise build fails:

"../src/intel/compiler/brw_private.h:40:4: note:
 ‘std::variant’ is only available from C++17 onwards"

Fixes: 6c194ddd18f ("intel/compiler: Prepare SIMD selection helpers to handle different prog_datas")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20725>

virgl: Request setting the atomic offset in the range_base

With that NTT can encode the array base of atomic arrays separately
so that the host driver can address the arrays correctly.

Fixes GL-CTS: KHR-Single-GL43.arrays_of_arrays_gl.AtomicUsage

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>

virgl: lower image variable offsets into the intrinsic range_base value

With that we get the correct base offset when accessing image arrays.
This is required if there a various images with different access
specifiers, because only with the correct base offset the host driver is
able to pick the right array.

Fixes GL-CTS: KHR-GL43.shading_language_420pack.binding_image_array

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>

ntt: Make use of the range_base offset when translating atomics in NTT

v2: Unconditionally add teh range base, it is properly initialized.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>

ntt: handle the image intrinsic range_base when translating to TGSI

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>

nir: Add range_base to atomic_counter and an option to use it

Some drivers may encode constant offsets in the instruction, so
make it possible for the drivers to request lowering the atomic
uniform offset into the range_base variable of the intrinsic.

v2: drop patch to use build-in array offset evaluation, it makes
    problems with zink, and update the code accordingly
v3: always initialize range base

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>

nir: Add possibility to store image var offset in range_base

Add the intrinsic range_base value to the image intrinsics and add
the option to store the image array offset into range_base instead
of adding it to the image array index if the driver requests it.

v2: Always initialize range_base

v3: fix for bindless intrinsics

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>