Yuantian Tang [Wed, 19 Apr 2017 05:27:39 +0000 (13:27 +0800)]
arm: psci: make psci usable on single core socs
PSCI can be used on both multiple and single core socs. Current
implementation only allows PSCI to work on multiple core socs.
This patch removes this restriction so that PSCI can work on
single core socs as well.
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Wed, 19 Apr 2017 23:39:13 +0000 (05:09 +0530)]
armv8: ls104xardb: Secure Boot: enable PPA support for eMMC/SD and NAND boot
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Wed, 19 Apr 2017 23:39:12 +0000 (05:09 +0530)]
armv8: fsl-layerscape: Add validation of PPA image from NAND and SD
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Wed, 19 Apr 2017 23:39:11 +0000 (05:09 +0530)]
armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND Flash
Add Kconfig option to support loading PPA header from eMMC/SD and
NAND Flash.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 14 Apr 2017 06:48:23 +0000 (14:48 +0800)]
armv8: ls1046aqds: Integrate FSL PPA
The PPA is a EL3 firmware, which support PSCI, hotplug,
power-management features etc.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 14 Apr 2017 06:48:22 +0000 (14:48 +0800)]
armv8: ls1043aqds: enable FSL PPA
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Fri, 14 Apr 2017 06:48:21 +0000 (14:48 +0800)]
armv8: ls1043aqds: Integrate FSL PPA
The PPA is a EL3 firmware, which support PSCI, hotplug,
power-management features etc.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Santan Kumar [Thu, 13 Apr 2017 10:01:09 +0000 (15:31 +0530)]
armv8: ls2080ardb: Add phy number for serdes1 protocol 0x4b
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Tue, 11 Apr 2017 07:02:13 +0000 (15:02 +0800)]
arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033
Since commit ce412b7, RGMII TX clock internal delay is not enabled
for AR8033 unconditionally. On LS1021ATWR board, the third port
eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to
be enabled.
This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX
clock internal delay for AR8033 on the third port.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Tom Rini [Tue, 18 Apr 2017 15:36:06 +0000 (11:36 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 18 Apr 2017 14:31:46 +0000 (10:31 -0400)]
Merge git://git.denx.de/u-boot-x86
Tom Rini [Tue, 18 Apr 2017 14:31:39 +0000 (10:31 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-ubi
Tom Rini [Tue, 18 Apr 2017 14:30:09 +0000 (10:30 -0400)]
board: Remove orphan SPARC boards
Since
936478e797a8 SPARC as been removed as an architecture. Remove
these now orphan boards.
Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sat, 15 Apr 2017 19:11:31 +0000 (13:11 -0600)]
rockchip: Print a message when returning to the bootrom
At present if the return to bootrom fails (e.g. because you are not using
the Rockchip's bootrom's pointer table in MMC) then the board prints
SPL message and hangs. Print a message first if we can, to help in
understanding what happened when it hangs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 14:37:54 +0000 (16:37 +0200)]
drivers/crypto/fsl: remove redundant logical contraint
'A || (!A && B)' is equivalent to 'A || B'.
Let's reduce the complexity of the statement in start_jr0().
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:31:53 +0000 (15:31 +0200)]
fsl/sata: correctly identify failed malloc
After allocating sata->cmd_hdr_tbl_offset we have to check
this variable and not variable sata.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:23:49 +0000 (15:23 +0200)]
ddr: fsl: incorrect logical constraint in populate_memctl_options
(pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40)
is always true.
We should use && here.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:15:40 +0000 (15:15 +0200)]
FPGA: drivers/fpga/ivm_core.c: incorrect printf
The number of arguments for printf does not match the
format string.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 13:05:46 +0000 (15:05 +0200)]
usbtty: avoid potential NULL pointer dereference
If current_urb is NULL it should not be dereferenced.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 11:28:13 +0000 (13:28 +0200)]
yaffs2: remove redundant condition
If !parent, the changed line is not reached.
So there is no need to check the value again.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 11:05:40 +0000 (13:05 +0200)]
tools/env: avoid memory leak in fw_setenv
If realloc fails we should release the old buffer.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 10:29:20 +0000 (12:29 +0200)]
arm: omap-common: add missing va_end()
Each call of va_start must be matched by a call of va_end.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 14 Apr 2017 23:47:51 +0000 (19:47 -0400)]
travis-ci: Switch over to Linaro gcc-6.3.1 toolchains for ARM
Linaro provides a number of pre-built GCC toolchains for both 32 and
64bit ARM. Switch to their 2017.02 release of gcc-6.3.1 for both.
Cc: Koen Kooi <koen.kooi@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 14 Apr 2017 23:47:50 +0000 (19:47 -0400)]
buildman: Allow 'gnueabihf' toolchains for ARM
Many toolchains for ARM use the 'gnueabihf' suffix rather than just
'gnueabi', so allow these to be used, but with a lower priority than
'gnueabi' ones.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Fri, 14 Apr 2017 02:10:24 +0000 (11:10 +0900)]
sysreset: psci: support system reset in a generic way with PSCI
If the system is running PSCI firmware, the System Reset function
(func ID: 0x80000009) is supposed to be handled by PSCI, that is,
the SoC/board specific reset implementation should be moved to PSCI.
U-Boot should call the PSCI service according to the arm-smccc
manner.
The arm-smccc is supported on ARMv7 or later. Especially, ARMv8
generation SoCs are likely to run ARM Trusted Firmware BL31. In
this case, U-Boot is a non-secure world boot loader, so it should
not be able to reset the system directly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 14 Apr 2017 02:10:23 +0000 (11:10 +0900)]
ARM: adjust arm-smccc code for use in U-Boot
Adjust ARM SMC Calling Convention code for U-Boot:
- Replace the license block with SPDX
- Change path to asm-offsets.h
- Define UNWIND() as no-op
- Add Kconfig entry
- Add asm-offsets
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 14 Apr 2017 02:10:22 +0000 (11:10 +0900)]
ARM: import arm-smccc code from Linux 4.11-rc6
Imports ARM SMC Calling Convention code from Linux 4.11-rc6.
The files have been copied as follows:
[Linux] [U-Boot]
arch/arm/kernel/smccc-call.S -> arch/arm/cpu/armv7/smccc-call.S
arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S
arch/arm/include/asm/opcodes* -> arch/arm/include/asm/opcodes*
include/linux/arm-smccc.h -> include/linux/arm-smccc.h
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 14 Apr 2017 02:05:48 +0000 (11:05 +0900)]
blackfin: ibf-dsp561: remove orphan Blackfin board
This is a Blackfin board that commit
ea3310e8aafa ("Blackfin:
Remove") missed to remove.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 14 Apr 2017 01:55:00 +0000 (10:55 +0900)]
drivers: remove Blackfin specific drivers
These drivers have no user since commit
ea3310e8aafa ("Blackfin:
Remove").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Masahiro Yamada [Fri, 14 Apr 2017 01:54:59 +0000 (10:54 +0900)]
cmd: remove Blackfin specific commands
These commands have no user since commit
ea3310e8aafa ("Blackfin:
Remove").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Fri, 14 Apr 2017 01:53:56 +0000 (10:53 +0900)]
tools: moveconfig: remove GCC prefix of obsolete architecture
Recently, U-Boot removed support for these architectures.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tyler Hall [Wed, 12 Apr 2017 20:29:17 +0000 (16:29 -0400)]
cramfs: basic symlink support
Handle symlinks to files in the current directory. Other cases could be
handled with additional code, but this is a start.
Add explicit errors for absolute paths and links found in the middle of
a path (directories). Other cases like '..' or '.' will result with the
file not being found as when those path components are explicitly
provided.
Add a helper to decompress a null-terminated link name which is shared
with cramfs_list_inode.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
Tyler Hall [Wed, 12 Apr 2017 20:29:16 +0000 (16:29 -0400)]
cramfs: block pointers are 32 bits
Using a variably-sized type is incorrect here since we're reading a
fixed file format. Fixes cramfs on 64-bit platforms.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
Tyler Hall [Wed, 12 Apr 2017 20:29:15 +0000 (16:29 -0400)]
cmd: cramfs: use map_sysmem for sandbox support
As with most other commands, this needs to factor in the sysmem offset
in the sandbox or it will try to dereference the simulated physical
address directly.
Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
Simon Glass [Sun, 19 Mar 2017 18:59:22 +0000 (12:59 -0600)]
x86: config: Enable dhrystone command for link
Enable this command so we can get an approximate performance measurement.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 19 Mar 2017 18:59:21 +0000 (12:59 -0600)]
x86: Display the SPL banner only once
At present on a cold reboot we must reset the CPU to get it to full speed.
With 64-bit U-Boot this happens in SPL. At present we print the banner
before doing this, the end result being that we print the banner twice.
Print the banner a little later (after the CPU is ready) to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 19 Mar 2017 18:59:20 +0000 (12:59 -0600)]
x86: Drop leading spaces in cpu_x86_get_desc()
The Intel CPU name can have leading spaces. Remove them since they are not
useful.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
xypron.glpk@gmx.de [Sat, 15 Apr 2017 14:25:25 +0000 (16:25 +0200)]
cmd: ubi: remove unnecessary logical constraint
A size_t variable can never be negative.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tom Rini [Mon, 17 Apr 2017 22:16:49 +0000 (18:16 -0400)]
Prepare v2017.05-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Shengzhou Liu [Mon, 10 Apr 2017 08:00:08 +0000 (16:00 +0800)]
powerpc/board/t1024rdb: enable board-level reset when issuing reset command
As board-specific reset logic, it needs to issue reset signal
via CPLD when issuing 'reset' command in u-boot, this patch
solves the issue of reset command not working on T1024RDB.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ruchika Gupta [Thu, 2 Mar 2017 08:42:41 +0000 (14:12 +0530)]
powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram
For E6500 cores, L2 cache has been used as init_ram. L1 cache is a
write through cache on E6500.If lines are not locked in both L1 and
L2 caches, crashes are observed during secure boot. This patch locks/
unlocks both L1 and L2 cache to prevent the crash.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Yangbo Lu [Mon, 10 Apr 2017 07:04:11 +0000 (15:04 +0800)]
armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQ
Current sysclk fixing would fix all clocks with 'fixed-clock' compatible.
This patch is to fix sysclk by path to avoid any incorrect fixing.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ashish kumar [Fri, 7 Apr 2017 06:10:32 +0000 (11:40 +0530)]
armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups
Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Santan Kumar [Wed, 5 Apr 2017 09:04:32 +0000 (14:34 +0530)]
armv8: ls2080a: Add serdes2 protocol 0x51 support
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Shengzhou Liu [Thu, 23 Mar 2017 10:14:40 +0000 (18:14 +0800)]
arm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoC
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
tang yuantian [Fri, 10 Mar 2017 06:49:25 +0000 (14:49 +0800)]
armv8: ls1046aqds: enable ppa in default config
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Mon, 27 Mar 2017 18:41:03 +0000 (11:41 -0700)]
armv7: ls1021a: Drop macro CONFIG_LS102XA
Use CONFIG_ARCH_LS1021A instead.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Mon, 27 Mar 2017 18:41:02 +0000 (11:41 -0700)]
armv8: ls1043a: Drop macro CONFIG_LS1043A
Use CONFIG_ARCH_LS1043A instead.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Mon, 27 Mar 2017 18:41:01 +0000 (11:41 -0700)]
armv8: ls2080a: Drop macro CONFIG_LS2080A
Use CONFIG_ARCH_LS2080A instead.
Signed-off-by: York Sun <york.sun@nxp.com>
Ruchika Gupta [Mon, 17 Apr 2017 12:37:19 +0000 (18:07 +0530)]
arm: ls1046ardb: Add SD secure boot target
- Add SD secure boot target for ls1046ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size
as header is appended to u-boot image. So header will also be
copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for the
header.
- Reduce the size of CAAM driver for SPL Blobification functions
and descriptors, that are not required at the time of SPL are
disabled. Further error code conversion to strings is disabled
for SPL build.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ruchika Gupta [Mon, 17 Apr 2017 12:37:18 +0000 (18:07 +0530)]
arm: ls1043ardb: Add NAND secure boot target
Add NAND secure boot target for ls1043ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript
from NAND to DDR. Offsets for Bootscript on NAND and DDR have been
also defined.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ruchika Gupta [Mon, 17 Apr 2017 12:37:17 +0000 (18:07 +0530)]
arm: ls1043ardb: Add SD secure boot target
- Add SD secure boot target for ls1043ardb.
- Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream
ID and corresponding stream ID in SMMU.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied
from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM
(128K) where 32K are reserved for use by boot ROM and 6K for secure
boto header.
- Error messages during SPL boot are limited to error code numbers
instead of strings to reduce the size of SPL image.
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Vinitha Pillai-B57223 [Thu, 23 Mar 2017 08:18:20 +0000 (13:48 +0530)]
armv8: LS1012ARDB: Add QSPI Secure Boot target
Add QSPI Secure Boot target to enable chain of trust
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Vinitha Pillai-B57223 [Thu, 23 Mar 2017 08:18:19 +0000 (13:48 +0530)]
armv8: SECURE_BOOT: Enable chain of trust on LS1012A platform
Define bootscript and its header addresses for QSPI target
Also add PPA header address in Kconfig
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Vinitha Pillai-B57223 [Thu, 23 Mar 2017 08:18:18 +0000 (13:48 +0530)]
armv8: LS1046ARDB: Add QSPI Secure Boot target
Add QSPI Secure Boot target. Also enable sec init.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Thu, 23 Mar 2017 08:18:17 +0000 (13:48 +0530)]
armv8: LS1046AQDS: Add NOR Secure Boot Target
Add NOR secure boot target. Also enable sec init.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Vinitha Pillai-B57223 [Thu, 23 Mar 2017 08:18:16 +0000 (13:48 +0530)]
armv8: SECURE_BOOT: Enable chain of trust on LS1046A platform
Define bootscript and its header addresses for QSPI target. Also
define PPA header address to enable PPA validation.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Vinitha Pillai-B57223 [Thu, 23 Mar 2017 08:18:15 +0000 (13:48 +0530)]
armv8: LS1043ARDB: Enable PPA in Secure boot defconfig
Enable PPA in secure boot by defining FSL_LS_PPA macro in its
defconfig file.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Vinitha Pillai-B57223 [Thu, 23 Mar 2017 08:18:14 +0000 (13:48 +0530)]
armv8: fsl-layerscape: SECURE BOOT: Add header address of PPA in kconfig
The header address of PPA defined in Kconfig.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
VINITHA PILLAI [Fri, 31 Mar 2017 05:20:02 +0000 (10:50 +0530)]
powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilation
BLOB feature is not required during SPL compilation.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Thu, 30 Mar 2017 04:23:13 +0000 (09:53 +0530)]
armv8: ls1046ardb: SPL size reduction
Using changes in this patch we were able to reduce approx 4k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1046ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1046ardb/ls1046ardb.c to keep
only ddr_init and board_early_init_f funcations in case of SPL
build.
3. Changes in ls1046a_common.h & ls1046ardb.h to remove driver
specific macros due to which static data was being compiled in
case of SPL build.
4. Disable MMC driver from bieng compiled in case of SPL NAND
build and NAND driver from bieng compiled in case of SPL MMC build.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Thu, 30 Mar 2017 04:22:38 +0000 (09:52 +0530)]
armv8: ls1043ardb: SPL size reduction
Using changes in this patch we were able to reduce approx 10k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1043ardb/Makefile to remove
compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1043ardb/ls1043ardb.c to keep
only ddr_init and board_early_init_f funcations in case of SPL
build.
3. Changes in ls1043a_common.h & ls1043ardb.h to remove driver
specific macros due to which static data was being compiled in
case of SPL build.
4. Disable MMC driver from bieng compiled in case of SPL NAND
build and NAND driver from bieng compiled in case of SPL MMC build.
5. Remove I2C driver support from SPL in case of LS1043ARDB.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Thomas Schaefer [Tue, 28 Mar 2017 18:29:56 +0000 (11:29 -0700)]
drivers: ddr: fsl: fix unused-const-variable warnings
Depending on DDR configuration, gcc-6.x will show up unused-const-
variable messages. Use __maybe_unused specifier for all dynamic_odt
variable definitions to remove these warnings.
Memory footprint will not increase as gcc will optimize out unused
constants.
Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Tom Rini [Mon, 17 Apr 2017 02:08:13 +0000 (22:08 -0400)]
Merge git://git.denx.de/u-boot-rockchip
Tom Rini [Mon, 17 Apr 2017 02:07:52 +0000 (22:07 -0400)]
Merge git://git.denx.de/u-boot-dm
Philipp Tomsich [Sat, 1 Apr 2017 10:59:25 +0000 (12:59 +0200)]
rockchip: rk3399: spl: add UART0 support for SPL
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).
To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.
As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.
As the RK3399 needs to use its board_debug_uart_init() function, we
have Kconfig enable it by default for RK3399 builds.
With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB are then update (the change for the RK3399-Q7 is
left for later to not cause issues on applying the change).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
eric.gao@rock-chips.com [Mon, 10 Apr 2017 02:41:46 +0000 (10:41 +0800)]
rockchip: pmic: Enable RK808 for rk3399 evb
For using mipi display, we need to enable lcd3v3
which supplied by rk808,so enable rk808 first.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
eric.gao@rock-chips.com [Mon, 10 Apr 2017 02:17:03 +0000 (10:17 +0800)]
rockchip: i2c: Enable i2c for rk3399
To enable mipi display, we need to enable pmic
rk808 first for lcd3v3 power,which use i2c0 to
communicate with soc. So enable i2c0.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
eric.gao@rock-chips.com [Mon, 10 Apr 2017 01:53:31 +0000 (09:53 +0800)]
rockchip: rk3399: Add missing sentinel in syscon
when enable PMIC rk808,the system will halt at very
early stage,log is shown as bellow.
INFO: plat_rockchip_pmu_init(1211): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x200000
INFO: SPSR = 0x3c9
time 44561b, 0 (<<----Just stop here)
It's caused by the absence of "{ }" in syscon_rk3399.c
,which will lead to memory overflow like below.According
to Sysmap file ,we can find the function buck_get_value
of rk808 is just follow the compatible struct,the pointer
"of_match" point to "buck_get_value",but it is not a
struct and don't have member of compatible, In this case,
system crash. So,on the face, it looks like that rk808 is
guilty.but he is really innocent.
while (of_match->compatible) { <<----------
if (!strcmp(of_match->compatible, compat)) {
*of_idp = of_match;
return 0;
}
of_match++;
}
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Klaus Goger [Fri, 7 Apr 2017 17:13:38 +0000 (19:13 +0200)]
rockchip: ARM64: split RK3399-Q7 board off the RK3399-EVB board
The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3399.
It provides the following feature set:
* up to 4GB DDR3
* on-module SPI-NOR flash
* on-module eMMC (with 8-bit interace)
* SD card (on a baseboad) via edge connector
* Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY
* HDMI/eDP/MIPI displays
* 2x MIPI-CSI
* USB
- 1x USB 3.0 dual-role (direct connection)
- 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub)
* on-module STM32 Cortex-M0 companion controller, implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
- USB<->CAN bridge controller
Note that we use a multi-payload FIT image for booting and have
Cortex-M0 payload in a separate subimage: we thus rely on the FIT
image loader to put it into the SRAM region that ATF expects it in.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed build warning on puma-rk3399:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 7 Apr 2017 17:09:37 +0000 (19:09 +0200)]
rockchip: dts: rk3399-puma: make the DTS dual-licensed
The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed.
This updates the licensing info in the rk3399-puma.dts.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Fri, 7 Apr 2017 10:38:52 +0000 (12:38 +0200)]
rockchip: sysreset: rk3188: Make sure remap is off on warm-resets
The warm-reset of rk3188 socs keeps the remap setting as it was, so if
it was enabled, the cpu would start from address 0x0 of the sram instead
of address 0x0 of the bootrom, thus making the reset hang.
Therefore make sure the remap is disabled before attempting a warm reset.
Cold reset is not affected by this at all.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 7 Apr 2017 10:12:55 +0000 (18:12 +0800)]
rockchip: rk3399: do not use lower address
The lower address is reserved for ATF, do not use it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Wed, 5 Apr 2017 22:19:36 +0000 (00:19 +0200)]
rockchip: rk3188: enable remap function
Most Rockchip socs have the ability to either map the bootrom or a sram
area to the starting address of the cpu by flipping a bit in the GRF.
Newer socs leave this untouched and mapped to the bootrom but the legacy
loaders on rk3188 and before enabled the remap functionality and the
current smp implementation in the Linux kernel also requires it to be
enabled, to bring up secondary cpus.
So to keep smp working in the kernel, mimic the behaviour of the legacy
bootloaders and enable the remap functionality.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Wed, 5 Apr 2017 22:19:18 +0000 (00:19 +0200)]
rockchip: cosmetic: Move rock board to its correct position
Somehow
43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards") moved
the rock board in between some rk3288 board, probably as a result of
rebasing.
So move it back to its original position above all rk3288 boards.
Fixes:
43b5c78d8d91 ("rockchip: cosmetic: Sort RK3288 boards")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Sat, 1 Apr 2017 06:49:54 +0000 (14:49 +0800)]
rockchip: Add USB to the default boot targets
Now that most rockchip SoC based board have usb host support, enable
USB boot targets by default.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build errors when CONFIG_CMD_USB not defined:
Signed-off-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Sat, 1 Apr 2017 06:46:52 +0000 (14:46 +0800)]
rockchip: tinker: configs: Add USB, PXE, DHCP to the default boot targets
tinker board support ethernet and usb host, so enable USB, PXE and DHCP support.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 29 Mar 2017 19:20:29 +0000 (21:20 +0200)]
rockchip: dts: rk3399-puma: disable 'fifo-mode' in sdmmc
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 29 Mar 2017 19:20:28 +0000 (21:20 +0200)]
rockchip: spl: rk3399: disable DDR security regions for SPL
The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, the DMA is likely to target this first MB, as it
transfers from/to the stack).
System security is not affected, as the final security configuration is
performed by the ATF, which is executed after the SPL stage.
With this fix in place, we can now drop 'fifo-mode' in the DTS for the
RK3399-Q7 (Puma).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Fri, 14 Apr 2017 00:51:47 +0000 (08:51 +0800)]
board: sama5d3_xplained: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 14 Apr 2017 00:51:46 +0000 (08:51 +0800)]
board: sama5d3_xplained: Clean up code
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 14 Apr 2017 00:51:45 +0000 (08:51 +0800)]
board: sama5d3_xplained: Update to support DM/DT
Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Fix build error with sama5d3_xplained_mmc:
Signed-off-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Fri, 14 Apr 2017 00:51:44 +0000 (08:51 +0800)]
board: sama5d3xek: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang [Fri, 14 Apr 2017 00:51:43 +0000 (08:51 +0800)]
board: sama5d3xek: Clean up code
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Remove CONFIG_PHY_MICREL as per previous patch:
Signed-off-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Fri, 14 Apr 2017 00:51:42 +0000 (08:51 +0800)]
board: sama5d3xek: Update to support DM/DT
Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Add back CONFIG_PHY_MICREL to prevent a build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 15 Apr 2017 02:05:17 +0000 (22:05 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-video
Simon Glass [Mon, 10 Apr 2017 17:34:59 +0000 (11:34 -0600)]
dm: led: Add a new 'led' command
When driver model is used for LEDs, provide a command to allow LED access.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:58 +0000 (11:34 -0600)]
led: Mark existing driver as legacy
The existing 'led' command does not support driver model. Rename it to
indicate that it is legacy code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:57 +0000 (11:34 -0600)]
dm: led: Add support for blinking LEDs
Allow LEDs to be blinked if the driver supports it. Enable this for
sandbox so that the tests run.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:56 +0000 (11:34 -0600)]
dm: led: Support toggling LEDs
Add support for toggling an LED into the uclass interface. This can be
efficiently implemented by the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:55 +0000 (11:34 -0600)]
dm: led: Add support for getting the state of an LED
It is useful to be able to read the LED as well as write it. Add this to
the uclass and update the GPIO driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:54 +0000 (11:34 -0600)]
dm: led: Adjust the LED uclass
At present this is very simple, supporting only on and off. We want to
also support toggling and blinking. As a first step, change the name of
the main method and use an enum to indicate the state.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:53 +0000 (11:34 -0600)]
dm: led: Rename struct led_uclass_plat
These structures are normally named with 'uc' instead of 'uclass'. Change
this one for consistency.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:52 +0000 (11:34 -0600)]
dm: led: Add a missing blank line in the Kconfig file
There should be a blank line between each option. Add one before LED_GPIO.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Simon Glass [Mon, 10 Apr 2017 17:34:51 +0000 (11:34 -0600)]
sandbox: Add some test LEDs
Add some LEDs to the standard sandbox device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ziping Chen <techping.chan@gmail.com>
Jean-Jacques Hiblot [Fri, 7 Apr 2017 11:42:08 +0000 (13:42 +0200)]
dm: scsi: fix divide-by-0 error in scsi_scan()
With DM_SCSI enabled, blk_create_devicef() is called with blkz = 0, leading
to a divide-by-0 exception.
scsi_detect_dev() can be used to get the required parameters (block size
and number of blocks) from the drive before calling blk_create_devicef().
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Fri, 7 Apr 2017 11:42:07 +0000 (13:42 +0200)]
scsi: move the partition initialization out of the scsi detection
We might want to get information about the scsi device without initializing the partition.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Fri, 7 Apr 2017 11:42:06 +0000 (13:42 +0200)]
scsi: make the LUN a parameter of scsi_detect_dev()
This is a cosmetic change. target and LUN have kind of the same role in
this function. One of them was passed as a parameter and the other was
embedded in a structure. For consistency, pass both of them as parameters.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Fri, 7 Apr 2017 11:42:01 +0000 (13:42 +0200)]
arm: omap: sata: compile out board-level sata code when CONFIG_DM_SCSI is defined
When CONFIG_DM_SCSI is defined, the SATA initialization will be implemented
in the scsi-uclass driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Fri, 7 Apr 2017 11:42:00 +0000 (13:42 +0200)]
arm: omap: sata: move enable sata clocks to enable_basic_clocks()
All the clocks which has to be enabled has to be done in
enable_basic_clocks(), so moving enable sata clock to common
clocks enable function.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>