Rob Clark [Fri, 18 Nov 2016 13:39:33 +0000 (08:39 -0500)]
egl: add EGL_ANDROID_native_fence_sync
With fixes from Chad squashed in, plus fixes for issues that Rafael
found while writing piglit tests.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Tested-by: Chad Versace <chadversary@chromium.org>
Rob Clark [Fri, 18 Nov 2016 13:39:32 +0000 (08:39 -0500)]
dri: extend fence extension to support native fd fences
Required to implement EGL_ANDROID_native_fence_sync.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Tested-by: Chad Versace <chadversary@chromium.org>
Rob Clark [Thu, 1 Dec 2016 18:57:24 +0000 (10:57 -0800)]
egl: un-fallthrough sync attr parsing
Doesn't work so well when you start having more than one possible
attrib. Prep-work for next patch.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Tested-by: Chad Versace <chadversary@chromium.org>
Rob Clark [Fri, 18 Nov 2016 13:39:30 +0000 (08:39 -0500)]
egl: initialize SyncCondition after attr parsing
Reduce the noise in the next patch. For EGL_SYNC_NATIVE_FENCE_ANDROID
the sync condition is conditional on EGL_SYNC_NATIVE_FENCE_FD_ANDROID
attribute.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Tested-by: Chad Versace <chadversary@chromium.org>
Tim Rowley [Thu, 1 Dec 2016 17:06:28 +0000 (11:06 -0600)]
tgsi: store writes_primid when scanning tgsi
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Wed, 30 Nov 2016 22:04:06 +0000 (17:04 -0500)]
mesa: only verify that enabled arrays have backing buffers
We were previously also verifying that no backing buffers were available
when an array wasn't enabled. This is has no basis in the spec, and it
causes GLupeN64 to fail as a result.
Fixes:
c2e146f487 ("mesa: error out in indirect draw when vertex bindings mismatch")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Anholt [Wed, 30 Nov 2016 22:00:28 +0000 (14:00 -0800)]
vc4: Avoid false scheduling dependencies for LOAD_IMMs.
Noticed in shaders with branching, where we ended up scheduling delay
slots near the start of a block for the uniforms reset setup.
total instructions in shared programs: 93970 -> 93951 (-0.02%)
instructions in affected programs: 3117 -> 3098 (-0.61%)
3DMMES performance +0.423087% +/- 0.133521% (n=9,10)
Eric Anholt [Wed, 30 Nov 2016 20:19:38 +0000 (12:19 -0800)]
vc4: Try to schedule QIR instructions between writing to and reading math.
This helps us get the delay slots between SFU writes and reads filled.
total instructions in shared programs: 94494 -> 93970 (-0.55%)
instructions in affected programs: 59206 -> 58682 (-0.89%)
3DMMES performance +1.89967% +/- 0.157611% (n=10,9)
Eric Anholt [Wed, 30 Nov 2016 19:52:06 +0000 (11:52 -0800)]
vc4: Improve interleaving of texture coordinates vs results.
The latency_between was trying to handle the delay between the coordinate
write ("before") and the corresponding sample read ("after"), but we were
handing in the two instructions swapped.
This meant that we tried to fit things between a tex_s and its *preceding*
tex_result. This made us only interleave normal texture coordinates by
accident, and pessimized UBO reads by pushing the tex_result collection
earlier until there was nothing but it (and then its preceding coordinate
setup) left.
In addition to latency reduction, things end up packing better (probably
due to reduced live ranges of the texture results):
total instructions in shared programs: 98121 -> 94775 (-3.41%)
instructions in affected programs: 91196 -> 87850 (-3.67%)
3DMMES performance +1.15569% +/- 0.124714% (n=8,10)
Eric Anholt [Wed, 30 Nov 2016 19:30:06 +0000 (11:30 -0800)]
vc4: Fix stray "." on no-op MUL packs.
This happened when the PM bit was set for R4 unpacks, where the MUL pack
was NOP.
Eric Anholt [Wed, 30 Nov 2016 19:25:09 +0000 (11:25 -0800)]
vc4: Allow merging instructions with SF set where the other writes NOP.
I'm not sure how I managed to write the SF merge code
(
7d8b79f398f18ed7bb48a74b1b82950e2f08abad) without allowing merges with
NOPs. *Everything* we try to merge with will have a NOP on one or the
other side of the instruction, and that's why that commit showed no
benefit.
total instructions in shared programs: 99347 -> 95128 (-4.25%)
instructions in affected programs: 91906 -> 87687 (-4.59%)
3DMMES performance +2.57105% +/- 0.135276% (n=6,8)
Eric Anholt [Thu, 1 Dec 2016 01:27:37 +0000 (17:27 -0800)]
vc4: In a loop break/continue, jump if everyone has taken the path.
This should be a win for most loops, which tend to have uniform control
flow.
More importantly, it exposes important information to live variables: that
the break/continue here means that our jump target may have access to
values that were live on our input. Previously, we were just setting the
exec mask and letting control flow fall through, so an intervening def
between the break and the end of the loop would appear to live variables
as if it screened off the variable, when it didn't actually.
Fixes a regression in glsl-vs-loop-redundant-condition.shader_test when a
perturbing of register allocation caused a live variable to get stomped.
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Wed, 30 Nov 2016 05:56:48 +0000 (00:56 -0500)]
anv: expose support for VK_KHR_sampler_mirror_clamp_to_edge
This is already supported in genX_state.c, expose the extension string.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Jason Ekstrand [Tue, 29 Nov 2016 22:00:39 +0000 (14:00 -0800)]
anv/cmd_buffer: Actually use the stencil dimension
In an attempt to fix 3DSTATE_DEPTH_BUFFER for stencil-only cases, I
accidentally kept setting the SurfaceType to 2D in the stencil-only case
thanks to a copy+paste error.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Ilia Mirkin [Sun, 27 Nov 2016 06:15:03 +0000 (01:15 -0500)]
swr: add streamout buffer offset into pBuffer pointer
The buffer_size does not take the offset into account. Just add the
offset into the pointer which lines up the structures much better.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 27 Nov 2016 05:46:33 +0000 (00:46 -0500)]
swr: fix assertion for max number of so targets
The number has to be less than or equal to the max, not just less than.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 27 Nov 2016 05:45:17 +0000 (00:45 -0500)]
swr: properly report max number of SO components
The components count the number of individual values, not the number of
slots.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sat, 26 Nov 2016 22:56:24 +0000 (17:56 -0500)]
swr: turn off queries around blits
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sat, 26 Nov 2016 22:35:31 +0000 (17:35 -0500)]
swr: don't advertise stream pause/resume
There is no support for resuming streamout. Furthermore, this also
controls glDrawTransformFeedback functionality which requires the same
ability to query how many primitives were sent out of TF.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sat, 26 Nov 2016 22:11:50 +0000 (17:11 -0500)]
swr: fix range computation for instanced client-side arrays
We need to take the instance divisor and number of instances into
account for instanced client-side arrays, rather than the vertex
parameters.
Loosely based on the comparable nvc0 logic.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 00:01:06 +0000 (19:01 -0500)]
swr: [rasterizer memory] assert when trying to convert an unknown format
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 19:07:00 +0000 (14:07 -0500)]
swr: remove warning about multi-layer surfaces
We now support clearing these, and actually rendering to multiple layers
would require GS support, which will fail in much more spectacular ways
for now. Once that is hooked up, there won't be anything else to do
here.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Thu, 17 Nov 2016 02:33:29 +0000 (21:33 -0500)]
swr: [rasterizer core] don't attempt to load another RTAI when storing
Since we don't pass a renderTargetArrayIndex in, and the current hot
tile may be for a different index, we may end up loading the RTAI=0 into
the hot tile for no reason.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Marek Olšák [Wed, 30 Nov 2016 00:38:23 +0000 (01:38 +0100)]
radeonsi: document a CP DMA bug that doesn't need a workaround yet
This one is easy to miss, because it's not documented in any internal doc.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 29 Nov 2016 22:35:09 +0000 (23:35 +0100)]
radeonsi: apply the double EVENT_WRITE_EOP workaround to VI as well
Internal docs don't mention it, but they also don't mention that the bug
has been fixed (like other CI bugs fixed in VI).
Vulkan does this too.
v2: also update r600_gfx_write_fence_dwords
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Marek Olšák [Tue, 29 Nov 2016 20:19:52 +0000 (21:19 +0100)]
radeonsi: add a tess+GS hang workaround for VI dGPUs
ported from Vulkan
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 29 Nov 2016 19:49:24 +0000 (20:49 +0100)]
radeonsi: don't apply the Z export bug workaround to Hainan
not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 29 Nov 2016 19:41:23 +0000 (20:41 +0100)]
radeonsi: apply a tessellation bug workaround for SI
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 29 Nov 2016 19:16:50 +0000 (20:16 +0100)]
radeonsi: apply a TC L1 write corruption workaround for SI
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 29 Nov 2016 18:25:03 +0000 (19:25 +0100)]
radeonsi: apply a multi-wave workgroup SPI bug workaround to affected CIK chips
All codepaths are handled except for clover.
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 29 Nov 2016 18:23:20 +0000 (19:23 +0100)]
radeonsi: consolidate max-work-group-size computation
The next commit will need this.
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 30 Nov 2016 21:52:20 +0000 (08:52 +1100)]
mesa: reset linked_stages bitmask when re-linking
34953f8907fdd added this bitmask but it wasn't being reset when
a program was relinked. If a stage was removed from the new
program then it could case a crash as we expect the linked shader
for that stage to not be null.
Fixes crashes in:
ESEXT-CTS.tessellation_shader.single.xfb_captures_data_from_correct_stage
ES31-CTS.core.tessellation_shader.single.xfb_captures_data_from_correct_stage
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98917
Rob Clark [Wed, 30 Nov 2016 21:43:42 +0000 (16:43 -0500)]
freedreno/a5xx: fix negative branches
Looks like immed branch offset size increased again.. making what we
think is a small negative number look to hw like a huge positive number.
And things go badly when shader tries to jump to hyperspace.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 30 Nov 2016 19:01:12 +0000 (14:01 -0500)]
freedreno: fix android build with a5xx
Android doesn't build all the files that normal linux/autotools build
does (mainly standalond ir3_compiler).. but possibly we should pull
C_SOURCES + aNxx_SOURCES into a single variable picked up by both
Android.mk and Makefile.am? (Suggested by Rob H.)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 30 Nov 2016 18:52:11 +0000 (13:52 -0500)]
freedreno/a5xx: fix discard
Signed-off-by: Rob Clark <robdclark@gmail.com>
Ville Syrjälä [Mon, 28 Nov 2016 16:44:28 +0000 (18:44 +0200)]
anv: Prefer in-tree headers to out-of-tree headers
Set the include paths to consider in-tree headers before out-of-tree
headers.
Avoids the build failing due to stale headers being present in
$prefix. Previosuly 'make -ki install' or something similar was required
to update the out-of-tree headers to allow the build to succeed.
Also avoids having to rebuild the entire thing after every 'make
install'.
Cc: Rob Clark <robdclark@gmail.com>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Rob Clark [Tue, 8 Nov 2016 15:50:03 +0000 (10:50 -0500)]
freedreno/a5xx: initial support
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 8 Nov 2016 15:49:16 +0000 (10:49 -0500)]
freedreno: update generated headers
Pull in a5xx
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 14:53:44 +0000 (09:53 -0500)]
freedreno: make gmem tile size alignment configurable
a5xx seems to prefer 64 pixel alignment, in at least some cases. Make
this configurable per generation.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 17:21:38 +0000 (12:21 -0500)]
freedreno/ir3: don't offset inloc by 8
On a3xx/a4xx, the SP_VS_VPC_DST_REG.OUTLOCn is offset by 8, so we used
to add this offset into fs->inputs[n].inloc. But a5xx drops this extra
offset-by-8. So instead make inloc zero based and add the offset when
we emit OUTLOCn values (for the gen's that need the offset).
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 17:10:23 +0000 (12:10 -0500)]
freedreno/a3xx: use new shader linkage helper
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 17:08:16 +0000 (12:08 -0500)]
freedreno/a4xx: use new shader linkage helper
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 23 Nov 2016 14:46:15 +0000 (09:46 -0500)]
freedreno/ir3: add new helper for shader linkage
Helps simplify things on a5xx, where pos/psize get added to the vs-out
map. And anyways, simplifies a3xx and a4xx.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Nicolai Hähnle [Fri, 18 Nov 2016 19:51:56 +0000 (20:51 +0100)]
st/mesa: skip lower_output_reads when possible
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 21 Nov 2016 09:36:50 +0000 (10:36 +0100)]
st/glsl_to_tgsi: swizzle PROGRAM_OUTPUTs correctly in src_register translation
This is required for reading directly from fragment shader stencil and depth
outputs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 18 Nov 2016 19:49:54 +0000 (20:49 +0100)]
gallium: add PIPE_CAP_TGSI_CAN_READ_OUTPUTS
Drivers that support this benefit by saving one lowering pass in the
GLSL-to-TGSI conversion.
radeonsi already supports this because all outputs are stored in temporary
variables before the export (except for TCS outputs, which have always
been readable in TGSI anyway due to their special semantics).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Tue, 29 Nov 2016 23:41:16 +0000 (00:41 +0100)]
ac/nir: Fix out of bounds array access.
With nir_intrinsic_ssbo_atomic_comp_swap we run out of params.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Kristian H. Kristensen [Tue, 29 Nov 2016 06:40:23 +0000 (22:40 -0800)]
aubinator: Add support for enum types
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 05:00:34 +0000 (21:00 -0800)]
intel/genxml: Fix ksp for INTERFACE_DESCRIPTOR_DATA
This one was split across two dwords as "Kernel Start Pointer" and
"Kernel Start Pointer High", which looks like it works when the driver
only accesses "Kernel Start Pointer". This breaks, of course, with BO
offsets > 4G.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:46:05 +0000 (17:46 -0800)]
intel/genxml: Use enum 3D_Logic_Op_Function where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:42:46 +0000 (17:42 -0800)]
intel/genxml: Use blend function and factor enums where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:20:23 +0000 (17:20 -0800)]
intel/genxml: Use enum 3D_Vertex_Component_Control where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:10:57 +0000 (17:10 -0800)]
intel/genxml: Use enum 3D_Stencil_Operation where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:59:46 +0000 (16:59 -0800)]
intel/genxml: Use enum SURFACE_FORMAT where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:44:22 +0000 (16:44 -0800)]
intel/genxml: Use enum 3D_Prim_Topo_Type where applicable
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:38:04 +0000 (16:38 -0800)]
intel/genxml: Use 3D_Compare_Function for gen8+ test functions
When the state fields where shuffled around for gen8, the compare
function enums were downgraded to just uints. Change them to enum
3D_Compare_Function.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:34:08 +0000 (16:34 -0800)]
intel/genxml: Emit genxml enums as C enums
The previous commits got rid of any clashes between #defines and enum
values and we can now emit the genxml enums as debugger friendly C
enums.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:32:20 +0000 (16:32 -0800)]
intel/genxml: Remove duplicate COMPAREFUNCTION values
These values were defined both as an enum and as inline values. Remove
the inline values and reference the 3D_Compare_Function enum instead.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:24:13 +0000 (16:24 -0800)]
intel/genxml: Allow referencing enums in type attributes
This lets us reference enums in the type attribute of a field.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 01:15:14 +0000 (17:15 -0800)]
anv: Emit cherryview SF state without including gen9_pack.h
Cleaner this way and we avoid including gen9_pack.h when we compile with
gen8_pack.h. We also avoid the if (cherryview) condition for non-gen8
gens that don't need it.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:16:48 +0000 (16:16 -0800)]
anv: Don't include two different pack headers
The batch chain logic only needs the pre-gen8 size of
MI_BATCH_BUFFER_START, which seems like something we can make a special
case for. The other two gen7 references, MI_BATCH_BUFFER_END and
MI_NOOP, are the same on all gens.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 29 Nov 2016 00:14:12 +0000 (16:14 -0800)]
intel/genxml: Move enums above structs
We'll need to define them before we can reference them in structs and
instructions. Enums have no dependencies, so move them first in the
file.
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kristian H. Kristensen [Tue, 15 Nov 2016 05:10:11 +0000 (21:10 -0800)]
genxml: Add values for Barycentric Interpolation Mode
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Mon, 28 Nov 2016 01:45:34 +0000 (20:45 -0500)]
anv: remove per-sample shading from TODO
This was done some time ago.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Ilia Mirkin [Sun, 27 Nov 2016 22:39:52 +0000 (17:39 -0500)]
anv: clean up VkPhysicalDeviceFeatures list
Remove duplicate .alphaToOne, add missing .shaderResourceMinLod, and
reorder a few entries to match their vulkan.h order. All the sparse
features are still left out entirely.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Michel Dänzer [Thu, 28 Jul 2016 08:54:49 +0000 (17:54 +0900)]
vulkan/wsi/x11: Destroy Present event context when destroying swapchain
Without this, the X server may accumulate stale Present event contexts
if a client creates and destroys multiple swapchains using the same
window.
v2: Based on Chris Wilson's review:
* Use xcb_present_select_input_checked so that protocol errors
generated by old X servers can be handled gracefully
* Use xcb_discard_reply() instead of free(xcb_request_check())
v3: Rebased on top of this code having been refactored out of anv
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Wed, 2 Nov 2016 03:28:12 +0000 (14:28 +1100)]
glsl: use linked_shaders bitmask to iterate stages for subroutine fields
This should be faster than looping over every stage and null checking, but
will also make the code a bit cleaner when we switch to getting more fields
from gl_program rather than from gl_linked_shader as we can just copy the
pointer and not need to worry about null checking then copying.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Wed, 9 Nov 2016 21:33:50 +0000 (08:33 +1100)]
mesa: optimise interleaved sso validation
Now that we have a linked_stages bitfield we can use this
to check if the program is used at a later stage.
This change is also required to be able to use gl_program
rather than gl_shader_program in the CurrentProgram array.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Mon, 31 Oct 2016 10:16:50 +0000 (21:16 +1100)]
mesa/glsl: add bitmask to track stages a program was linked against
This will be used to enable us to store the current gl_program
rather than gl_shader_program in the gl_pipline_object allowing
us to simplify handing of validation.
Also we should not be depending on _LinkedShader for this information
as it may contain shaders from a failed linking attempt rather than
the current program still in use.
We could also use this mask to iterate over the stages during linking
with _mesa_bit_scan() rather then the current method of NULL checking
each stage.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Ilia Mirkin [Thu, 24 Nov 2016 23:02:31 +0000 (18:02 -0500)]
swr: [rasterizer jit] use signed integer representation for logic op
Instead of (incorrectly) biasing the snorm value to make it look like a
unorm, just use signed integer math.
This fixes arb_color_buffer_float-render GL_RGBA8_SNORM
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 22:51:24 +0000 (17:51 -0500)]
swr: add missing rgbx8_srgb variant
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 22:42:26 +0000 (17:42 -0500)]
swr: reorder renderable formats, add grouping comments
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 19:04:51 +0000 (14:04 -0500)]
swr: use util_copy_framebuffer_state helper
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 18:33:04 +0000 (13:33 -0500)]
swr: enable cubemap arrays
Everything is in place for these.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Sun, 20 Nov 2016 18:31:43 +0000 (13:31 -0500)]
swr: rearrange caps into limits/supported/unsupported groups
I find this a lot more readable and compact - much easier to scan
through the list and see what's on and what's off.
No functional change intended.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Fri, 18 Nov 2016 23:53:05 +0000 (18:53 -0500)]
swr: only store up to the LOD size
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 23 Nov 2016 01:50:00 +0000 (19:50 -0600)]
swr: [rasterizer common] add SwrTrace() and macros
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Marek Olšák [Mon, 28 Nov 2016 00:37:42 +0000 (01:37 +0100)]
radeonsi: don't fetch 8 dwords for samplerBuffer and imageBuffer
The compiler doesn't shrink s_load_dwordx8, so we always wasted 4 SGPRs.
Also, the extraction of the descriptor created some really ugly asm code
with lots of VALU bitwise ops and v_readfirstlane.
Totals from *affected* shaders:
SGPRS: 13880 -> 13253 (-4.52 %)
VGPRS: 15200 -> 15088 (-0.74 %)
Code Size: 499864 -> 459816 (-8.01 %) bytes
Max Waves: 1554 -> 1564 (0.64 %)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 27 Nov 2016 17:13:15 +0000 (18:13 +0100)]
radeonsi: disable XNACK to free 2 SGPRs on APUs
My LLVM commit disables it for dGPUs, but not APUs.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 26 Nov 2016 21:52:12 +0000 (22:52 +0100)]
radeonsi: count and report temp arrays in scratch separately
v2: only do this if debug output of shader dumping is enabled
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Marek Olšák [Sat, 26 Nov 2016 21:44:10 +0000 (22:44 +0100)]
radeonsi: don't try to eliminate trivial VS outputs for PS and CS
PS and CS don't have any param exports, so it's a no-op.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 26 Nov 2016 14:52:05 +0000 (15:52 +0100)]
radeonsi: disable RB+ blend optimizations for dual source blending
This fixes dual source blending on Stoney. The fix was copied from Vulkan.
The problem was discovered during internal testing.
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 26 Nov 2016 14:43:39 +0000 (15:43 +0100)]
radeonsi: set CB_BLEND1_CONTROL.ENABLE for dual source blending
copied from Vulkan
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 26 Nov 2016 14:39:06 +0000 (15:39 +0100)]
radeonsi: always set all blend registers
better safe than sorry
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Nov 2016 22:11:45 +0000 (23:11 +0100)]
radeonsi: set the smallest possible CB_TARGET_MASK
better safe than sorry; set_framebuffer_state always makes this dirty
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Nov 2016 22:28:53 +0000 (23:28 +0100)]
radeonsi: don't print bodies of header-only packets
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Nov 2016 21:55:20 +0000 (22:55 +0100)]
radeonsi: print unknown registers with correct formatting
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Nov 2016 20:19:17 +0000 (21:19 +0100)]
ddebug: fix hang detection with deferred flushes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Thu, 24 Nov 2016 00:35:30 +0000 (00:35 +0000)]
radv: set spi_baryc_cntl.pos_float_location to 0
This fixes:
dEQP-VK.pipeline.multisample_interpolation.offset_interpolate_at_sample_position.*
This should probably be 2 when sample shading is enabled, but I'm
not sure.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 24 Nov 2016 00:18:21 +0000 (00:18 +0000)]
radv: force persample shading when required.
We need to force persample shading when
a) shader uses sample_id
b) shader uses sample_position
c) shader uses sample qualifier.
Also since ps_iter_samples can now change independently of the
rasterizer samples we need to move setting the regs more often.
This fixes:
dEQP-VK.pipeline.multisample_interpolation.centroid_interpolate_at_consistency.*
dEQP-VK.pipeline.multisample_interpolation.centroid_qualifier_inside_primitive.137_191_1.*
dEQP-VK.pipeline.multisample_interpolation.sample_interpolate_at_distinct_values.*
dEQP-VK.pipeline.multisample_interpolation.sample_qualifier_distinct_values.128_128_1.*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 23 Nov 2016 22:25:50 +0000 (22:25 +0000)]
nir: print var binding in dumps.
This only useful for spir-v shaders, but I keep finding myself
having to add it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Engestrom [Tue, 29 Nov 2016 11:40:55 +0000 (11:40 +0000)]
docs: fix small typo
Fixes:
ba28f2136febca32fe56 ("docs: add note about r-b/other tags when resending")
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Matt Turner [Mon, 28 Nov 2016 21:34:55 +0000 (13:34 -0800)]
i965/sched: Schedule trivial blocks.
In commit
45cd76e342d1e8e schedule_instructions(bblock_t *) began
setting bblock_t::cycle_count, but that function was not called on
trivial blocks.
Remove the code to skip trivial blocks so that cycle_count is set.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Mon, 28 Nov 2016 21:29:45 +0000 (13:29 -0800)]
i965/sched: Make 'time' a local variable.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Mon, 28 Nov 2016 21:25:01 +0000 (13:25 -0800)]
i965/cfg: Initialize bblock_t::cycle_count.
schedule_instructions(bblock_t *) isn't called on blocks with a single
instruction, and since it is the only thing that set cycle_count,
cycle_count would be uninitialized.
A non-empty block with bblock_t::cycle_count == 0 is arguably a bug.
That'll be fixed in the next commit.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Mon, 28 Nov 2016 21:24:04 +0000 (13:24 -0800)]
i965/cfg: Initialize cfg_t::cycle_count.
This reverts commit
b4001af1744a02f472bd1204458662088307981b.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Bas Nieuwenhuizen [Tue, 29 Nov 2016 07:54:05 +0000 (08:54 +0100)]
ac/nir: Fix accessing an unitialized value.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 29 Nov 2016 07:51:00 +0000 (08:51 +0100)]
radv: Initialize the shader_stats_dump flag.
Meta was using it before it was set. I suspect we typically don't
want to dump meta shaders, so just set it to false in the beginning.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Tue, 15 Nov 2016 23:47:49 +0000 (15:47 -0800)]
vc4: Add a note for the future about texture latency calculation.
Debugging a shader-db reported cycle count regression from the tex
coalescing, I eventually figured out that the texture latencies were
totally bogus. Really fixing it will probably involve mirroring
vc4_qir_schedule.c's texture fifo management here.
Eric Anholt [Tue, 15 Nov 2016 22:48:43 +0000 (14:48 -0800)]
vc4: Add support for coalescing ALU ops into tex_[srtb] MOVs.
This isn't as complete as I would like (can't merge interpolation because
of the implicit r5 dependency, doesn't work with control flow), but this
was cheap and easy.
Improves 3DMMES Taiji performance by 1.15353% +/- 0.299896% (n=29, 16)
total instructions in shared programs: 99810 -> 99059 (-0.75%)
instructions in affected programs: 10705 -> 9954 (-7.02%)