Patrice Chotard [Tue, 5 Sep 2017 09:04:25 +0000 (11:04 +0200)]
ARM: dts: STiH410: set DWC3 dual role mode to peripheral
On STi 96boards, configure by default the micro USB connector
(managed by DWC3 hardware block) in peripheral mode.
This will allow to use fastboot feature.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 5 Sep 2017 09:04:24 +0000 (11:04 +0200)]
usb: dwc3: Add dwc3 glue driver support for STi
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.
Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 5 Sep 2017 09:04:23 +0000 (11:04 +0200)]
STiH410-B2260: enable USB, fastboot, reset, PHY related flags
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 5 Sep 2017 09:04:22 +0000 (11:04 +0200)]
STiH410-B2260: enable USB Host Networking
Enable USB Host Networking support by enabling Ethernet/USB
adaptors support and by enabling some BOOTP flags
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 5 Sep 2017 09:04:21 +0000 (11:04 +0200)]
usb: phy: Add STi USB2 PHY
This is the generic phy driver for the picoPHY ports
used by USB2/1.1 controllers. It is found on STiH407 SoC
family from STMicroelectronics.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 5 Sep 2017 09:04:20 +0000 (11:04 +0200)]
mmc: sti_sdhci: Use reset framework
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 5 Sep 2017 09:04:19 +0000 (11:04 +0200)]
ARM: dts: stih410-family: Add missing reset_names for mmc1 node
reset-names property is needed to use the reset
API for STi sdhci driver.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 5 Sep 2017 09:04:18 +0000 (11:04 +0200)]
mmc: sti_sdhci: Rework sti_mmc_core_config()
Use struct udevice* as input parameter. Previous
parameters are retrieved through plat and priv data.
This to prepare to use the reset framework.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tuomas Tynkkynen [Fri, 1 Sep 2017 14:26:02 +0000 (17:26 +0300)]
pci: Remove unnecessary 'default n' from Kconfig
'default n' is the default anyway so it doesn't need to be specified
explicitly, and the rest of the file doesn't specify it either anywhere.
Drop it.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tuomas Tynkkynen [Fri, 1 Sep 2017 14:26:01 +0000 (17:26 +0300)]
pci: layerscape: Remove unused field 'hose' from struct ls_pcie
This field is no longer used since the DM conversion. Drop it.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tuomas Tynkkynen [Fri, 1 Sep 2017 14:26:00 +0000 (17:26 +0300)]
pci: tegra: Remove unused field 'hose' from struct tegra_pcie
This field is no longer used since the DM conversion. Drop it.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tuomas Tynkkynen [Fri, 1 Sep 2017 14:25:59 +0000 (17:25 +0300)]
pci: xilinx: Remove unused field 'hose' from struct xilinx_pcie
This field has never been used as the driver has been DM-based since the
beginning. Drop it.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tuomas Tynkkynen [Fri, 1 Sep 2017 14:25:58 +0000 (17:25 +0300)]
pci: xilinx: Fix doc comments on config space accessors
These take the 'struct udevice *' as an argument, not the
'struct xilinx_pcie *` which is a local variable. Fix the comments to
match the code.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Fri, 22 Sep 2017 11:37:43 +0000 (07:37 -0400)]
fs/fat: Reduce stack usage
We have limited stack in SPL builds. Drop itrblock and move to
malloc/free of itr to move this off of the stack. As part of this fix a
double-free issue in fat_size().
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Rework to use malloc/free as moving this to a global overflows some SH
targets.
Tom Rini [Thu, 21 Sep 2017 11:51:20 +0000 (07:51 -0400)]
Merge branch 'next' of git://git.denx.de/u-boot-video
rick [Mon, 28 Aug 2017 07:08:01 +0000 (15:08 +0800)]
nds32: spi: Support spi dm driver.
Support spi driver and can detect MX25U1635E flash on AE3XX board.
Verification:
sf probe 0:0
50000000 0
spi_flash_std_probe(sf_Probr.c)
spi_flash_probe_slave(sf_Probr.c)
SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
NDS32 # sf test 0x100000 0x1000
SPI flash test:
0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
1 check: 15 ticks, 266 KiB/s 2.128 Mbps
2 write: 21 ticks, 190 KiB/s 1.520 Mbps
3 read: 11 ticks, 363 KiB/s 2.904 Mbps
Test passed
0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
1 check: 15 ticks, 266 KiB/s 2.128 Mbps
2 write: 21 ticks, 190 KiB/s 1.520 Mbps
3 read: 11 ticks, 363 KiB/s 2.904 Mbps
Signed-off-by: rick <rick@andestech.com>
rick [Mon, 28 Aug 2017 07:13:09 +0000 (15:13 +0800)]
nds32: board: Support SPI driver.
Add spi dts node and enable spi dm flash config.
Signed-off-by: rick <rick@andestech.com>
rick [Mon, 28 Aug 2017 02:09:01 +0000 (10:09 +0800)]
nds32: mtd: add spi flash id MX25U16335E.
To support MACRONIX MX25U1635E 16M-BIT flash.
Signed-off-by: rick <rick@andestech.com>
rick [Tue, 29 Aug 2017 02:15:05 +0000 (10:15 +0800)]
nds32: ftmac100: Fix write mac addr fail problem.
After soft reset complete, write mac address immediately will fail.
Add delay to work around this problem.
Signed-off-by: rick <rick@andestech.com>
rick [Tue, 29 Aug 2017 02:12:02 +0000 (10:12 +0800)]
nds32: ftmac100 support cache enable.
Enable cache and ftmac100 performance can be improved.
Signed-off-by: rick <rick@andestech.com>
rick [Tue, 29 Aug 2017 02:09:00 +0000 (10:09 +0800)]
nds32: ftmac100: support cache enable.
Add cache inval and flush when rx and tx.
Signed-off-by: rick <rick@andestech.com>
rick [Mon, 28 Aug 2017 05:31:48 +0000 (13:31 +0800)]
nds32: bootm: Fix warning of struct tag_serialnr declared
move #include <asm/setup.h> from bootm.c to bootm.h
Signed-off-by: rick <rick@andestech.com>
rick [Mon, 28 Aug 2017 03:04:40 +0000 (11:04 +0800)]
nds32: board: Fix andestech adp-ae3xx.c make fail problem.
Add #include <asm/mach-types.h> to fix it.
Signed-off-by: rick <rick@andestech.com>
Tom Rini [Wed, 20 Sep 2017 16:32:34 +0000 (12:32 -0400)]
Merge git://www.denx.de/git/u-boot-imx
Fabio Estevam [Tue, 5 Sep 2017 23:46:40 +0000 (20:46 -0300)]
mx6sabresd: Add Serial Download Protocol support
Add Serial Download Protocol support (SDP), which allows loading
SPL and u-boot.img via imx_usb_loader tool as explained in
doc/README.sdp.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Tue, 5 Sep 2017 23:46:39 +0000 (20:46 -0300)]
toradex: imx6: Move g_dnl_bind_fixup() into common SPL code
Instead of having every board file to add its own g_dnl_bind_fixup()
implementation, move it to the common imx6 SPL code.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Ćukasz Majewski <lukma@denx.de>
Ian Ray [Tue, 22 Aug 2017 06:03:54 +0000 (09:03 +0300)]
board: ge: bx50v3: set eth0 MAC address
Define i2c mux configuration. Add new vpd_reader which is used to read
vital product data. Read VPD from EEPROM and set eth0 MAC address.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Jose Alarcon <jose.alarcon@ge.com>
Dennis Gilmore [Thu, 24 Aug 2017 15:49:43 +0000 (10:49 -0500)]
detect and setup solidrun hummingboard2
The hummingboard2 is slightly different to the cubox i and to the
hummingboard. The GPIO pin info to probe came from solidruns
for of u-boot on github.
https://github.com/SolidRun/u-boot-imx6/blob/imx6/board/solidrun/mx6_cubox-i/mx6_cubox-i.c#L569-L589
I have tested on a hummingboard-edge witha imx6 solo and 512mb of
ram.
Signed-off-by: Dennis Gilmore <dgilmore@redhat.com>
Tom Rini [Mon, 18 Sep 2017 19:44:57 +0000 (15:44 -0400)]
Merge git://git.denx.de/u-boot-rockchip
Klaus Goger [Fri, 15 Sep 2017 12:46:04 +0000 (14:46 +0200)]
rockchip: puma_rk3399: increase serialno_str size
Increase serialno_str to 17 bytes so it can hold the 16 bytes long serial
nummer and the terminating null byte added by snprintf.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Kever Yang [Thu, 7 Sep 2017 03:20:51 +0000 (11:20 +0800)]
rockchip: ram: rk3399: update reg map for of-platdata
After Simon's patch, the dtoc can work with 64bit address,
so we need to fix reg number for it.
Depend on Simon's patch set:
https://patchwork.ozlabs.org/cover/807266/
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Thu, 7 Sep 2017 03:20:50 +0000 (11:20 +0800)]
rockchip: sdhci: update reg map for of-platdata
After Simon's patch, the dtoc can work with 64bit address,
so we need to fix reg number for it.
Depend on Simon's patch set:
https://patchwork.ozlabs.org/cover/807266/
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 14 Aug 2017 17:05:33 +0000 (19:05 +0200)]
rockchip: dts: rk3368: reduce the number of nodes seen in TPL
The RK3368 TPL stage always returns to the BootROM, so it has no need
for the eMMC, SD and SPI nodes. This marks those nodes (that should
be included in SPL, but not TPL) as 'u-boot,dm-spl'.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Mon, 14 Aug 2017 17:05:32 +0000 (19:05 +0200)]
rockchip: rk3368: adjust DMC driver for 32/64bit-aware OF_PLATDATA
With the new 32/64bit-aware dtoc, the type of reg is fdt64_t and the
OF_PLATDATA structure layout changes. This adjusts the DMC driver for
the RK3368 to track these changes.
For the time being (i.e. until regmap_init_mem_platdata works for the
64bit case), we won't use regmap_init_mem_platdata here and simply
access of_plat.reg[] directly.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Mon, 14 Aug 2017 17:05:31 +0000 (19:05 +0200)]
rockchip: timer: update for 32/64bit-aware OF_PLATDATA
With dtoc emitting fdt64_t for addresses (and region sizes), the array
indices for accessing the reg[] array needs to be adjusted. This
adjusts the Rockchip DM timer driver to correctly handle OF_PLATDATA
given this new structure layout.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 12 Sep 2017 15:32:29 +0000 (17:32 +0200)]
rockchip: defconfig: puma-rk3399: enable OF_LIVE (live tree)
With the critical drivers ready for switching to a live tree, we can
now enable it in the defconfig for the RK3399-Q7.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 12 Sep 2017 15:32:26 +0000 (17:32 +0200)]
rockchip: efuse: change to use dev_read_addr_ptr
With the dev_read_addr_ptr function available, we can change the
efuse driver to use it (and eliminate the explicit type-cast).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 12 Sep 2017 15:32:24 +0000 (17:32 +0200)]
rockchip: clk: rk3399: Convert to livetree
Update the clock driver for the RK3399 to support a live device tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 12 Sep 2017 15:30:57 +0000 (17:30 +0200)]
rockchip: dts: rk3399-puma: replace 'rockchip, vbus-gpio' with fixed regulator
On the RK3399-Q7, we need to turn on the on-module USB hub before using the
USB host interfaces (only the OTG interface is directly connected to the edge
connector). This drops the deprecated 'rockchip,vbus-gpio' property and uses
a fixed regulator to turn on the USB hub.
References: 26a8b80 "usb: host: xhci-rockchip: use fixed regulator to control vbus"
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 12 Sep 2017 15:30:56 +0000 (17:30 +0200)]
rockchip: clk: rk3399: add clk_enable function and support USB HOST0/1
The generic ehci-driver (ehci-generic.c) will try to enable the clocks
listed in the DTSI. If this fails (e.g. due to clk_enable not being
implemented in a driver and -ENOSYS being returned by the clk-uclass),
the driver will bail our and print an error message.
This implements a minimal clk_enable for the RK3399 and supports the
clocks mandatory for the EHCI controllers; as these are enabled by
default we simply return success.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Mon, 4 Sep 2017 12:32:58 +0000 (20:32 +0800)]
rockchip: rk3368: add the missing target and pinctrl config for sheep board
Add the missing target and pinctrl config for rk3368 sheep board
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Andy Yan [Mon, 4 Sep 2017 12:32:23 +0000 (20:32 +0800)]
rockchip: rk3368: add ENV_MEM_LAYOUT to extra env settings
Add the ENV_MEM_LAYOUT_SETTINGS to CONFIG_EXTRA_ENV_SETTINGS
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Jagan Teki [Tue, 12 Sep 2017 11:45:47 +0000 (17:15 +0530)]
rk3288: Add Vyasa initial board support
This patch adds support for Vyasa RK3288 initial board
from Amarula Solutions.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Tue, 29 Aug 2017 16:24:05 +0000 (18:24 +0200)]
rockchip: rk3399: spl: remove hard-coded addresses for GRF and SGRF
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL
enabled: this allows the use of syscon to retrieve the addresses of
GRF and SGRF (except for the early debug UART setup, which runs so
early that the device-model is not initialised).
This removes the hard-coded addresses and goes through syscon to
retrieve the base-addresses of GRF and SGRF. After that, we use
the structure definitions to locate the respective registers.
In addition to this, the inclusion of header files is also cleaned up:
- all headers are included at the beginning (there was a spurious
inclusion of the grf header from within a function)
- all #include statements for unused headers are removed
- the remaining #include statements are sorted (while keeping common.h
included in front)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:27 +0000 (22:04 +0200)]
rockchip: lion-rk3368: defconfig: resync w/ OF_LIVE and BOOTSTAGE enabled
This adds OF_LIVE and BOOTSTAGE support for the RK3368-uQ7 and
regenerates the defconfig (picking up a few changes/reorderings) from
upstream Kconfig changes.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:26 +0000 (22:04 +0200)]
rockchip: dts: rk3368-lion: add /chosen/tick-timer
To support bootstage recording, we want to mark our DM timer as the
tick-timer; this triggers the support for 'trying harder' to read the
timer in the Rockchip DM timer driver, even if the device model isn't
ready yet.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:25 +0000 (22:04 +0200)]
rockchip: gpio: remove outdated/misleading comment
Remove a comment claiming that this driver only supports the RK3288,
as we also use it on the RK3368, RK3399 and (most likely) on other
variants.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 2
- use the dev_read_addr_ptr function in rk_gpio.c
Philipp Tomsich [Mon, 11 Sep 2017 20:04:24 +0000 (22:04 +0200)]
rockchip: gpio: convert to livetree
Update the Rockchip GPIO-bank driver to support a live tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 2
- use the dev_read_addr_ptr function in rk_gpio.c
Philipp Tomsich [Mon, 11 Sep 2017 20:04:23 +0000 (22:04 +0200)]
rockchip: i2c: Convert to livetree
Update the Rockchip I2C driver to support livetree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Heiko Schocher <hs@denx.de>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:22 +0000 (22:04 +0200)]
rockchip: rk8xx: remove unused header includes
Remove header file includes that have been left over after the
conversion to livetree-support.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:21 +0000 (22:04 +0200)]
rockchip: sdhci: Convert to livetree
Update the Rockchip SDHCI wrapper to support a live device tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 2
- use the dev_read_addr_ptr function in rockchip_sdhci.c
Philipp Tomsich [Mon, 11 Sep 2017 20:04:20 +0000 (22:04 +0200)]
rockchip: spi: Convert to livetree
Update the Rockchip SPI driver to support a live device tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:19 +0000 (22:04 +0200)]
rockchip: pinctrl: rk3368: Convert to livetree
Update the pinctrl driver for the RK3368 to support a live device tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:18 +0000 (22:04 +0200)]
rockchip: clk: rk3368: Convert to livetree
Update the clock driver for the RK3368 to support a live device tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 2
- use the dev_read_addr_ptr function in clk_rk3368.c
Philipp Tomsich [Mon, 11 Sep 2017 20:04:17 +0000 (22:04 +0200)]
rockchip: timer: Convert to livetree
Update the Rockchip timer driver to support a live device tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:16 +0000 (22:04 +0200)]
rockchip: timer: implement timer_get_boot_us
To make the Rockchip DM timer driver useful for the timing of
bootstages, we need a few enhancements:
- This implements timer_get_boot_us.
- This avoids reinitialising the timer, if it has already been
set up (e.g. by our TPL and SPL stages). Now, we have a single
timebase ticking from TPL through the full U-Boot.
- This adds support for reading the timer even before the
device-model is ready: we find the timer via /chosen/tick-timer,
then read its address and clock-frequency, and finally read the
timeval directly).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:15 +0000 (22:04 +0200)]
rockchip: mmc: convert to livetree
Update the Rockchip-specific wrapper for the Designware driver to
support a live device tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 2
- use the dev_read_addr_ptr function in rockchip_dw_mmc.c
Philipp Tomsich [Mon, 11 Sep 2017 20:04:14 +0000 (22:04 +0200)]
net: phy: micrel: Convert to livetree
Update the Micrel KSZ90x1 driver for a live tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:13 +0000 (22:04 +0200)]
net: designware: Convert to livetree
Update the Designware Ethernet MAC driver to support a live device
tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:12 +0000 (22:04 +0200)]
dm: core: add dev_read_addr_ptr()
The dev_read_addr_ptr() mimics the behaviour of the devfdt_get_addr_ptr(),
retrieving the first address of the node's reg-property and returning
it as a pointer (or NULL on failure).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:11 +0000 (22:04 +0200)]
dm: timer: handle being called before dm_root is ready
When used with bootstage recording, dm_timer_init may be called
surprisingly early: i.e. before dm_root is ready. To deal with
this case, we explicitly check for this condition and return
-EAGAIN to the caller (refer to drivers/timer/rockchip_timer.c
for a case where this is needed/used).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:10 +0000 (22:04 +0200)]
dm: timer: Convert to livetree
This updates dm_timer_init to support a live tree and deals with
some fallout (i.e. the need to restructure the code such, that we
don't need multiple discontinuous #if CONFIG_IS_ENABLED blocks).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 11 Sep 2017 20:04:09 +0000 (22:04 +0200)]
bootstage: adjust Makefile to allow including bootstage in SPL, but not in TPL
For timing our bootstages on the RK3368, which has a minimal TPL
(and where we consequently don't want to time the bootstages) and a
full-featured SPL (where we can bootstage recording), we need to
adjust the Makefile.
Use the $(SPL_TPL_) macro in the Makefile for bootstage.o
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Klaus Goger [Mon, 11 Sep 2017 19:05:00 +0000 (21:05 +0200)]
rockchip: board: puma_rk3399: update README flash instructions
Puma supports other boot sources then SD-Card. Update README to include
the required steps.
* how to package a SPI-NOR SPL
* how to flash eMMC with rkdeveloptool
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Klaus Goger [Mon, 11 Sep 2017 19:04:59 +0000 (21:04 +0200)]
rockchip: board: lion_rk3368: update README flash instructions
Add a section to the README on how to flash the on-board eMMC
with the rkdeveloptool.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu [Mon, 14 Aug 2017 07:04:28 +0000 (15:04 +0800)]
rockchip: rk322x: Disable integrated macphy for saving power consuming
Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 9 Aug 2017 11:28:03 +0000 (19:28 +0800)]
rockchip: rk322x: enable fastboot to set boot mode tag
To support fastboot "fastboot reboot-bootloader" cmd.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 9 Aug 2017 11:10:13 +0000 (19:10 +0800)]
rockchip: enable rk322x sysreset driver
The sysreset driver for rk322x is ready but not enabled,
add it to Makefile to make sure it's enabled.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
William Wu [Wed, 9 Aug 2017 03:36:28 +0000 (11:36 +0800)]
ARM: dts: rockchip: add USB nodes for evb-rv1108
This patch adds USB OTG/EHCI/OHCI nodes for evb-rv1108 USB ports.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
William Wu [Wed, 9 Aug 2017 03:36:27 +0000 (11:36 +0800)]
configs: rockchip: add USB configs for evb-rv1108 board
This patch adds USB configs to support the USB OTG port(consist
of DWC2 controller) and the USB Host port(consist of EHCI and OHCI
controllers) on evb-rv1108 board, and also support fastboot over
USB and USB mass storage.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Anatolij Gustschin [Mon, 28 Aug 2017 18:58:38 +0000 (20:58 +0200)]
imx6: drop duplicated bss memset and board_init_r() call
bss section is cleared in crt0.S. board_init_r() is also
entered from crt0 code.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Vanessa Maegima [Tue, 29 Aug 2017 16:53:18 +0000 (13:53 -0300)]
pico-imx7d: Add "how to boot with NXP 4.1 Kernel"
The NXP 4.1 kernel needs to boot with secure boot.
Add information on how to enable secure boot mode.
Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Eric Nelson [Thu, 31 Aug 2017 15:34:23 +0000 (08:34 -0700)]
imx: imx7d: remove CamelCase from ENET_xMHz macros
Update these macros to use all upper-case to avoid checkpatch
warnings:
ENET_25MHz,
ENET_50MHz,
ENET_125MHz,
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Stefan Agner [Wed, 13 Sep 2017 21:29:45 +0000 (14:29 -0700)]
imx_common: detect USB serial downloader reliably
The current mechanism using SCR/GPR registers work well when
the serial downloader boot mode has been selected explicitly
(either via boot mode pins or using bmode command). However,
in case the system entered boot ROM due to unbootable primary
boot devices (e.g. empty eMMC), the SPL fails to detect that
it has been downloaded through serial loader and tries to
continue booting from eMMC:
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
The only known way to reliably detect USB serial downloader
is by checking the USB PHY receiver block power state...
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Tom Rini [Mon, 18 Sep 2017 14:58:10 +0000 (10:58 -0400)]
Merge git://git.denx.de/u-boot-uniphier
Stefan Agner [Wed, 13 Sep 2017 21:29:44 +0000 (14:29 -0700)]
imx: add macro to detect whether USB PHY is active
This macro allows to detect whether the USB PHY is active. This
is helpful to detect if the boot ROM has previously started the
USB serial downloader.
The idea is taken from the mfgtool support in the NXP U-Boot:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?h=imx_v2016.03_4.1.15_2.0.0_ga&id=
a352ed3c5184b95c4c9f7468f5fbb5f43de5e412
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Masahiro Yamada [Fri, 15 Sep 2017 12:43:22 +0000 (21:43 +0900)]
ARM: uniphier: add GPU(Mali) reset deassert and clk enable
The driver for Linux is out of control of Socionext, so set up
reset / clock in here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 15 Sep 2017 12:43:21 +0000 (21:43 +0900)]
ARM: uniphier: remove bit field macros from sc64-regs.h
Starting from PXs3, the bit fields of RSTCTRL, CLKCTRL registers
will change every SoC. There is no more point to define bitfields
in the common header file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 15 Sep 2017 12:43:20 +0000 (21:43 +0900)]
ARM: uniphier: merge two defconfig files into uniphier_v7_defconfig
The main difference between Pro4 and PXs2/LD6b is the Denali NAND
IP version. This is now distinguished by DT. Merge the two defconfig
files into uniphier_v7_defconfig.
Update the README.uniphier too.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 15 Sep 2017 12:43:19 +0000 (21:43 +0900)]
mtd: nand: denali: allow to override corrupted revision register
The Denali IP does not update the revision register properly.
Allow to override it with SoC data associated with compatible.
Linux had already finished big surgery of this driver, but I need
to prepare the NAND core before the full sync of the driver.
For now, I am fixing the most fatal problem on UniPhier platform.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Sun, 17 Sep 2017 15:46:51 +0000 (11:46 -0400)]
Merge git://git.denx.de/u-boot-x86
Heinrich Schuchardt [Tue, 12 Sep 2017 01:40:31 +0000 (03:40 +0200)]
x86: ivybridge: remove unused variables
legacy_hole_base_k and legacy_hole_size_k are defined but
not used.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 6 Sep 2017 01:49:50 +0000 (19:49 -0600)]
x86: Enable early timer for chromebook_link
Enable this option for link so that the timer is available earlier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 6 Sep 2017 01:49:49 +0000 (19:49 -0600)]
bootstage: Provide a separate record count setting for SPL
With SPL we often have limited memory and do not need very many bootstage
records. Add a separate Kconfig option for SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 6 Sep 2017 01:49:48 +0000 (19:49 -0600)]
bootstage: Drop unused options
The CONFIG_BOOTSTAGE_USER_COUNT option is no-longer needed since we can now
support any number of user IDs. Also BOOTSTAGE_ID_COUNT is not needed now.
Drop these unused options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 6 Sep 2017 01:49:46 +0000 (19:49 -0600)]
dm: x86: Allow TSC timer to be used before DM is ready
With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.
This will be used by the 'early' timer also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Wed, 6 Sep 2017 01:49:45 +0000 (19:49 -0600)]
board_f: Drop the timer after relocation
Once U-Boot relocates itself the existing driver-model timer (if any) is
no-longer valid until the device is reinitialised. Any use of the device
may cause a crash. To handle this, set the timer to NULL after relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Wed, 16 Aug 2017 05:42:02 +0000 (22:42 -0700)]
x86: Support Intel Cherry Hill board
This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:
- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video console
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:42:01 +0000 (22:42 -0700)]
x86: braswell: Disable PUNIT power configuration for B0 stepping
FSP's built-in UPD configuration enables PUNIT power configuration,
but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:42:00 +0000 (22:42 -0700)]
x86: braswell: Add FSP configuration
Add FSP related configuration for Braswell.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:59 +0000 (22:41 -0700)]
x86: braswell: Add microcode for B0/C0/D0 stepping SoC
This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:58 +0000 (22:41 -0700)]
x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:57 +0000 (22:41 -0700)]
x86: fsp: Update fsp command to show spec 1.1 header
FSP spec 1.1 adds 3 new APIs and their offsets are in the header.
Update the 'fsp hdr' command to show these new entries.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:56 +0000 (22:41 -0700)]
x86: dm: video: Add a framebuffer driver that utilizes VBT
When a VBT is given to an FSP that supports graphics initialization,
the FSP will produce a graphics info HOB that contains all necessary
information for the linear frame buffer of the integrated graphics
device. This adds a DM video driver for it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:55 +0000 (22:41 -0700)]
x86: dts: Include Intel Video BIOS Table in the ROM image
Now that binman is able to recognize the Video BIOS Table entry,
add such one in the u-boot.dtsi.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:54 +0000 (22:41 -0700)]
tools: binman: Add a new entry type for Intel VBT
This adds a new entry type for Intel Video BIOS Table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:53 +0000 (22:41 -0700)]
x86: Add Video BIOS Table (VBT) related Kconfig options
This adds Kconfig options for Video BIOS Table which is normally
required if you are using an Intel FSP firmware that is complaint
with spec 1.1 or later to initialize the integrated graphics device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:52 +0000 (22:41 -0700)]
x86: fsp: Add FSP_GRAPHICS_INFO_HOB
This adds a new HOB type for graphics information introduced in FSP
spec 1.1. When graphics capability is included in FSP and enabled,
FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI
specification which provides information about the graphics mode and
framebuffer.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:51 +0000 (22:41 -0700)]
x86: fsp: Update struct common_buf for FSP spec 1.1
FSP spec 1.1 adds one more member to the struct common_buf to
determine the memory size that can be reserved by FSP below "top
of low usable memory" for bootloader usage. This new member uses
the reserved space so that it is still compatible with previous
FSP spec 1.0.
A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also
published when common_buf.tolum_size is valid and non zero.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 16 Aug 2017 05:41:50 +0000 (22:41 -0700)]
x86: tsc: Add Airmont reference clock values
Per the Intel 64 and IA-32 Architecture Software Developer's Manual,
add the reference clock for Intel Atom Processors based on the Airmont
Microarchitecture (Braswell).
This keeps in sync with Linux kernel commit:
6fcb41c: x86/tsc_msr: Add Airmont reference clock values
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>