H. Peter Anvin [Sun, 24 Nov 2013 18:56:49 +0000 (10:56 -0800)]
"make alldeps"
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cyrill Gorcunov [Sun, 10 Nov 2013 07:45:24 +0000 (11:45 +0400)]
insns: Restore back MMX,FPU flags
In commit
9bb987d8e0330429afba42015b1fc7c7ca0d1b16
we had to drop some flags due to flags type used
in nasm code.
Since now flags internal structure is reworked, we
can restore them back.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 9 Nov 2013 18:28:52 +0000 (22:28 +0400)]
Update .gitignore
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 9 Nov 2013 18:28:05 +0000 (22:28 +0400)]
make: Update deps
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 9 Nov 2013 18:16:11 +0000 (22:16 +0400)]
iflag: Start using new instruction flags engine
Here we start using instruction flags generator.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 26 Oct 2013 21:20:42 +0000 (01:20 +0400)]
insns: Introduce insns-flags.pl
It been found that 64 bits for instruction flags is too small,
so instead we start using indirect addressing scheme to keep
instruction flags in bitvectors instead.
Using one bitvector per instruction template entry is wastefull
(especially if vector grow in future, at moment it's 128 bit length),
so we use indirect addressing, which is generated as follow
- read instruction flags from insns.dat
- flag sequence sorted and joined into one key string
- this key string become a hash index
- all hash entries are compacted into one array
- every instruction template uses array offset instead
of flags bitfield
Just for info, at moment we have 195 unique flags combination,
but since instruction template will use index as unsigned
integer, we can use a way more wider combination of flags
in future.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 24 Nov 2013 08:26:35 +0000 (12:26 +0400)]
make: Add 'golden' target
We've 'test' target in toplevel Makefile, lets be
complete and allow to generate "golden" tests from
toplevel as well.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Fri, 22 Nov 2013 03:40:42 +0000 (19:40 -0800)]
bnd: Drop bnd prefix for relaxed short jmp instructions
Reverted the redundant branch instruction patterns for bnd prefix.
And when a relaxed jmp instruction becomes a short (Jb) form,
bnd prefix is not needed because it does not initialize bnd registers.
So in that case, bnd prefix is silently dropped.
BND JMP foo -> drops bnd prefix
BND JMP short foo -> shows an explicit error
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 20 Nov 2013 23:32:52 +0000 (15:32 -0800)]
disp8: Consolidate a logic to get compressed displacement
Consolidated two separate but similar functions in nasm and ndisasm
into a commonly linked source code.
To encode and decode the compressed displacement (disp8*N) for EVEX,
N value should be derived using various conditions.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 20 Nov 2013 02:44:13 +0000 (18:44 -0800)]
disasm: Add suport for bnd registers
MPX uses a new bnd registers and a new mib syntax.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 20 Nov 2013 02:43:04 +0000 (18:43 -0800)]
disasm: Add EVEX decorator syntax
Broadcasting, opmask, embedded rounding and SAE decorators
are not added at proper position.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 15 Nov 2013 21:20:55 +0000 (13:20 -0800)]
disasm: Add ZMM vsib
ZMM registers can be used for vsib index and the number of registers
has been increased to 32.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 15 Nov 2013 21:18:32 +0000 (13:18 -0800)]
disasm: Support EVEX compressed displacement
When tuple type is indicated in the bytecode, disp8 is
treated as a compressed disp and gets calculated back to disp8*N.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Mon, 11 Nov 2013 19:49:10 +0000 (11:49 -0800)]
disasm: Add basic AVX512 support
Disassembler can translate EVEX prefix, count up to 32 vector registers
and recognize new ZMM / opmask registers.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Sat, 9 Nov 2013 01:22:24 +0000 (17:22 -0800)]
disasm: style cleanup
Fix indentation.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 30 Oct 2013 10:12:45 +0000 (03:12 -0700)]
match: Check the number of elements in broadcasting operands
The broadcasting decorator {1to##} must describe exactly how many times
the memory element is repeated in order to clearly match the correct
instruction format.
For example,
vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8} ; good
vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16} ; fail qword * 16 = 1024b
vaddps zmm30,zmm29,DWORD [rcx]{1to16} ; good
vaddps zmm30,zmm29,DWORD [rcx]{1to8} ; fail dword * 8 = 256b
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 30 Oct 2013 10:00:12 +0000 (03:00 -0700)]
match: Improve broadcast opsize matching
Broadcasting operand size is different from the original
operand size because 32b or 64b element is repeated to form a vector.
So when matching a broadcasting operand, opsize should be treated
differently.
The broadcasting element size is specified in the decorator information.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Tue, 29 Oct 2013 00:07:57 +0000 (17:07 -0700)]
Build: Suppress warning messages
Giving a correct printf format specifier supresses the warning message.
And a local pointer variable is initialized with NULL.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Sat, 26 Oct 2013 02:29:53 +0000 (19:29 -0700)]
AVX-512: Add {evex} instruction prefix
For instructions that can be encoded either in VEX or EVEX,
{evex} forces nasm to encode in EVEX.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Thu, 24 Oct 2013 01:39:03 +0000 (18:39 -0700)]
PREFETCHWT1: Add a new instruction flag
PREFETCHWT1 instruction's CPUID was TBD before.
Now it has its new CPUID bit : PREFETCHWT1
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 18 Oct 2013 03:37:26 +0000 (20:37 -0700)]
AVX512: Update instruction group
CPUID bit for vptestnm[dq] changed.
vptestnm[dq]: AVX512CD -> AVX512F
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 8 Nov 2013 21:31:58 +0000 (13:31 -0800)]
MPX: Move BND prefix indication from bytecode to iflags
As BND prefix validity check conflicts with jcc8 prefix,
IF_BND is added for the instruction templates which can have
bnd prefix for preserving the content of bound register.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 8 Nov 2013 19:41:12 +0000 (11:41 -0800)]
MPX: Adapt GAS's mib syntax with an index reg only
GAS uses *1 multiplier for explicitly marking an index register in mib operand.
e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format
So only for mib operands, this is encoded same as gas does.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:59:10 +0000 (19:59 -0700)]
iflags: Use UINT64_C() for 64bit values
UINT64_C() macro is used for iflags as it becomes 64bit.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 03:49:54 +0000 (20:49 -0700)]
SHA: SHA test cases
32bit and 64bit test asm files.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:44:03 +0000 (19:44 -0700)]
SHA: Add SHA instructions
New instruction extensions of SHA family are added.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:42:41 +0000 (19:42 -0700)]
MPX: Add test cases for MPX
MPX test asm files are added. These include all three different styles of
mib syntax (NASM, ICC and gas).
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:38:51 +0000 (19:38 -0700)]
MPX: Add BND prefix for branch instructions
BND prefix is used for adding bounds checking protection
across flow control changes such as call, ret, jmp and jcc calls.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:10:13 +0000 (19:10 -0700)]
MPX: Add MPX instructions
Added MPX instructions and corresponding parser and encoder.
ICC style mib - base + disp and index are separate - is supported.
E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index
As a supplement to NASM style mib - split EA - parser,
omitted base+disp is now treated as 0 displacement.
E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Fri, 27 Sep 2013 23:53:51 +0000 (16:53 -0700)]
disasm: add support for emitting split EA format
Add support for emitting split EA format in the disassembler,
indicated by the MIB instruction flag.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Fri, 27 Sep 2013 23:39:16 +0000 (16:39 -0700)]
parser: support split base,index effective address
Mostly intended for the "mib" expressions in BNDLDX/BNDSTX.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Fri, 27 Sep 2013 00:28:39 +0000 (17:28 -0700)]
parse: factor out mref parsing
Factor out the parsing of an mref from parse_line(). In order to
support the [base,index] syntax we need to be able to parse an mref in
two steps.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Fri, 27 Sep 2013 00:23:08 +0000 (17:23 -0700)]
parser: simplify code by keeping a pointer to the current operand
There is an awful lot of syntax-heavy "result->oprs[operand]" going
on; simplify by making a pointer to the current operand.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Sat, 21 Sep 2013 03:52:11 +0000 (20:52 -0700)]
AVX-512: Add perfomtest-compliant headers to test cases
test/avx512*.asm files are now tested by using perfomtest.pl
Refer to pefomtest help message for the usage.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Cyrill Gorcunov [Sat, 9 Nov 2013 08:02:15 +0000 (12:02 +0400)]
BR3392270: preproc: Handle all token chains in mmacro params range
A typical example is
|
| %macro m0 0-*
| %rep %0
| m0 arg is %1
| %rotate 1
| %endrep
| %endmacro
|
| %macro m1 0-*
| m0 %{1:-1}
| %endmacro
|
| m1 a=b, c=d
If passed with nasm -E the output must be like
m0 arg is a=b
m0 arg is c=d
http://bugzilla.nasm.us/show_bug.cgi?id=3392270
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
H. Peter Anvin [Fri, 8 Nov 2013 23:28:19 +0000 (15:28 -0800)]
Add (redundant) parentheses around bit tests mixed with &&
It is easy to get confused when mixing & and &&, so add redundant
parenteses for clarity.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Jin Kyu Song [Fri, 8 Nov 2013 09:14:39 +0000 (01:14 -0800)]
REX: Set REX bits in accordance with 32-register environment
REX.RXB bits were set for high-8 registers previously.
Since high-16 zmm registers are newly added, those bits should
be set as one bit of binary number of register value.
Similarly EVEX.R'/V'/X should be set in the same manner.
Authored-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Cyrill Gorcunov [Mon, 28 Oct 2013 07:35:55 +0000 (11:35 +0400)]
Revert "make: Remove generated files on clean target"
This reverts commit
b6c7291b3d1f904b20955c3f9829b8cc92801227.
We already have this cleanup stage in "cleaner" target, I managed
to miss it.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 27 Oct 2013 17:15:47 +0000 (21:15 +0400)]
make: Remove generated files on clean target
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
H. Peter Anvin [Thu, 24 Oct 2013 13:17:23 +0000 (14:17 +0100)]
Merge remote-tracking branch 'origin/master'
H. Peter Anvin [Thu, 24 Oct 2013 12:57:57 +0000 (13:57 +0100)]
Makefile.in: always run "make alldeps" when "make dist"
"make dist" (tarball generation) really should include "make alldeps"
so the Makefile dependencies are correct.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Thu, 24 Oct 2013 12:45:06 +0000 (13:45 +0100)]
Run "make alldeps" to update dependencies
H. Peter Anvin [Thu, 24 Oct 2013 12:25:51 +0000 (13:25 +0100)]
Makefile.in: generate manpages for "make dist"
Make sure the "dist" target generates the man pages.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Thu, 24 Oct 2013 12:22:19 +0000 (13:22 +0100)]
Revert "build: Include pregenerated nasm manpages"
This reverts commit
99427bdb6c85c812665f6d7b36ac520a631c5b23.
We don't include generated files in the repository, instead we should
pregenerate them for the tarball generation, just as we do for the
Perl-generated files.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Sat, 19 Oct 2013 19:20:28 +0000 (12:20 -0700)]
macros.pl: Remove superfluous whitespace
Squeeze multiple whitespace characters together, since they have no
semantic function.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Jin Kyu Song [Mon, 7 Oct 2013 21:51:09 +0000 (14:51 -0700)]
iflags: Eliminate perl smart match operator
As smart match operator reuiqres perl version 5.10.1 or later,
it is replaced with grep function.
This part of code is going to be completely removed once iflags
renovataion is done. This commit is a quick fix for a build error.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Cyrill Gorcunov [Thu, 3 Oct 2013 13:21:39 +0000 (17:21 +0400)]
Merge branch 'nasm-2.10.xx'
* nasm-2.10.xx:
coff: Better handling of section redefinition
Marat Dukhan [Thu, 19 Sep 2013 23:19:52 +0000 (19:19 -0400)]
coff: Better handling of section redefinition
Currently, if we try to define an already defined section and specify
section flags, NASM will output "warning: section attributes ignored
on redeclaration of section %SECTIONNAME%".
The patch modifies this behaviour:
1. If the previous section definition differs only in alignment flags,
no warning is generated
2. If the new definition implies larger alignment, it overrides the
previous section alignment
3. If the new definition specifies any section alignment, the content of
the section will be aligned on the new boundary (i.e. the effect is the
same as if there was ALIGN macro)
Signed-off-by: Marat Dukhan <maratek@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
H. Peter Anvin [Thu, 3 Oct 2013 01:25:19 +0000 (18:25 -0700)]
Add support for DZ and RESZ, document the ZWORD keyword
Add the DZ and RESZ pseudoinstructions and add ZWORD to the
documentation.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
H. Peter Anvin [Wed, 2 Oct 2013 21:58:19 +0000 (14:58 -0700)]
NASM 2.11rc1
H. Peter Anvin [Wed, 2 Oct 2013 21:58:02 +0000 (14:58 -0700)]
NASM 2.10rc1
H. Peter Anvin [Wed, 2 Oct 2013 21:28:09 +0000 (14:28 -0700)]
Merge branch 'avx512'
AVX512 is ready enough that it will realistically be in version 2.11.
Add AVX512 to the master branch; for legacy branch maintenance use the
nasm-2.10.xx branch.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cyrill Gorcunov [Sat, 21 Sep 2013 09:14:15 +0000 (13:14 +0400)]
strfunc: Tabs to spaces conversion
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Marat Dukhan [Fri, 20 Sep 2013 22:54:49 +0000 (18:54 -0400)]
coff: Support for section names longer than 8 bytes
http://bugzilla.nasm.us/show_bug.cgi?id=3392233
Signed-off-by: Marat Dukhan <maratek@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Sat, 21 Sep 2013 03:36:19 +0000 (20:36 -0700)]
AVX-512: Fix bugs related to uninitialized variables
Initialized disp8 to avoid a case that disp8 encoded
instead of the actual offset value.
Added a checking routine for basereg value before using it
as an index of array.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Fri, 13 Sep 2013 21:12:57 +0000 (14:12 -0700)]
AVX-512: Added AVX-512PF instructions
Added Prefetch (AVX-512PF) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1.
CPUID feature flag for PREFETCHWT1 is TBD
but PREFETCHWT1 is included in this commit.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Fri, 13 Sep 2013 21:12:56 +0000 (14:12 -0700)]
AVX-512: Add AVX-512ER instructions
Added Exponential and Reciprocal (AVX-512ER) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1.
IF_AVX512 is now shared by all AVX-512* instructions as a bit mask.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Fri, 13 Sep 2013 21:12:55 +0000 (14:12 -0700)]
AVX-512: Add AVX-512CD instructions
Added Conflict Detection (AVX-512CD) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Sat, 7 Sep 2013 04:22:18 +0000 (21:22 -0700)]
AVX-512: Add Pseudo-ops for CMP instructions
Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on.
Test case is also updated to validate them.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Sat, 31 Aug 2013 01:10:36 +0000 (18:10 -0700)]
AVX-512: Reorder instructions in insns.dat
Within a same instruction mnemonic, instructions are reordered
in order of opcode byte value.
Therefore when there are two possible opcode candidates, smaller
opcode is picked now.
e.g.) vmovapd zmm30, zmm29 -> now 28h is used. 29h previously
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Sat, 31 Aug 2013 01:10:35 +0000 (18:10 -0700)]
AVX-512: Fix rounding mode value in EVEX prefix with SAE
If SAE is set, VL(vector length) is implied to be 512.
EVEX.L'L (=EVEX.RC) is set to 00b by default.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 29 Aug 2013 02:15:29 +0000 (19:15 -0700)]
AVX-512: Add test case for opmask instructions
Added K* instructions test cases in test/avx512f.asm.
The previous test case from GNU AS were repeating the same instruction twice,
so the repeated half part is removed.
Changed the python script (gas2nasm.py) to include opmask instructions.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 29 Aug 2013 02:15:28 +0000 (19:15 -0700)]
AVX-512: Remove trailing space and align columns
Cosmetic change
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 29 Aug 2013 02:15:27 +0000 (19:15 -0700)]
AVX-512: Add OPMASK instructions
Added opmask instructions (kandw and etc). Defined KREG and RM_K
aliasing RM_OPMASK and OPMASKREG respectively to make insns.dat
look neat.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 29 Aug 2013 02:15:26 +0000 (19:15 -0700)]
AVX-512: Add IF_SPMASK and fix IF_PFMASK
Defined IF_SPMASK for specific processor types and
fixed IF_PFMASK to mask the exact preferred bits only.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 29 Aug 2013 02:15:25 +0000 (19:15 -0700)]
AVX-512: Fix bug in checking high-16 registers
Register value needs to be checked. Previous patch compared with reg_enum.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 29 Aug 2013 02:15:24 +0000 (19:15 -0700)]
AVX-512: Fix comments
Fixed or purged some old comments and added a comment for a previous patch.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 29 Aug 2013 02:15:23 +0000 (19:15 -0700)]
AVX-512: Remember the position of operand with broadcast or embedded rounding
It was not so straight forward to find the postion of operand that has
a broadcasting, embedded rounding mode or SAE (Suppress All Exceptions)
decorator out from operands types or bytecode.
Remebering the postion of the operand of interest in the parser reduces
the burden that assembler looks through the operands.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Sat, 24 Aug 2013 01:40:49 +0000 (18:40 -0700)]
AVX-512: Add a feature to generate a raw bytecode file
From gas testsuite file, a text file containing raw bytecodes
is useful when verifying the output of NASM.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Wed, 21 Aug 2013 06:50:26 +0000 (23:50 -0700)]
AVX-512: Add a test case for EVEX encoded instructions
This was converted from a gas testsuite.
(gas/testsuite/gas/i386/x86-64-avx512f-intel.d)
A python script that is used for converting is also included.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Tue, 27 Aug 2013 03:28:43 +0000 (20:28 -0700)]
AVX-512: Fix match function to check the range of registers
High-16 registers of XMM and YMM need to be encoded with EVEX not VEX.
Even if all the operand types match with VEX instruction format,
it should use EVEX instead.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Tue, 27 Aug 2013 03:28:42 +0000 (20:28 -0700)]
AVX-512: Change the data type for instruction flags
Increased the size of data type for instruction flags from 32bits to 64bits.
And a new type (iflags_t) is defined for better maintainability.
Bigger data type is needed because more instruction set types are coming
but there were not enough space for them. Since they are not bit masks,
only one instruction set is allowed for each instruction.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Tue, 27 Aug 2013 03:28:41 +0000 (20:28 -0700)]
AVX-512: Fix a bug in calculating Disp8*N value
Fixed a bug that derived an incorrect N value for tuple types of
T2, T4, T8.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Tue, 27 Aug 2013 03:28:39 +0000 (20:28 -0700)]
AVX-512: Find the correct position of the last SIMD op
Since embedded rounding mode is following the last SIMD op,
GPR op should be skipped when finding the last SIMD op.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Tue, 27 Aug 2013 03:28:38 +0000 (20:28 -0700)]
AVX-512: Moved {er} decorator position next to the last SIMD op
This is for following the current syntax used in gas even though
this is not SDM conforming.
According to SDM, {er} should follow the last GPR op not SIMD op.
e.g. SDM : VCVTSI2SD xmm1, xmm2, r/m64{er}
NASM : VCVTSI2SD xmm1, xmm2{er}, r/m64
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 22 Aug 2013 02:29:12 +0000 (19:29 -0700)]
AVX-512: Fix parser to handle opmask decorator correctly
When a memory reference operand is a destination, this could have
an opmask decorator as well.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 22 Aug 2013 02:29:11 +0000 (19:29 -0700)]
AVX-512: Add ZWORD keyword
ZWORD (512 bits) keyword is added
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 22 Aug 2013 02:29:10 +0000 (19:29 -0700)]
AVX-512: Fix instruction match function
When an instruction allows broadcasting, the memory element size is
different from the size of normal memory operation.
This information is provided in a decoflags field, so it should try to
match those properties before it fails.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 22 Aug 2013 02:29:09 +0000 (19:29 -0700)]
AVX-512: Reword comment about opmask decorators
Previous comment was not so clear.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Thu, 22 Aug 2013 02:29:08 +0000 (19:29 -0700)]
AVX-512: Handle curly braces in multi-line macro parameters
Multi-line macro uses curly braces for enclosing a parameter
containing comma(s). Passing curly braces as a part of a parameter
which is already enclosed with braces confuses the macro expander.
Escape character '\' is prefixed in this case.
e.g.) mmacro {1,2,3}, {4,\{5,6\}}
mmacro gets 2 parameters of '1,2,3' and '4,{5,6}'
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Fri, 16 Aug 2013 02:01:25 +0000 (19:01 -0700)]
AVX-512: Add EVEX encoding and new instructions
EVEX encoding support includes 32 vector regs (XMM/YMM/ZMM),
opmask, broadcasting, embedded rounding mode,
suppress all exceptions, compressed displacement.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Tue, 6 Aug 2013 03:46:18 +0000 (20:46 -0700)]
AVX-512: Add support for parsing braces
AVX-512 introduced new syntax using braces for decorators.
Opmask, broadcat, rounding control use this new syntax.
http://software.intel.com/sites/default/files/319433-015.pdf
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Tue, 23 Jul 2013 05:36:13 +0000 (09:36 +0400)]
NASM 2.10.09
Cyrill Gorcunov [Tue, 23 Jul 2013 05:36:00 +0000 (09:36 +0400)]
doc: changes -- Prepare for 2.10.09
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Mon, 22 Jul 2013 06:09:35 +0000 (10:09 +0400)]
build: Include pregenerated nasm manpages
It's been reported that force people to install
asciidoc for man pages generation is not acceptible.
Just ship them pregenerated.
http://bugzilla.nasm.us/show_bug.cgi?id=3392262
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 21 Jul 2013 16:58:43 +0000 (20:58 +0400)]
NASM 2.10.08
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 21 Jul 2013 07:19:27 +0000 (11:19 +0400)]
doc: changes -- Add fixes for VMOVNTDQA, MOVNTDQA, MOVLPD
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 21 Jul 2013 10:45:02 +0000 (14:45 +0400)]
test: Add br978756
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 21 Jul 2013 07:18:01 +0000 (11:18 +0400)]
test: Add br3392259
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 21 Jul 2013 07:37:43 +0000 (11:37 +0400)]
insns: Fix MOVLPD
http://bugzilla.nasm.us/show_bug.cgi?id=978756
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 21 Jul 2013 07:14:04 +0000 (11:14 +0400)]
insns: Fix MOVNTDQA instruction
http://bugzilla.nasm.us/show_bug.cgi?id=3392259
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 21 Jul 2013 07:13:15 +0000 (11:13 +0400)]
insns: Fix VMOVNTDQA instruction
http://bugzilla.nasm.us/show_bug.cgi?id=3392259
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 20 Jul 2013 20:42:47 +0000 (00:42 +0400)]
changes.src: Prepare for 2.10.08
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
H. Peter Anvin [Sat, 20 Jul 2013 00:06:08 +0000 (17:06 -0700)]
BR 3392260: Handle instructions only separated by vector SIB size
There are two instructions (VGATHERQPS, VPGATHERQD) where the only
separation between two forms is the vector length given to the vector
SIB. This means the *matcher* has to be able to distinguish
instructions by vector SIB length and the matcher only operates on the
operands and the instruction flags, not on the bytecode.
Export the vector index-ness into the operand flags and add to the
matcher.
This resolves BR 3392260.
Reported-by: Agner <agner@anger.org>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cyrill Gorcunov [Mon, 15 Jul 2013 21:33:09 +0000 (01:33 +0400)]
parse_line: Shrink code with memset helper
We know that P_none = 0 thus instead of using
for() statement assign them all in one memset
call.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 14 Jul 2013 14:45:48 +0000 (18:45 +0400)]
ea_type: Fix typo in comment
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Thu, 4 Jul 2013 21:33:09 +0000 (01:33 +0400)]
autoconf: Warn a user if no asciidoc/xmlto found
It's been noticed on nasm forum that we don't complain
if no asciidoc/xmlto package installed on a system while
they are required for man pages generation.
So warn a user then, but still allow to build nasm.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Marat Dukhan [Sat, 29 Jun 2013 21:30:44 +0000 (01:30 +0400)]
make: Fix nasm build with MSVC
http://bugzilla.nasm.us/show_bug.cgi?id=3392258
Signed-off-by: Marat Dukhan <maratek@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
MITSUNARI Shigeo [Sat, 22 Jun 2013 22:01:05 +0000 (07:01 +0900)]
insns: Fix vspllw instruction
http://bugzilla.nasm.us/show_bug.cgi?id=3392257
Signed-off-by: MITSUNARI Shigeo <herumi@nifty.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
MITSUNARI Shigeo [Thu, 30 May 2013 06:21:55 +0000 (15:21 +0900)]
insns: Fix vgatherqpd instruction
Signed-off-by: MITSUNARI Shigeo <herumi@nifty.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>