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sim: bfin: move model data into machs.h
[platform/upstream/binutils.git]
/
sim
/
bfin
/
ChangeLog
2011-05-25
Mike Frysinger
sim: bfin: move model data into machs.h
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commitdiff
2011-05-25
Mike Frysinger
sim: bfin: add a performance monitor stub
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diff to current
2011-05-25
Mike Frysinger
sim: bfin: add bf526-0.2/bf54x-0.4 rom regions
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2011-05-14
Mike Frysinger
sim: bfin: allow pushing of SP
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2011-05-14
Mike Frysinger
sim: bfin: implement loop back support in the UARTs
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2011-05-09
Mike Frysinger
sim: bfin: fix UART LSR read-only bit saturation
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2011-04-27
Mike Frysinger
sim: bfin: constify dmac pmap arrays
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2011-04-26
Mike Frysinger
sim: gpio: add output support
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2011-04-26
Mike Frysinger
sim: gpio: update mask a/b signals better
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2011-04-16
Mike Frysinger
sim: bfin: use store buffer with more 32bit insns
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2011-04-15
Mike Frysinger
sim: bfin: handle implicit DISALGNEXCPT with video...
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2011-04-11
Mike Frysinger
sim: bfin: respect the port level on signals to the SIC
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2011-04-11
Mike Frysinger
sim: bfin: add missing GPIO pin 15
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2011-04-01
Mike Frysinger
sim: bfin: add OTP output port
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2011-03-29
Mike Frysinger
sim: bfin: regen configure to include new cfi device
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2011-03-29
Mike Frysinger
sim: bfin: fix sign extension with 16bit acc add insns
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2011-03-27
Mike Frysinger
sim: bfin: handle saturation with RND12 sub insns
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2011-03-26
Mike Frysinger
sim: bfin: add missing VS set with add/sub insns
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2011-03-25
Mike Frysinger
sim: bfin: add hw tracing to gpio/sic port events
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2011-03-25
Mike Frysinger
sim: bfin: fix GPIO logic bugs when processing events
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2011-03-25
Mike Frysinger
sim: bfin: fix clear/set/toggle GPIO handling
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2011-03-24
Mike Frysinger
sim: bfin: document SIC limitation
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2011-03-24
Mike Frysinger
sim: bfin: fix inverted W1C logic
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2011-03-24
Mike Frysinger
sim: bfin: define more UART LSR bits
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2011-03-24
Mike Frysinger
sim: bfin: fix typo in TWI stat reg
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2011-03-24
Mike Frysinger
sim: bfin: update VIT_MAX behavior to match hardware...
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2011-03-24
Mike Frysinger
sim: bfin: always do 16bit sign extension with the...
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2011-03-24
Mike Frysinger
sim: bfin: update AV and AC ASTAT bits with acc negation
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2011-03-24
Mike Frysinger
sim: bfin: fix thinko in SIC pin encoding
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2011-03-24
Mike Frysinger
sim: bfin: allow byteop[123]p src regs to be the same
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2011-03-24
Mike Frysinger
sim: bfin: fix thinko in bfin_gpio bus addresses
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2011-03-17
Mike Frysinger
sim: bfin: check for kill/pread
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2011-03-15
Mike Frysinger
sim: bfin: add GPIO device simulation
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2011-03-15
Mike Frysinger
sim: bfin: fix brace style
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2011-03-15
Mike Frysinger
sim: bfin: handle AZ updates with 16bit adds/subs
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2011-03-15
Mike Frysinger
sim: bfin: skip acc/ASTAT updates for moves
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2011-03-15
Mike Frysinger
sim: bfin: handle AN (negative overflows) in dsp mult...
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2011-03-15
Mike Frysinger
sim: bfin: handle V overflows in dsp mult insns
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2011-03-15
Mike Frysinger
sim: bfin: decode ASTAT on failure
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2011-03-15
Mike Frysinger
sim: bfin: handle saturation with fract multiplications
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2011-03-14
Mike Frysinger
sim: bfin: forgot to cvs add the changelog
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