gas: consistently emit diagnostics for non-zero data emission to .bss/.struct
[external/binutils.git] / opcodes /
2015-12-08 DJ Delorierl78: Enable MULU for all ISAs.
2015-12-07 Alan ModraReorder some power9 insns
2015-12-04 Claudiu ZissulescuFix failures in the GAS testsuite for the ARC architecture.
2015-12-02 Andre VieiraFix ldah being disassembled as ldaexh
2015-11-27 Matthew Wahab[AArch64][PATCH 3/3] Add floating-point FP16 instructions
2015-11-27 Matthew Wahab[AArch64][PATCH 2/3] Adjust a utility function for...
2015-11-27 Matthew Wahab[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating...
2015-11-27 Matthew Wahab[AArch64] Add ARMv8.2 instruction alias REV64.
2015-11-27 Matthew Wahab[AArch64] Add ARMv8.2 instructions BFC and REV64.
2015-11-27 Matthew Wahab[AArch64] Let aliased instructions be their preferred...
2015-11-27 Matthew Wahab[Aarch64] Support an ARMv8.2 system register.
2015-11-23 Tristan Gingoldopcodes: handle mach-o for thumb/arm disambiguation.
2015-11-20 Matthew Wahab[AArch64] Add support for ARMv8.1 Virtulization Host...
2015-11-20 Nick CliftonRemove a if-clause that is redundant because the same...
2015-11-20 Nick CliftonUpdate translations.
2015-11-19 Matthew Wahab[AArch64] Reject invalid immediate operands to MSR PAN
2015-11-17 Nick CliftonFix the disassembly of conditional instructions will...
2015-11-15 Tristan GingoldBump version to 2.26.51
2015-11-12 Peter BergnerAdd assembler, disassembler and linker support for...
2015-11-09 Robert SuchanekMove copy_u.w to MSA64 ASE, remove copy_u.d.
2015-11-02 Nick CliftonDisassemble RX NOP instructions as such.
2015-11-02 Nick CliftonFix disassembly of RX zero-offset register indirect...
2015-10-28 Yao QiPass noaliases_p to aarch64_decode_insn
2015-10-27 Vinay KumarFix RL78 disassembly of DE+offset addressing to always...
2015-10-27 Vinay KumarDisplay system registers by their names when disassembl...
2015-10-27 Vinay KumarFix RL78 disassembly so that SP+OFFSET addressing alway...
2015-10-14 Andreas KrebbelAdd missing changelog entries
2015-10-14 Andreas KrebbelS/390: Fix instruction type of troo, trot, trto, and...
2015-10-08 Nick CliftonFix compile time warning compiling ARC port.
2015-10-07 Yao QiAvoid using 'template' C++ keyword
2015-10-07 Nick CliftonNew ARC implementation.
2015-10-02 Yao Qi[aarch64] expose disas_aarch64_insn and rename it to...
2015-10-02 Yao Qi[aarch64] Remove argument pc from disas_aarch64_insn
2015-09-29 Dominik VogtAdd support for extensions in the .machine pseudoop...
2015-09-28 Nick CliftonUpdare French translation for binutils and German trans...
2015-09-28 Tom RixPatches for illegal ppc 500 instructions
2015-09-25 jamesbowmanThe FT32's disassembly of 10-bit literals has the incor...
2015-09-23 Nick CliftonFix compile time warnings generated when compiling...
2015-09-22 Nick CliftonEnhance the RX disassembler to detect and report bad...
2015-09-22 Anton Blanchardopcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics
2015-09-10 Andreas KrebbelS/390: Fix instruction format of crj*, clrj*, and clgrj*.
2015-09-10 Andreas KrebbelS/390: Remove F_20 and FE_20. Adjust comments.
2015-09-10 Andreas KrebbelS/390: Fix MASK_RIE_R0PI and MASK_RIE_R0PU.
2015-09-09 Andreas KrebbelS/390: Remove trailing zeros on 4-bytes opcodes.
2015-09-09 Andreas KrebbelS/390: Fix opcode of ppno.
2015-08-25 Jose E. MarchesiSupport for the sparc %pmcdper privileged register.
2015-08-24 Jan StancekFix the partial disassembly of a broken three byte...
2015-08-21 Alexander FominPR binutils/18257: Properly decode x86/Intel mask instr...
2015-08-17 Alan ModraTrailing space in opcodes/ generated files
2015-08-13 Andre VieiraFixes for unpredictable nops and 26-bit versions of...
2015-08-12 Simon Dardis[MIPS] Map 'move' to 'or'.
2015-08-12 H.J. LuRemove trailing spaces in opcodes
2015-08-11 Nick CliftonFix the disassembly of the AArch64 SIMD EXT instruction.
2015-08-10 Robert SuchanekAdd SIGRIE instruction for MIPS R6
2015-08-07 Amit PawarRemove CpuFMA4 support from CPU_ZNVER1_FLAGS.
2015-07-30 H.J. LuProperly disassemble movnti in Intel mode
2015-07-27 H.J. LuRegenerate configure files
2015-07-23 Alan ModraFix ubsan signed integer overflow
2015-07-22 H.J. LuFix memory operand size for vcvtt?ps2u?qq instructions
2015-07-16 Alessandro MarzocchiUpdates the ARM disassembler's output of floating point...
2015-07-14 H.J. LuSync config/warnings.m4 with GCC
2015-07-10 Alan ModraAdd missing changelog entries
2015-07-03 Alan ModraRemove ppc860, ppc750cl, ppc7450 insns from common...
2015-07-01 Sandra LoosemoreOpcodes and assembler support for Nios II R2
2015-06-30 Amit PawarAdd support for monitorx/mwaitx instructions
2015-06-22 Peter BergnerPPC sync instruction accepts invalid and incompatible...
2015-06-22 Nick CliftonStop "objdump -d" from disassembling past a symbolic...
2015-06-19 Peter BergnerAllow for optional operands with non-zero default values.
2015-06-16 Matthew Wahab[AArch64] Support id_mmfr4 system register
2015-06-16 Szabolcs NagyFixes a compile time warnng about left shifting a negat...
2015-06-12 Peter BergnerRemove unused MTMSRD_L macro and re-add accidentally...
2015-06-05 Peter BergnerAdd hwsync extended mnemonic.
2015-06-04 Nick CliftonFixes the check for emulated MSP430 instrucrtions that...
2015-06-02 Matthew Wahab[ARM] Support for ARMv8.1 Adv.SIMD extension
2015-06-02 Matthew Wahab[ARM] Add support for ARMv8.1 PAN extension
2015-06-02 Matthew Wahab[ARM] Rework CPU feature selection in the disassembler
2015-06-02 Matthew Wahab[AArch64] Support for ARMv8.1a Adv.SIMD instructions
2015-06-02 Matthew Wahab[AArch64] Support for ARMv8.1a Limited Ordering Regions...
2015-06-01 Matthew Wahab[AArch64][libopcode] Add support for PAN architecture...
2015-06-01 Jan Beulichx86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}
2015-06-01 Jan Beulichx86/Intel: disassemble vcvt{,u}si2s{d,s} with correct...
2015-06-01 Jan Beulichx86/Intel: accept mandated operand order for vcvt{...
2015-05-18 H.J. LuRemove Disp32 from AMD64 direct call/jmp
2015-05-15 H.J. LuSupport AMD64/Intel ISAs in assembler/disassembler
2015-05-15 Peter BergnerFix some PPC assembler errors.
2015-05-13 H.J. LuAdd missing ChangeLog entries for PR binutis/18386
2015-05-11 H.J. LuRemove Disp16|Disp32 from 64-bit direct branches
2015-05-11 H.J. LuAdd Intel MCU support to opcodes
2015-05-09 H.J. LuIgnore 0x66 prefix for call/jmp/jcc in 64-bit mode
2015-04-30 DJ DelorieMake RL78 disassembler and simulator respect ISA for...
2015-04-29 Nick CliftonUpdated translations for various binutils components.
2015-04-27 Peter Bergneropcodes/
2015-04-27 Andreas KrebbelS/390: Fixes for z13 instructions.
2015-04-23 Jan Beulichx86: disambiguate disassembly of certain AVX512 insns
2015-04-15 H.J. LuRemove the unused PREFIX_UD_XXX
2015-04-15 H.J. LuCheck dp->prefix_requirement instead
2015-04-15 H.J. LuHandle invalid prefixes for rdrand and rdseed
2015-04-15 H.J. LuReplace mandatory_prefix with prefix_requirement
2015-04-15 Renlin Li[ARM] Disassembles SSAT and SSAT16 instructions incorre...
2015-04-06 Ilya Tocarx86: Use individual prefix control for each opcode.
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