aarch64: Add SVE2.1 Contiguous load/store instructions.
[platform/upstream/binutils.git] / opcodes /
2024-01-15 Srinath Parvathaneniaarch64: Add SVE2.1 Contiguous load/store instructions.
2024-01-15 Srinath ParvathaneniPATCH 5/6][Binutils] aarch64: Add SVE2.1 fmin and fmax...
2024-01-15 Srinath Parvathaneniaarch64: Add SVE2.1 dupq, eorqv and extq instructions.
2024-01-15 Srinath Parvathaneniaarch64: Add support for FEAT_SVE2p1.
2024-01-15 Srinath Parvathaneniaarch64: Add support for FEAT_SME2p1 instructions.
2024-01-15 Srinath Parvathaneniaarch64: Add support for FEAT_B16B16 instructions.
2024-01-15 Indu Bhagatopcodes: i386-reg.tbl: Add a comment to reflect depende...
2024-01-15 Indu Bhagatopcodes: x86: new marker for insns that implicitly...
2024-01-15 Indu Bhagatopcodes: gas: x86: define and use Rex2 as attribute...
2024-01-12 Andrew Carlottiaarch64: Remove unused code
2024-01-12 Andrew Carlottiaarch64: Make FEAT_ASMv8p2 instruction aliases always...
2024-01-12 Andrew Carlottiaarch64: Add +xs flag for existing instructions
2024-01-12 Andrew Carlottiaarch64: Add +wfxt flag for existing instructions
2024-01-12 Andrew Carlottiaarch64: Add +rcpc2 flag for existing instructions
2024-01-12 Andrew Carlottiaarch64: Add +jscvt flag for existing fjcvtzs instruction
2024-01-11 Lulu CaiLoongArch: Discard extra spaces in objdump output
2024-01-10 Saurabh Jhagas: aarch64: Add system registers for Debug and PMU...
2024-01-09 Jan Beulichx86: add missing APX logic to cpu_flags_match()
2024-01-09 Srinath Parvathaneniaarch64: ADD FEAT_THE RCWCAS instructions.
2024-01-09 Victor Do Nascimentoaarch64: Regenerate aarch64-*-2.c files
2024-01-09 Victor Do Nascimentoaarch64: Add support for 128-bit system register mrrs...
2024-01-09 Victor Do Nascimentoaarch64: Add xs variants of tlbip operands
2024-01-09 Victor Do Nascimentoaarch64: Implement TLBIP 128-bit instruction
2024-01-09 Victor Do Nascimentoaarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier...
2024-01-09 Victor Do Nascimentoaarch64: Apply narrowing of allowed immediate values...
2024-01-09 Victor Do Nascimentoaarch64: Add support for the SYSP 128-bit system instru...
2024-01-09 Victor Do Nascimentoaarch64: Add support for xzr register in register pair...
2024-01-09 Victor Do Nascimentoaarch64: Expand maximum number of operands from 5 to 6
2024-01-09 Victor Do Nascimentoaarch64: Add +d128 architectural feature support
2024-01-08 srinathaarch64: Add ite feature system registers.
2024-01-07 H.J. Lui386: Correct adcx suffix in disassembler
2024-01-05 Tejas JoshiAdd AMD znver5 processor support
2024-01-05 Jan Beulichx86: corrections to CPU attribute/flags splitting
2024-01-05 Jin MaRISC-V: T-HEAD: Fix wrong instruction encoding for...
2024-01-04 Alan ModraUpdate year range in copyright notice of binutils files
2024-01-04 Lulu CaiLoongArch: Fix some macro that cannot be expanded properly
2023-12-30 Alan ModraLoongArch: Commas inside double quotes
2023-12-29 changjiachenLoongArch: opcodes: Add support for tls le relax.
2023-12-29 Jin MaRISC-V: THEAD: Add 5 assembly pseudoinstructions for...
2023-12-28 Hu, Lin1Support APX JMPABS for disassembler
2023-12-28 Cui, LiliSupport APX pushp/popp
2023-12-28 Mo, ZeweiSupport APX Push2/Pop2
2023-12-28 konglin1Support APX NDD
2023-12-28 Cui, LiliSupport APX GPR32 with extend evex prefix
2023-12-28 Cui, LiliCreated an empty EVEX_MAP4_ sub-table for EVEX instruct...
2023-12-28 Cui, LiliSupport APX GPR32 with rex2 prefix
2023-12-25 Lulu CaiLoongArch: Add new relocs and macro for TLSDESC.
2023-12-24 Alan ModraRe: LoongArch: Add support for <b ".L1"> and <beq,...
2023-12-20 Jens Remuss390: Add suffix to conditional branch instruction...
2023-12-20 Jens Remuss390: Optionally print instruction description in disas...
2023-12-20 Jens Remuss390: Use safe string functions and length macros in...
2023-12-20 Jens Remuss390: Enhance error handling in s390-mkopc
2023-12-20 Jens Remuss390: Provide IBM z16 (arch14) instruction descriptions
2023-12-20 Jens Remuss390: Align letter case of instruction descriptions
2023-12-20 Jens Remuss390: Fix build when using EXEEXT_FOR_BUILD
2023-12-19 Andrea Coralloaarch64: Add FEAT_ITE support
2023-12-19 Andrea Coralloaarch64: Add FEAT_ECBHB support
2023-12-19 Andrea Coralloaarch64: Add FEAT_SPECRES2 support
2023-12-19 Haochen Jiangx86: Remove the restriction for size of the mask regist...
2023-12-18 mengqinggangLoongArch: Add call36 and tail36 pseudo instructions...
2023-12-15 Jan Beulichrevert "x86: allow 32-bit reg to be used with U{RD...
2023-12-15 Jan Beulichx86: fold assembly dialect attributes
2023-12-15 Jan Beulichx86: Intel syntax implies Intel mnemonics
2023-12-14 Jin MaRISC-V: Fix the wrong encoding and operand of the XThea...
2023-12-14 Cui, LiliRemove redundant Byte, Word, Dword and Qword from insn...
2023-12-13 Cui, LiliMake const_1_mode print $1 in AT&T syntax
2023-12-11 mengqinggangLoongArch: Add support for <b ".L1"> and <beq, $t0...
2023-12-04 Jens Remuss390: Support for jump visualization in disassembly
2023-12-01 Jan Beulichx86: allow 32-bit reg to be used with U{RD,WR}MSR
2023-12-01 Patrick O'NeillRISC-V: Make riscv_is_mapping_symbol stricter
2023-12-01 Nelson ChuRISC-V: Add SiFive custom vector coprocessor interface...
2023-12-01 Christoph MüllnerRISC-V: Zv*: Add support for Zvkb ISA extension
2023-11-30 Patrick O'NeillRISC-V: Avoid updating state until symbol is found
2023-11-27 Jiajie Chenas: Add new estimated reciprocal instructions in LoongA...
2023-11-27 Jiajie Chenas: Add new atomic instructions in LoongArch v1.1
2023-11-24 Jan BeulichRISC-V: drop leftover match_never() references
2023-11-24 Jan Beulichx86: shrink opcode sets table
2023-11-24 Jan Beulichx86: also prefer VEX encoding over EVEX one for VCVTNEP...
2023-11-24 Jan BeulichRISC-V: reduce redundancy in sign/zero extension macro...
2023-11-24 Jan BeulichRISC-V: disallow x0 with certain macro-insns
2023-11-24 Nick CliftonFix building for the s390 target with clang
2023-11-23 Jens Remuss390: Correct prno instruction name
2023-11-23 Jens Remuss390: Add missing extended mnemonics
2023-11-23 Jens Remuss390: Align optional operand definition to specs
2023-11-23 Jens Remuss390: Make operand table indices relative to each other
2023-11-23 Jin MaRISC-V: Add vector permutation instructions for T-Head...
2023-11-23 Jin MaRISC-V: Add vector mask instructions for T-Head VECTOR...
2023-11-23 Jin MaRISC-V: Add reductions instructions for T-Head VECTOR...
2023-11-23 Jin MaRISC-V: Add floating-point arithmetic instructions...
2023-11-23 Jin MaRISC-V: Add fixed-point arithmetic instructions for...
2023-11-23 Jin MaRISC-V: Add integer arithmetic instructions for T-Head...
2023-11-23 Jin MaRISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR...
2023-11-23 Jin MaRISC-V: Add load/store segment instructions for T-Head...
2023-11-23 Jin MaRISC-V: Add load/store instructions for T-Head VECTOR...
2023-11-23 Jin MaRISC-V: Add configuration-setting instructions for...
2023-11-23 Jin MaRISC-V: Add CSRs for T-Head VECTOR vendor extension
2023-11-21 Jan-Benedict Glaw[opcodes] ARC + PPC: Fix -Walloc-size warnings
2023-11-17 Jan Beulichx86: CPU-qualify {disp16} / {disp32}
2023-11-16 Srinath Parvathaneniaarch64: Add support for VMSA feature enhancements.
2023-11-16 Srinath Parvathaneniaarch64: Add new AT system instructions.
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