PR24798, buffer overflow in process_cu_tu_index
[external/binutils.git] / opcodes /
2019-04-27 Andrew Bennett[MIPS] Add load-link, store-conditional paired instructions
2019-04-24 John DarringtonS12Z: Opcodes: Handle bit map operations with non-canon...
2019-04-24 John DarringtonS12Z: s12z-opc.h: Add extern "C" bracketing
2019-04-15 Andre Vieira[binutils, ARM, 16/16] Add support to VLDR and VSTR...
2019-04-15 Andre Vieira[binutils, ARM, 15/16] Add support for VSCCLRM
2019-04-15 Andre Vieira[opcodes, ARM, 14/16] Add mode availability to coproces...
2019-04-15 Andre Vieira[binutils, ARM, 13/16] Add support for CLRM
2019-04-15 Andre Vieira[binutils, ARM, 12/16] Scalar Low Overhead loop instruc...
2019-04-15 Andre Vieira[binutils, ARM, 11/16] New BFCSEL instruction for Armv8...
2019-04-15 Andre Vieira[binutils, ARM, 10/16] BFCSEL infrastructure with new...
2019-04-15 Andre Vieira[binutils, ARM, 9/16] New BFL instruction for Armv8...
2019-04-15 Andre Vieira[binutils, ARM, 8/16] BFL infrastructure with new globa...
2019-04-15 Andre Vieira[binutils, ARM, 7/16] New BFX and BFLX instruction...
2019-04-15 Andre Vieira[binutils, ARM, 6/16] New BF instruction for Armv8...
2019-04-15 Andre Vieira[binutils, ARM, 5/16] BF insns infrastructure with...
2019-04-15 Andre Vieira[binutils, ARM, 3/16] BF insns infrastructure with...
2019-04-15 Andre Vieira[binutils, ARM, 1/16] Add support for Armv8.1-M Mainlin...
2019-04-12 John DarringtonS12Z: opcodes: Replace "operator" with "optr".
2019-04-11 Sudakshina Das[BINUTILS, AArch64, 2/2] Update Store Allocation Tag...
2019-04-11 Sudakshina Das[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction
2019-04-09 Robert Suchanek[MIPS] Add RDHWR with the SEL field for MIPS R6.
2019-04-08 H.J. Lux86: Consolidate AVX512 BF16 entries in i386-opc.tbl
2019-04-07 Alan Modraprint_insn_powerpc tidy
2019-04-07 Alan ModraPR24421, Wrong brackets in opcodes/arm-dis.c
2019-04-05 Xuepeng Guox86: Support Intel AVX512 BF16
2019-04-05 Alan ModraPowerPC bc extended branch mnemonics and "y" hints
2019-04-05 Alan ModraPowerPC disassembler: Don't emit trailing spaces
2019-04-04 Peter BergnerAdd extended mnemonics for bctar. Fix setting of 'at...
2019-03-28 Alan ModraPR24390, Don't decode mtfsb field as a cr field
2019-03-25 Tamar ChristinaArm: Fix Arm disassembler mapping symbol search.
2019-03-25 Tamar ChristinaAArch64: Have -D override mapping symbol as documented.
2019-03-25 Tamar ChristinaAArch64: Fix AArch64 disassembler mapping symbol search
2019-03-25 Tamar ChristinaAArch64: Fix disassembler bug with out-of-order sections
2019-03-19 H.J. Luix86: Disable AVX512F when disabling AVX2
2019-03-18 H.J. Lux86: Optimize EVEX vector load/store instructions
2019-03-12 Andreas KrebbelAdd missing changelogs for previous commits.
2019-03-12 Andreas KrebbelS/390: arch13: Adjust to recent changes
2019-03-12 Andreas KrebbelS/390: arch13: Add instruction descriptions
2019-02-08 Jim WilsonAdd missing ChangeLog files for previous patch.
2019-02-08 Jim WilsonRISC-V: Compress 3-operand beq/bne against x0.
2019-02-07 Tamar ChristinaArm: Backport hlt to all architectures.
2019-02-07 Tamar ChristinaAArch64: Add verifier for By elem Single and Double...
2019-02-07 Nick CliftonUpdated Swedish translation for the opcodes sub-directory
2019-01-31 Andreas KrebbelS/390: Implement instruction set extensions
2019-01-25 Tamar ChristinaAArch64: Add missing changelog for Update encodings...
2019-01-25 Sudi DasAArch64: Update encodings for stg, st2g, stzg and st2zg.
2019-01-25 Sudi DasAArch64: Add new STZGM instruction for Armv8.5-A Memory...
2019-01-25 Sudi DasAArch64: Remove ldgv and stgv instructions from Armv8...
2019-01-23 Nick CliftonUpdated translations for some of the binutils subdirectory.
2019-01-21 Nick CliftonUpdated translations for various binutils subdirectories.
2019-01-20 Chenghua Xu[MIPS] fix typo in mips_arch_choices.
2019-01-19 Nick CliftonChange version to 2.32.51 and regenerate configure...
2019-01-19 Nick CliftonAdd markers for 2.32 branch to NEWS and ChangeLog files.
2019-01-12 Yoshinori SatoAdd RXv3 instructions.
2019-01-09 John DarringtonS12Z: Don't crash when disassembling invalid instructions.
2019-01-09 John DarringtonS12Z: Fix disassembly of indexed OPR operands with...
2019-01-09 Andrew PaprockiAdjust bfd/warning.m4 egrep patterns
2019-01-07 Alan Modras12z regen
2019-01-03 John DarringtonS12Z: opcodes: Separate the decoding of operations...
2019-01-01 Alan ModraUpdate year range in copyright notice of binutils files
2019-01-01 Alan ModraChangeLog rotation
2018-12-28 Alan ModraPR24028, PPC_INT_FMT
2018-12-18 Alan ModraInclude bfd_stdint.h in bfd.h
2018-12-07 Jim WilsonRISC-V: Fix 4-arg add parsing.
2018-12-06 Andrew Burgesssim/opcodes: Allow use of out of tree cgen source directory
2018-12-06 Andrew Burgessopcodes/riscv: Hide '.L0 ' fake symbols
2018-12-03 Jim WilsonRISC-V: Accept version, supervisor ext and more than...
2018-12-03 Egeyar Bagcioglu[aarch64] - Only use MOV for disassembly when shifter...
2018-11-29 Jim WilsonRISC-V: Add missing c.unimp instruction.
2018-11-27 Jim WilsonRISC-V: Add .insn CA support.
2018-11-21 John DarringtonS12Z opcodes: Fix bug disassembling certain shift instr...
2018-11-13 Francois H. Theronopcodes/nfp: Fix disassembly of crc[] with swapped...
2018-11-12 Sudakshina Das[BINUTILS, AARCH64, 8/8] Add data cache instructions...
2018-11-12 Sudakshina Das[BINUTILS, AARCH64, 7/8] Add system registers for Memor...
2018-11-12 Sudakshina Das[BINUTILS, AARCH64, 6/8] Add Tag getting instruction...
2018-11-12 Sudakshina Das[BINUTILS, AARCH64, 5/8] Add Tag getting instruction...
2018-11-12 Sudakshina Das[BINUTILS, AARCH64, 4/8] Add Tag setting instructions...
2018-11-12 Sudakshina Das[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instruc...
2018-11-12 Sudakshina Das[BINUTILS, AARCH64, 2/8] Add Tag generation instruction...
2018-11-12 Sudakshina Das[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging...
2018-11-06 Sudakshina Das[BINUTILS, ARM] Add Armv8.5-A to select_arm_features...
2018-11-06 Alan ModraPowerPC instruction mask checks
2018-11-06 Jan Beulichx86: correctly handle VPBROADCASTD with EVEX.W set...
2018-11-06 Jan Beulichx86: correctly handle VMOVD with EVEX.W set outside...
2018-11-06 Jan Beulichx86: correctly handle KMOVD with VEX.W set outside...
2018-11-06 Jan Beulichx86: adjust {,E}VEX.W handling for PEXTR* / PINSR*
2018-11-06 Jan Beulichx86: adjust {,E}VEX.W handling outside of 64-bit mode
2018-11-06 Jan Beulichx86: fix various non-LIG templates
2018-11-06 Jan Beulichx86: allow {store} to select alternative {,}PEXTRW...
2018-11-06 Jan Beulichx86: add more VexWIG
2018-11-06 Jan Beulichx86: XOP VPHADD* / VPHSUB* are VEX.W0
2018-10-23 Andreas KrebbelS/390: Support vector alignment hints
2018-10-22 John DarringtonS12Z: Disassembly: Fallback to show the address if...
2018-10-19 Tamar ChristinaArm: Fix disassembler crashing on -b binary when thumb...
2018-10-16 Matthew MalcomsonAArch64: Fix error checking for SIMD udot (by element)
2018-10-10 Jan Beulichx86: fold Size{16,32,64} template attributes
2018-10-09 Sudakshina Das[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS
2018-10-09 Sudakshina Das[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and...
2018-10-09 Sudakshina Das[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction
2018-10-09 Sudakshina Das[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instr...
next