Fix spelling in comments in C source files (gold)
[external/binutils.git] / opcodes /
2016-11-22 Ambrogino ModiglianiFix spelling mistakes in comments in configure scripts
2016-11-22 Jose E. Marchesigas,opcodes: fix hardware capabilities bumping in the...
2016-11-22 Claudiu Zissulescu[ARC] Fix printing 'b' mnemonics.
2016-11-18 Szabolcs Nagy[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
2016-11-18 Szabolcs Nagy[AArch64] Add ARMv8.3 weaker release consistency load...
2016-11-18 Szabolcs Nagy[AArch64] Add ARMv8.3 javascript floating-point convers...
2016-11-18 Szabolcs Nagy[AArch64] Add ARMv8.3 combined pointer authentication...
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 combined pointer authentication...
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 PACGA instruction
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 single source PAC instructions
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 pointer authentication key registers
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 instructions which are in the...
2016-11-11 Szabolcs Nagy[AArch64] Increase max_num_aliases in aarch64-gen
2016-11-09 H.J. LuX86: Remove the .s suffix from EVEX vpextrw
2016-11-09 H.J. LuUpdate opcodes/ChangeLog
2016-11-09 H.J. LuX86: Merge AVX512F vmovq
2016-11-08 H.J. LuX86: Remove the THREE_BYTE_0F7A entry
2016-11-07 H.J. LuX86: Properly handle bad FPU opcode
2016-11-04 Andrew Burgessarc/nps400: Validate address type operands correctly
2016-11-03 Graham Markallarc: Implement NPS-400 dcmac instruction
2016-11-03 Andrew Burgessarc: Change max instruction length to 64-bits
2016-11-03 Graham Markallarc: Swap highbyte and lowbyte in print_insn_arc
2016-11-03 Graham Markallarc: Replace ARC_SHORT macro with arc_opcode_len function
2016-11-03 Andrew Burgessarc/opcodes/nps400: Fix some instruction masks
2016-11-03 H.J. LuX86: Reuse opcode 0x80 decoder for opcode 0x82
2016-11-03 H.J. LuX86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
2016-11-03 H.J. LuX86: Rename REG_82 to REG_83
2016-11-02 Igor TsimbalistEnable Intel AVX512_4VNNIW instructions
2016-11-02 Igor TsimbalistEnable Intel AVX512_4FMAPS instructions
2016-11-01 Nick CliftonAdd support for RISC-V architecture.
2016-10-21 H.J. LuX86: Remove pcommit instruction
2016-10-20 H.J. LuCheck invalid mask registers
2016-10-18 H.J. LuCheck addr32flag instead of sizeflag for rip/eip
2016-10-18 H.J. LuRemove the remaining SSE5 support
2016-10-18 Maciej W. RozyckiAArch64/opcodes: Correct an `index' global shadowing...
2016-10-17 Cupertino MirandaRemoved pseudo invalid instructions opcodes.
2016-10-14 Claudiu Zissulescu[ARC] Disassembler: fix LIMM detection for short instru...
2016-10-11 Jiong Wang[AArch64] PR target/20666, fix wrong encoding of new...
2016-10-07 Jiong Wang[AArch64] PR target/20667, fix disassembler for the...
2016-10-07 Alan Modrabfd_merge_private_bfd_data tidy
2016-10-05 Alan Modra-Wimplicit-fallthrough warning fixes
2016-10-05 Alan Modra-Wimplicit-fallthrough error fixes
2016-10-05 Alan ModraDon't use boolean OR in arithmetic expressions
2016-09-30 H.J. LuDon't assign alt twice
2016-09-30 Jiong Wang[AArch64] PR target/20553, fix opcode mask for SIMD...
2016-09-29 Alan ModraDisallow 3-operand cmp[l][i] for ppc64
2016-09-26 Vlad ZakharovWhen building target binaries, ensure that the warning...
2016-09-26 Claudiu Zissulescu[ARC] ISA alignment.
2016-09-21 Richard Sandiford[AArch64] Print spaces after commas in addresses
2016-09-21 Richard Sandiford[AArch64] Use "must" rather than "should" in error...
2016-09-21 Richard Sandiford[AArch64] Add SVE condition codes
2016-09-21 Richard Sandiford[AArch64][SVE 31/32] Add SVE instructions
2016-09-21 Richard Sandiford[AArch64][SVE 30/32] Add SVE instruction classes
2016-09-21 Richard Sandiford[AArch64][SVE 29/32] Add new SVE core & FP register...
2016-09-21 Richard Sandiford[AArch64][SVE 28/32] Add SVE FP immediate operands
2016-09-21 Richard Sandiford[AArch64][SVE 27/32] Add SVE integer immediate operands
2016-09-21 Richard Sandiford[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
2016-09-21 Richard Sandiford[AArch64][SVE 25/32] Add support for SVE addressing...
2016-09-21 Richard Sandiford[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
2016-09-21 Richard Sandiford[AArch64][SVE 23/32] Add SVE pattern and prfop operands
2016-09-21 Richard Sandiford[AArch64][SVE 22/32] Add qualifiers for merging and...
2016-09-21 Richard Sandiford[AArch64][SVE 21/32] Add Zn and Pn registers
2016-09-21 Richard Sandiford[AArch64][SVE 20/32] Add support for tied operands
2016-09-21 Richard Sandiford[AArch64][SVE 19/32] Refactor address-printing code
2016-09-21 Richard Sandiford[AArch64][SVE 18/32] Tidy definition of aarch64-opc...
2016-09-21 Richard Sandiford[AArch64][SVE 17/32] Add a prefix parameter to print_re...
2016-09-21 Richard Sandiford[AArch64][SVE 16/32] Use specific insert/extract method...
2016-09-21 Richard Sandiford[AArch64][SVE 15/32] Add {insert,extract}_all_fields...
2016-09-21 Richard Sandiford[AArch64][SVE 14/32] Make aarch64_logical_immediate_p...
2016-09-21 Richard Sandiford[AArch64][SVE 13/32] Add an F_STRICT flag
2016-09-21 Richard Sandiford[AArch64][SVE 02/32] Avoid hard-coded limit in indented...
2016-09-16 Claudiu Zissulescu[ARC] Disassemble correctly extension instructions.
2016-09-15 Peter BergnerModify POWER9 support to match final ISA 3.0 documentation.
2016-09-14 Anton KolesovStop the ARC disassembler from seg-faulting if initiali...
2016-09-12 Andreas KrebbelS/390: Add alternate processor names.
2016-09-12 Patrick SteuerS/390: Fix kmctr instruction type.
2016-09-07 H.J. LuX86: Allow additional ISAs for IAMCU in assembler
2016-08-30 Cupertino MirandaFixed issue with NULL pointer access on header var.
2016-08-26 Jose E. Marchesiopcodes, gas: fix mnemonic of sparc camellia_fl
2016-08-26 Thomas Preud'hommeAdd missing ARMv8-M special registers
2016-08-24 H.J. LuX86: Add ptwrite instruction
2016-08-24 Anton Kolesov[ARC] C++ compatibility for arc-dis.h
2016-08-23 Richard Sandiford[AArch64] Add V8_2_INSN macro
2016-08-23 Richard Sandiford[AArch64] Make more use of CORE/FP/SIMD_INSN
2016-08-23 Richard Sandiford[AArch64] Add OP parameter to aarch64-tbl.h macros
2016-08-01 Andrew Jenner Fix some PowerPC VLE BFD issues and add some...
2016-07-27 Maciej W. RozyckiMIPS/GAS: Implement microMIPS branch/jump compaction
2016-07-27 Graham MarkallBegin implementing ARC NPS-400 Accelerator instructions
2016-07-21 H.J. LuSet BFD_VERSION to 2.27.51
2016-07-20 Claudiu ZissulescuAdd support to the ARC disassembler for selecting instr...
2016-07-13 Maciej W. RozyckiMIPS/opcodes: Address issues with NAL disassembly
2016-07-13 Jose E. Marchesiopcodes,gas: support for the ldtxa SPARC instructions.
2016-07-08 jamesbowmanFT32: adjust disassembly opcode match fields
2016-07-01 Jan Beulichx86: allow suffix-less movzw and 64-bit movzb
2016-07-01 Jan Beulichx86: remove stray instruction attributes
2016-07-01 Jan Beulichx86/Intel: fix operand checking for MOVSD
2016-06-30 Yao QiFix typo in comment
2016-06-28 Richard Sandiford[AArch64] Make register indices be full 64-bit values
2016-06-25 Trevor Saundersremove a few sentinals
2016-06-23 Graham Markall[ARC] Misc minor edits/fixes
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