RISC-V: Add compressed instruction hints, and a few misc cleanups.
[external/binutils.git] / opcodes /
2017-12-20 Jim WilsonRISC-V: Add compressed instruction hints, and a few...
2017-12-19 Tamar ChristinaCorrect disassembly of dot product instructions.
2017-12-19 Tamar ChristinaAdd support for V_4B so we can properly reject it.
2017-12-18 Jan Beulichx86: fold certain AVX and AVX2 templates
2017-12-18 Jan Beulichx86: fold RegXMM/RegYMM/RegZMM into RegSIMD
2017-12-18 Jan Beulichx86: drop FloatReg and FloatAcc
2017-12-18 Jan Beulichx86: replace Reg8, Reg16, Reg32, and Reg64
2017-12-15 Dimitar DimitrovFix disassembly for PowerPC
2017-12-15 Jan Beulichx86: drop stray CheckRegSize uses
2017-12-13 Jim WilsonAdd missing RISC-V fsrmi and fsflagsi instructions.
2017-12-13 Dimitar DimitrovThis patch enables disassembler_needs_relocs for PRU...
2017-12-11 Renlin Li[Binutils][Objdump]Check symbol section information...
2017-12-03 Alan ModraFix "FAIL: VLE relocations 3"
2017-12-01 Peter BergnerUse consistent types for holding instructions, instruct...
2017-11-30 Jan Beulichx86: derive DispN from BaseIndex
2017-11-30 Jan Beulichx86: drop Vec_Disp8
2017-11-29 Stefan StroeSupport --localedir, --datarootdir and --datadir
2017-11-27 Nick CliftonUpdate the simplified Chinese translation of the messag...
2017-11-24 Jan Beulichx86: don't omit disambiguating suffixes from "fi*"
2017-11-23 Igor TsimbalistAdd Disp8MemShift for AVX512 VAES instructions.
2017-11-23 Jan Beulichx86: fix AVX-512 16-bit addressing
2017-11-23 Jan Beulichx86: correct UDn
2017-11-22 Igor TsimbalistRemove Vec_Disp8 field for vgf2p8mulb for AVX flavor.
2017-11-22 Igor TsimbalistUpdate ChangeLog
2017-11-22 Igor TsimbalistRemove Vec_Disp8 from vpcompressb and vpexpandb.
2017-11-22 claziss[ARC] Fix handling of ARCv2 H-register class.
2017-11-21 claziss[ARC] Improve printing of pc-relative instructions.
2017-11-16 Tamar ChristinaAdd new AArch64 FP16 FM{A|S} instructions.
2017-11-16 Tamar ChristinaCorrect AArch64 crypto dependencies.
2017-11-16 Tamar ChristinaAdd assembler and disassembler support for the new...
2017-11-16 Jan Beulichx86: ignore high register select bit(s) in 32- and...
2017-11-15 Jan Beulichx86: use correct register names
2017-11-15 Jan Beulichx86: drop VEXI4_Fixup()
2017-11-15 Jan Beulichx86-64: don't allow use of %axl as accumulator
2017-11-14 Jan Beulichx86: add disassembler support for XOP VPCOM* pseudo-ops
2017-11-14 Jan Beulichx86: add support for AVX-512 VPCMP*{B,W} pseudo-ops
2017-11-14 Jan Beulichx86: string insns don't allow displacements
2017-11-13 Jan Beulichx86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should...
2017-11-09 Tamar ChristinaAdd assembler and disassembler support for the new...
2017-11-09 Tamar ChristinaAdd the operand encoding types for the new Armv8.2...
2017-11-09 Tamar ChristinaAdds the new Fields and Operand types for the new instr...
2017-11-09 Tamar ChristinaSplit the ARM Crypto ISA extensions for AES and SHA1...
2017-11-08 Nick CliftonSplit the AArch64 Crypto instructions for AES and SHA1...
2017-11-08 Jiong WangAdds command line support for Armv8.4-A, via the new...
2017-11-07 Andrew Burgessopcodes/arc: Fix incorrect insn_class for some nps...
2017-11-07 Alan Modrangettext support
2017-11-03 claziss[ARC] Force the disassam to use the hexadecimal number...
2017-11-03 claziss[ARC] Sync opcode data base.
2017-10-25 Alan ModraPR22348, conflicting global vars in crx and cr16
2017-10-24 Andrew WatermanRISC-V: Fix disassembly of c.addi4spn, c.addi16sp,...
2017-10-23 Igor TsimbalistAdd missing ChangeLog entries
2017-10-23 Igor TsimbalistFix the master due to bad regenerated files
2017-10-23 Igor TsimbalistEnable Intel AVX512_BITALG instructions.
2017-10-23 Igor TsimbalistEnable Intel AVX512_VNNI instructions.
2017-10-23 Igor TsimbalistEnable Intel VPCLMULQDQ instruction.
2017-10-23 Igor TsimbalistEnable Intel VAES instructions.
2017-10-23 Igor TsimbalistEnable Intel GFNI instructions.
2017-10-23 Igor TsimbalistEnable Intel AVX512_VBMI2 instructions.
2017-10-18 Eric Botcazou[Visium] Disassemble the operands of the stop instruction.
2017-10-13 James BowmanFT32: support for FT32B processor - part 1
2017-10-09 Andreas KrebbelS/390: Sync with latest POP - 3 new instructions
2017-10-09 Andreas KrebbelS/390: Sync with IBM z14 POP - SI_RD format
2017-10-01 Alexander FedotovAdd new mnemonics for VLE multiple load instructions
2017-09-27 Nick CliftonAdd support for the new names of the RISC-V fmv.x.s...
2017-09-26 Nick CliftonAllow the macw and macl instructions to be used on...
2017-09-25 Sergio Durigan JuniorInitialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm...
2017-09-11 Kuan-Lin Chennds32: Rename __BIT() to N32_BIT().
2017-09-09 H.J. Lux86: Remove restriction on NOTRACK prefix position
2017-08-31 Nick CliftonAdd updated French translations for opcodes and gprof
2017-08-31 James BowmanFT32: improve disassembly readability
2017-08-24 Alexander Fedotov[PowerPC VLE] Add SPE2 and EFS2 instructions support
2017-08-23 Alan Modrappc-opc.c formatting
2017-08-22 Palmer DabbeltRISC-V: Mark "c.nop" as an alias
2017-08-21 Alexander Fedotov[PowerPC VLE] Add LSP (Lightweight Signal Processing...
2017-08-09 Jiong Wang[ARM] Don't warn on REG_SP when used in CRC32 instructions
2017-08-07 H.J. LuMark big and mach with ATTRIBUTE_UNUSED
2017-08-07 Maciej W. RozyckiGDB/opcodes: Remove arch/mach/endian disassembler asser...
2017-07-25 Nick CliftonFix typos in error and option messages in OPCODES library.
2017-07-24 Jiong Wang[AArch64] Fix the bit pattern order in the comments...
2017-07-21 Andreas KrebbelS/390: Support z14 as CPU name.
2017-07-20 Nick CliftonUpdate the German translation for the opcodes library.
2017-07-19 claziss[ARC] Add SecureShield AUX registers
2017-07-19 Claudiu Zissulescu[ARC] Add SJLI instruction.
2017-07-19 John Eric Martin[ARC] Add JLI support.
2017-07-18 Yuri ChornovianFix spelling typos.
2017-07-14 Ravi Bangoriabinutils/objdump: Fix disassemble for huge elf sections
2017-07-12 Alan ModraUpdate PO files
2017-07-11 Alan ModraMark generated cgen files read-only
2017-07-07 Alan ModraMove print_insn_XXX to an opcodes internal header,...
2017-07-05 Borislav PetkovX86: Disassemble primary opcode map's group 2 ModRM...
2017-07-05 Ramana RadhakrishnanFixup changelog entries for previous commit
2017-07-04 Ramana Radhakrishnan[Patch ARM] Support MVFR2 VFP Coprocessor register...
2017-07-04 Tristan GingoldRegenerate configure.
2017-07-03 Tristan GingoldRegenerate pot files.
2017-06-30 Maciej W. RozyckiMIPS/opcodes: Reorder LSA and DLSA instructions
2017-06-30 Maciej W. RozyckiMIPS: Add Imagination interAptiv MR2 MIPS32r3 processor...
2017-06-30 Maciej W. RozyckiMIPS: Add microMIPS XPA support
2017-06-30 Maciej W. RozyckiMIPS: Add microMIPS R5 support
2017-06-30 Maciej W. RozyckiMIPS: Fix XPA base and Virtualization ASE instruction...
2017-06-29 Maciej W. RozyckiMIPS/opcodes: Correctly combine ASE flags for ASE_MIPS1...
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