Use linux_get_siginfo_type_with_fields for x86
[external/binutils.git] / opcodes /
2016-02-01 Michael McConvilleFix undefined compilation behaviour shifting a value...
2016-01-25 Renlin Li[PATCH[ARM]Check mapping symbol while backward searchin...
2016-01-20 Matthew Wahab[AArch64] Reject invalid immediate operands to MSR UAO
2016-01-18 Maciej W. RozyckiMIPS: Remove remnants of 48-bit microMIPS instruction...
2016-01-17 Alan ModraRegen configure
2016-01-14 Nick CliftonFix display of RL78 MOVW instructions that use the...
2016-01-14 Matthew Wahab[AArch64] Fix missing architecture checks for ARMv8...
2016-01-12 Matthew Wahab[ARM] Support ARMv8.2 RAS extension.
2016-01-11 Peter BergnerDelete opcodes that have been removed from ISA 3.0.
2016-01-08 Andreas Schwabm68k: fix constraints of move.[bw] for ISA_B/C
2016-01-01 Alan ModraCopyright update for binutils
2016-01-01 Alan ModraNew 2016 binutils ChangeLog files
2016-01-01 Alan Modrabinutils ChangeLog rotation
2015-12-31 Andrew Burgessopcodes/arc: Support dmb instruction with no operands
2015-12-30 Alan ModraFix assorted ChangeLog errors
2015-12-24 Thomas Preud'hommeAdd assembler support for ARMv8-M Baseline
2015-12-24 Thomas Preud'hommeAdd assembler support for ARMv8-M Mainline
2015-12-22 Yoshinori SatoRXv2 support update
2015-12-15 Yoshinori SatoAdd support for RX V2 Instruction Set
2015-12-14 Matthew Wahab[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar...
2015-12-14 Matthew Wahab[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift...
2015-12-14 Matthew Wahab[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar...
2015-12-14 Matthew Wahab[AArch64][PATCH 11/14] Add support for the 2H vector...
2015-12-14 Matthew Wahab[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified...
2015-12-14 Matthew Wahab[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across...
2015-12-14 Matthew Wahab[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Eleme...
2015-12-14 Matthew Wahab[AArch64][PATCH 6/14] Support FP16 Vector Indexed Eleme...
2015-12-14 Matthew Wahab[AArch64][PATCH 5/14] Support FP16 Scalar Two Register...
2015-12-14 Matthew Wahab[AArch64][PATCH 4/14] Support FP16 Vector Two Register...
2015-12-14 Matthew Wahab[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three...
2015-12-14 Matthew Wahab[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three...
2015-12-14 Matthew Wahab[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD...
2015-12-14 Matthew Wahab[AArch64] Fix errors rebasing the ARMv8.2 AT and system...
2015-12-12 Alan ModraEnable 2 operand form of powerpc mfcr with -many
2015-12-11 Matthew Wahab[AArch64][Patch 5/5] Add instruction PSB CSYNC
2015-12-11 Matthew Wahab[AArch64][Patch 4/5] Support HINT aliases taking operands.
2015-12-11 Matthew Wahab[AArch64][Patch 3/5] Adjust maximum number of instructi...
2015-12-11 Matthew Wahab[AArch64][Patch 2/5] Add Statistical Profiling Extensio...
2015-12-10 Matthew Wahab[Aarch64] Support ARMv8.2 AT instructions
2015-12-10 Matthew Wahab[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
2015-12-10 Matthew Wahab[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP...
2015-12-10 Matthew Wahab[AArch64][binutils] Add support for ARMv8.2 PSTATE...
2015-12-10 Matthew Wahab[AArch64][PATCH 2/2] Add RAS system registers.
2015-12-10 Matthew Wahab[AArch64][PATCH 1/2] Add support for RAS instruction...
2015-12-09 H.J. LuImplement Intel OSPKE instructions
2015-12-08 DJ Delorierl78: Enable MULU for all ISAs.
2015-12-07 Alan ModraReorder some power9 insns
2015-12-04 Claudiu ZissulescuFix failures in the GAS testsuite for the ARC architecture.
2015-12-02 Andre VieiraFix ldah being disassembled as ldaexh
2015-11-27 Matthew Wahab[AArch64][PATCH 3/3] Add floating-point FP16 instructions
2015-11-27 Matthew Wahab[AArch64][PATCH 2/3] Adjust a utility function for...
2015-11-27 Matthew Wahab[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating...
2015-11-27 Matthew Wahab[AArch64] Add ARMv8.2 instruction alias REV64.
2015-11-27 Matthew Wahab[AArch64] Add ARMv8.2 instructions BFC and REV64.
2015-11-27 Matthew Wahab[AArch64] Let aliased instructions be their preferred...
2015-11-27 Matthew Wahab[Aarch64] Support an ARMv8.2 system register.
2015-11-23 Tristan Gingoldopcodes: handle mach-o for thumb/arm disambiguation.
2015-11-20 Matthew Wahab[AArch64] Add support for ARMv8.1 Virtulization Host...
2015-11-20 Nick CliftonRemove a if-clause that is redundant because the same...
2015-11-20 Nick CliftonUpdate translations.
2015-11-19 Matthew Wahab[AArch64] Reject invalid immediate operands to MSR PAN
2015-11-17 Nick CliftonFix the disassembly of conditional instructions will...
2015-11-15 Tristan GingoldBump version to 2.26.51
2015-11-12 Peter BergnerAdd assembler, disassembler and linker support for...
2015-11-09 Robert SuchanekMove copy_u.w to MSA64 ASE, remove copy_u.d.
2015-11-02 Nick CliftonDisassemble RX NOP instructions as such.
2015-11-02 Nick CliftonFix disassembly of RX zero-offset register indirect...
2015-10-28 Yao QiPass noaliases_p to aarch64_decode_insn
2015-10-27 Vinay KumarFix RL78 disassembly of DE+offset addressing to always...
2015-10-27 Vinay KumarDisplay system registers by their names when disassembl...
2015-10-27 Vinay KumarFix RL78 disassembly so that SP+OFFSET addressing alway...
2015-10-14 Andreas KrebbelAdd missing changelog entries
2015-10-14 Andreas KrebbelS/390: Fix instruction type of troo, trot, trto, and...
2015-10-08 Nick CliftonFix compile time warning compiling ARC port.
2015-10-07 Yao QiAvoid using 'template' C++ keyword
2015-10-07 Nick CliftonNew ARC implementation.
2015-10-02 Yao Qi[aarch64] expose disas_aarch64_insn and rename it to...
2015-10-02 Yao Qi[aarch64] Remove argument pc from disas_aarch64_insn
2015-09-29 Dominik VogtAdd support for extensions in the .machine pseudoop...
2015-09-28 Nick CliftonUpdare French translation for binutils and German trans...
2015-09-28 Tom RixPatches for illegal ppc 500 instructions
2015-09-25 jamesbowmanThe FT32's disassembly of 10-bit literals has the incor...
2015-09-23 Nick CliftonFix compile time warnings generated when compiling...
2015-09-22 Nick CliftonEnhance the RX disassembler to detect and report bad...
2015-09-22 Anton Blanchardopcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics
2015-09-10 Andreas KrebbelS/390: Fix instruction format of crj*, clrj*, and clgrj*.
2015-09-10 Andreas KrebbelS/390: Remove F_20 and FE_20. Adjust comments.
2015-09-10 Andreas KrebbelS/390: Fix MASK_RIE_R0PI and MASK_RIE_R0PU.
2015-09-09 Andreas KrebbelS/390: Remove trailing zeros on 4-bytes opcodes.
2015-09-09 Andreas KrebbelS/390: Fix opcode of ppno.
2015-08-25 Jose E. MarchesiSupport for the sparc %pmcdper privileged register.
2015-08-24 Jan StancekFix the partial disassembly of a broken three byte...
2015-08-21 Alexander FominPR binutils/18257: Properly decode x86/Intel mask instr...
2015-08-17 Alan ModraTrailing space in opcodes/ generated files
2015-08-13 Andre VieiraFixes for unpredictable nops and 26-bit versions of...
2015-08-12 Simon Dardis[MIPS] Map 'move' to 'or'.
2015-08-12 H.J. LuRemove trailing spaces in opcodes
2015-08-11 Nick CliftonFix the disassembly of the AArch64 SIMD EXT instruction.
2015-08-10 Robert SuchanekAdd SIGRIE instruction for MIPS R6
2015-08-07 Amit PawarRemove CpuFMA4 support from CPU_ZNVER1_FLAGS.
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