review.tizen.org Git - external/binutils.git/history

2017-05-02	Michael Clark	RISC-V: Change CALL macro to use ra as the temporary...	blob \| commitdiff
2017-03-15	Kito Cheng	RISC-V: Fix assembler for c.li, c.andi and c.addiw	blob \| commitdiff \| diff to current
2017-03-15	Kito Cheng	RISC-V: Fix assembler for c.addi, rd can be x0	blob \| commitdiff \| diff to current
2017-03-14	Andrew Waterman	RISC-V: Fix [dis]assembly of srai/srli	blob \| commitdiff \| diff to current
2017-02-15	Andrew Waterman	Add SFENCE.VMA instruction	blob \| commitdiff \| diff to current
2017-01-03	Kito Cheng	Add support for the Q extension to the RISCV ISA.	blob \| commitdiff \| diff to current
2017-01-02	Alan Modra	Update year range in copyright notice of all files.	blob \| commitdiff \| diff to current
2016-12-21	Andrew Waterman	Avoid creating symbol table entries for registers	blob \| commitdiff \| diff to current
2016-12-20	Andrew Waterman	Correct assembler mnemonic for RISC-V aqrl AMOs	blob \| commitdiff \| diff to current
2016-12-20	Andrew Waterman	Fix disassembly of RISC-V CSR instructions under -Mno...	blob \| commitdiff \| diff to current
2016-12-20	Andrew Waterman	Add canonical JALR for RISC-V	blob \| commitdiff \| diff to current
2016-12-20	Andrew Waterman	Formatting changes for RISC-V	blob \| commitdiff \| diff to current
2016-11-01	Nick Clifton	Add support for RISC-V architecture.	blob \| commitdiff \| diff to current

Domain: System / Toolchain;