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[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
[external/binutils.git]
/
opcodes
/
riscv-dis.c
2018-08-30
Jim Wilson
RISC-V: Allow instruction require more than one extension
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2018-07-30
Jim Wilson
RISC-V: Set insn info fields correctly when disassembling.
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2018-03-03
Alan Modra
opcodes error messages
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2018-01-10
Jim Wilson
RISC-V: Disassemble x0 based addresses as 0.
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2018-01-06
Jim Wilson
RISC-V: Print symbol address for jalr w/ zero offset.
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2018-01-03
Alan Modra
Update year range in copyright notice of binutils files
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2017-07-25
Nick Clifton
Fix typos in error and option messages in OPCODES library.
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2017-05-24
Yao Qi
Move print_insn_XXX to an opcodes internal header
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2017-05-04
Kito Cheng
RISC-V: Fix disassemble for c.li, c.andi and c.addiw
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2017-04-04
Palmer Dabbelt
RISC-V: Resurrect GP-relative disassembly hints
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2017-01-03
Dilyan Palauzov
Add fall through comment.
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2017-01-02
Alan Modra
Update year range in copyright notice of all files.
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2016-12-20
Andrew Waterman
Re-work RISC-V gas flags: now we just support -mabi...
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2016-11-01
Nick Clifton
Add support for RISC-V architecture.
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