[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
[external/binutils.git] / opcodes / riscv-dis.c
2018-08-30 Jim WilsonRISC-V: Allow instruction require more than one extension
2018-07-30 Jim WilsonRISC-V: Set insn info fields correctly when disassembling.
2018-03-03 Alan Modraopcodes error messages
2018-01-10 Jim WilsonRISC-V: Disassemble x0 based addresses as 0.
2018-01-06 Jim WilsonRISC-V: Print symbol address for jalr w/ zero offset.
2018-01-03 Alan ModraUpdate year range in copyright notice of binutils files
2017-07-25 Nick CliftonFix typos in error and option messages in OPCODES library.
2017-05-24 Yao QiMove print_insn_XXX to an opcodes internal header
2017-05-04 Kito ChengRISC-V: Fix disassemble for c.li, c.andi and c.addiw
2017-04-04 Palmer DabbeltRISC-V: Resurrect GP-relative disassembly hints
2017-01-03 Dilyan PalauzovAdd fall through comment.
2017-01-02 Alan ModraUpdate year range in copyright notice of all files.
2016-12-20 Andrew WatermanRe-work RISC-V gas flags: now we just support -mabi...
2016-11-01 Nick CliftonAdd support for RISC-V architecture.