Add multiple-CPU support in ravenscar-thread.c
[external/binutils.git] / opcodes / i386-opc.tbl
2017-11-14 Jan Beulichx86: add support for AVX-512 VPCMP*{B,W} pseudo-ops
2017-11-14 Jan Beulichx86: string insns don't allow displacements
2017-11-13 Jan Beulichx86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should...
2017-10-23 Igor TsimbalistEnable Intel AVX512_BITALG instructions.
2017-10-23 Igor TsimbalistEnable Intel AVX512_VNNI instructions.
2017-10-23 Igor TsimbalistEnable Intel VPCLMULQDQ instruction.
2017-10-23 Igor TsimbalistEnable Intel VAES instructions.
2017-10-23 Igor TsimbalistEnable Intel GFNI instructions.
2017-10-23 Igor TsimbalistEnable Intel AVX512_VBMI2 instructions.
2017-06-21 H.J. Lux86: CET v2.0: Update incssp and setssbsy
2017-06-21 H.J. Lux86: CET v2.0: Rename savessp to saveprevssp
2017-05-22 H.J. Lux86: Add NOTRACK prefix support
2017-03-09 H.J. LuX86: Add pseudo prefixes to control encoding
2017-03-09 H.J. LuUse CpuCET on rdsspq
2017-03-06 H.J. LuAdd support for Intel CET instructions
2017-02-28 Jan Beulichx86: fix handling of 64-bit operand size VPCMPESTR...
2017-01-12 Igor TsimbalistEnable Intel AVX512_VPOPCNTDQ instructions
2017-01-02 Alan ModraUpdate year range in copyright notice of all files.
2016-11-09 H.J. LuX86: Remove the .s suffix from EVEX vpextrw
2016-11-09 H.J. LuX86: Merge AVX512F vmovq
2016-11-02 Igor TsimbalistEnable Intel AVX512_4VNNIW instructions
2016-11-02 Igor TsimbalistEnable Intel AVX512_4FMAPS instructions
2016-10-21 H.J. LuX86: Remove pcommit instruction
2016-08-24 H.J. LuX86: Add ptwrite instruction
2016-07-01 Jan Beulichx86: allow suffix-less movzw and 64-bit movzb
2016-07-01 Jan Beulichx86: remove stray instruction attributes
2016-07-01 Jan Beulichx86/Intel: fix operand checking for MOVSD
2016-06-03 H.J. LuHandle indirect branches for AMD64 and Intel64
2016-05-27 H.J. LuReplace CpuAMD64/CpuIntel64 with AMD64/Intel64
2016-05-10 Alexander FominEnable Intel RDPID instruction.
2016-01-01 Alan ModraCopyright update for binutils
2015-12-09 H.J. LuImplement Intel OSPKE instructions
2015-06-30 Amit PawarAdd support for monitorx/mwaitx instructions
2015-06-01 Jan Beulichx86/Intel: accept mandated operand order for vcvt{...
2015-05-18 H.J. LuRemove Disp32 from AMD64 direct call/jmp
2015-05-15 H.J. LuSupport AMD64/Intel ISAs in assembler/disassembler
2015-05-11 H.J. LuRemove Disp16|Disp32 from 64-bit direct branches
2015-03-17 Ganesh Gopalasubra... Add znver1 processor
2015-01-01 Alan ModraChangeLog rotatation and copyright year update
2014-11-17 Ilya TocarAdd AVX512VBMI instructions
2014-11-17 Ilya TocarAdd AVX512IFMA instructions
2014-11-17 Ilya TocarAdd pcommit instruction
2014-11-17 Ilya TocarAdd clwb instruction
2014-07-22 Ilya TocarAdd AVX512DQ instructions and their AVX512VL variants.
2014-07-22 Ilya TocarAdd support for AVX512BW instructions and their AVX512V...
2014-07-22 Ilya TocarAdd support for AVX512VL versions of AVX512CD instructions.
2014-07-22 Ilya TocarAdd support for AVX512VL. Add AVX512VL versions of...
2014-04-04 Ilya TocarAdd support for Intel SGX instructions
2014-03-20 Ilya TocarFix memory size for gather/scatter instructions
2014-03-05 Alan ModraUpdate copyright years
2014-02-25 Ilya TocarRemove bogus vcvtps2ph variant.
2014-02-21 Ilya TocarAdd support for CPUID PREFETCHWT1
2014-02-20 Ilya TocarChange cpu for vptestnmd and vptestnmq instructions.
2014-02-12 Ilya TocarAdd clflushopt, xsaves, xsavec, xrstors
2013-10-12 H.J. LuOnly allow 32-bit/64-bit registers for bndcl/bndcu...
2013-10-08 Jan Beulichopcodes/
2013-09-30 H.J. LuAdd Size64 to movq/vmovq with Reg64 operand
2013-07-26 H.J. LuAdd Intel AVX-512 support
2013-07-25 H.J. LuSupport Intel SHA
2013-07-24 H.J. LuSupport Intel MPX
2013-07-08 H.J. LuReplace Xmmword with Qword on cvttps2pi
2013-04-08 Jan Beulichgas/testsuite/
2013-02-19 H.J. LuImplement Intel SMAP instructions
2012-11-20 H.J. LuFix opcode for 64-bit jecxz
2012-09-20 H.J. LuReplace CpuSSE3 with CpuCX16 for cmpxchg16b
2012-08-17 H.J. LuAdd AMD btver1 and btver2 support
2012-08-07 Jan BeulichThere were several cases where the registers in the...
2012-07-31 Jan BeulichVMOVNTDQA was both misplaced and improperly tagged...
2012-07-16 H.J. LuImplement RDRSEED, ADX and PRFCHW instructions
2012-07-02 Roland McGrathgas/testsuite/
2012-06-22 Roland McGrathgas/
2012-06-22 Roland McGrathgas/
2012-02-08 H.J. LuImplement Intel Transactional Synchronization Extensions
2012-01-13 H.J. LuAdd vmfunc
2011-08-01 H.J. LuAdd Disp32S to 64bit call.
2011-06-30 H.J. LuFix rorx in BMI2.
2011-06-10 H.J. LuSupport AVX Programming Reference (June, 2011).
2011-01-17 Quentin NeillAdd support for TBM instructions.
2011-01-05 H.J. LuImplement BMI instructions.
2010-10-14 H.J. LuRemove CheckRegSize from movq.
2010-10-14 H.J. LuRemove CheckRegSize from instructions with 0, 1 or...
2010-10-14 H.J. LuAdd CheckRegSize to instructions which require register...
2010-08-06 H.J. LuDon't generate multi-byte NOPs for i686.
2010-08-06 H.J. LuAdd Cpu186 to ud1/ud2/ud2a/ud2b.
2010-08-06 H.J. LuAdd ud1 to x86.
2010-07-05 H.J. LuReplace rdrnd with rdrand.
2010-07-01 H.J. LuSupport AVX Programming Reference (June, 2010)
2010-03-23 Sebastian Pop2010-03-22 Sebastian Pop <sebastian.pop@amd.com>
2010-02-11 H.J. LuUpdate copyright.
2010-02-11 Sebastian Pop2010-02-10 Quentin Neill <quentin.neill@amd.com>
2010-01-24 H.J. LuReplace "Vex" with "Vex=3" on AVX scalar instructions.
2010-01-21 H.J. LuAdd xsave64 and xrstor64.
2010-01-15 Sebastian Pop2010-01-15 Sebastian Pop <sebastian.pop@amd.com>
2009-12-19 H.J. LuReplace VexNDS, VexNDD and VexLWP with VexVVVV.
2009-12-16 H.J. LuRemove ByteOkIntel.
2009-12-16 H.J. LuReplace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A...
2009-12-16 H.J. LuReplace Vex2Sources and Vex3Sources with VexSources.
2009-12-16 H.J. LuRemove VexW0 and VexW1. Add VexW.
2009-12-15 H.J. LuAdd USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX.
2009-12-04 H.J. LuSupport fxsave64 and fxrstor64.
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