ld: Fix issue where PROVIDE overrides defined symbol
[external/binutils.git] / opcodes / i386-dis.c
2018-01-03 Alan ModraUpdate year range in copyright notice of binutils files
2017-11-24 Jan Beulichx86: don't omit disambiguating suffixes from "fi*"
2017-11-23 Jan Beulichx86: fix AVX-512 16-bit addressing
2017-11-23 Jan Beulichx86: correct UDn
2017-11-16 Jan Beulichx86: ignore high register select bit(s) in 32- and...
2017-11-15 Jan Beulichx86: use correct register names
2017-11-15 Jan Beulichx86: drop VEXI4_Fixup()
2017-11-14 Jan Beulichx86: add disassembler support for XOP VPCOM* pseudo-ops
2017-10-23 Igor TsimbalistEnable Intel AVX512_BITALG instructions.
2017-10-23 Igor TsimbalistEnable Intel AVX512_VNNI instructions.
2017-10-23 Igor TsimbalistEnable Intel VPCLMULQDQ instruction.
2017-10-23 Igor TsimbalistEnable Intel VAES instructions.
2017-10-23 Igor TsimbalistEnable Intel GFNI instructions.
2017-10-23 Igor TsimbalistEnable Intel AVX512_VBMI2 instructions.
2017-09-09 H.J. Lux86: Remove restriction on NOTRACK prefix position
2017-07-18 Yuri ChornovianFix spelling typos.
2017-07-05 Borislav PetkovX86: Disassemble primary opcode map's group 2 ModRM...
2017-06-21 H.J. Lux86: CET v2.0: Update incssp and setssbsy
2017-06-21 H.J. Lux86: CET v2.0: Rename savessp to saveprevssp
2017-06-21 H.J. Lux86: CET v2.0: Update NOTRACK prefix
2017-06-15 H.J. Lui386-dis: Check valid bnd register
2017-05-24 Yao QiMove print_insn_XXX to an opcodes internal header
2017-05-22 H.J. Lux86: Add NOTRACK prefix support
2017-03-06 H.J. LuAdd support for Intel CET instructions
2017-02-28 Jan Beulichx86: fix handling of 64-bit operand size VPCMPESTR...
2017-02-24 Jan Beulichx86: also correctly support TEST opcode aliases
2017-02-23 Jan Beulichx86: drop stray VEX opcode 82 references
2017-01-12 Igor TsimbalistEnable Intel AVX512_VPOPCNTDQ instructions
2017-01-02 Alan ModraUpdate year range in copyright notice of all files.
2016-12-01 Nick CliftonFix abort in x86 disassembler.
2016-11-28 Amit PawarX86: Ignore REX_B bit for 32-bit XOP instructions
2016-11-09 H.J. LuX86: Remove the .s suffix from EVEX vpextrw
2016-11-08 H.J. LuX86: Remove the THREE_BYTE_0F7A entry
2016-11-07 H.J. LuX86: Properly handle bad FPU opcode
2016-11-03 H.J. LuX86: Reuse opcode 0x80 decoder for opcode 0x82
2016-11-03 H.J. LuX86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
2016-11-03 H.J. LuX86: Rename REG_82 to REG_83
2016-11-02 Igor TsimbalistEnable Intel AVX512_4VNNIW instructions
2016-10-21 H.J. LuX86: Remove pcommit instruction
2016-10-20 H.J. LuCheck invalid mask registers
2016-10-18 H.J. LuCheck addr32flag instead of sizeflag for rip/eip
2016-10-18 H.J. LuRemove the remaining SSE5 support
2016-10-05 Alan Modra-Wimplicit-fallthrough warning fixes
2016-09-30 H.J. LuDon't assign alt twice
2016-08-24 H.J. LuX86: Add ptwrite instruction
2016-06-03 H.J. LuHandle indirect branches for AMD64 and Intel64
2016-05-10 Alexander FominEnable Intel RDPID instruction.
2016-04-23 H.J. LuSkip if size of bfd_vma is smaller than address size
2016-02-16 H.J. LuAdd parentheses to prevent truncated addresses
2016-01-01 Alan ModraCopyright update for binutils
2015-12-09 H.J. LuImplement Intel OSPKE instructions
2015-08-24 Jan StancekFix the partial disassembly of a broken three byte...
2015-08-21 Alexander FominPR binutils/18257: Properly decode x86/Intel mask instr...
2015-07-30 H.J. LuProperly disassemble movnti in Intel mode
2015-07-23 Alan ModraFix ubsan signed integer overflow
2015-06-30 Amit PawarAdd support for monitorx/mwaitx instructions
2015-06-01 Jan Beulichx86/Intel: disassemble vcvt{,u}si2s{d,s} with correct...
2015-05-15 H.J. LuSupport AMD64/Intel ISAs in assembler/disassembler
2015-05-09 H.J. LuIgnore 0x66 prefix for call/jmp/jcc in 64-bit mode
2015-04-23 Jan Beulichx86: disambiguate disassembly of certain AVX512 insns
2015-04-15 H.J. LuRemove the unused PREFIX_UD_XXX
2015-04-15 H.J. LuCheck dp->prefix_requirement instead
2015-04-15 H.J. LuHandle invalid prefixes for rdrand and rdseed
2015-04-15 H.J. LuReplace mandatory_prefix with prefix_requirement
2015-04-06 Ilya Tocarx86: Use individual prefix control for each opcode.
2015-03-17 Ganesh Gopalasubra... Add znver1 processor
2015-01-01 Alan ModraChangeLog rotatation and copyright year update
2014-11-17 Ilya TocarAdd AVX512VBMI instructions
2014-11-17 Ilya TocarAdd AVX512IFMA instructions
2014-11-17 Ilya TocarAdd pcommit instruction
2014-11-17 Ilya TocarAdd clwb instruction
2014-09-22 H.J. LuIgnore MOD field for control/debug register move
2014-09-10 H.J. LuProperly handle suffix for iret and sysret
2014-07-22 Ilya TocarAdd AVX512DQ instructions and their AVX512VL variants.
2014-07-22 Ilya TocarAdd support for AVX512BW instructions and their AVX512V...
2014-07-22 Ilya TocarAdd support for AVX512VL. Add AVX512VL versions of...
2014-06-10 H.J. LuOnly print prefixes before fwait
2014-05-09 H.J. LuProperly display extra data/address size prefixes
2014-05-05 H.J. LuProperly handle multiple opcode prefixes
2014-05-02 H.J. LuUse sigsetjmp/siglongjmp in opcodes
2014-05-01 H.J. LuHandle prefixes before fwait
2014-04-04 Ilya TocarAdd support for Intel SGX instructions
2014-03-20 Ilya TocarFix memory size for gather/scatter instructions
2014-03-05 Alan ModraUpdate copyright years
2014-02-12 Ilya TocarAdd clflushopt, xsaves, xsavec, xrstors
2014-01-30 Michael ZolotukhinFix shift for AVX512F gather/scatter instructions
2014-01-09 Roland McGrathFix buffer underrun in i386-dis.c.
2013-12-17 Michael ZolotukhinProperly handle ljmp/lcall with invalid MODRM byte
2013-10-12 H.J. LuOnly allow 32-bit/64-bit registers for bndcl/bndcu...
2013-10-11 Roland McGrathopcodes/
2013-08-19 H.J. LuRemove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3F
2013-07-26 H.J. LuAdd Intel AVX-512 support
2013-07-25 H.J. LuSupport Intel SHA
2013-07-24 H.J. LuSupport Intel MPX
2013-03-27 H.J. LuProperly check address mode for SIB
2013-02-19 H.J. LuImplement Intel SMAP instructions
2012-10-24 Roland McGrathgas/testsuite/
2012-08-07 Roland McGrathgas/testsuite/
2012-08-06 Roland McGrathgas/testsuite/
2012-08-06 Roland McGrathgas/testsuite/
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