2018-02-22 |
H.J. Lu | x86: Add {rex} pseudo prefix |
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2018-02-20 |
Maciej W. Rozycki | MIPS16/opcodes: Free up `M' operand code |
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2018-02-19 |
Thomas Preud'homme | [ARM] Fix bxns mask |
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2018-02-13 |
Nick Clifton | Fix compile time warning messages from gcc version... |
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2018-02-13 |
Maciej W. Rozycki | WebAssembly: Correct an `index' global shadowing error... |
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2018-02-12 |
Henry Wong | MIPS: Fix encoding for MIPSr6 sigrie instruction. |
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2018-02-05 |
Nick Clifton | Updated Brazillian portuguese and Russian translation |
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2018-01-23 |
Igor Tsimbalist | Enable Intel PCONFIG instruction. |
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2018-01-23 |
Igor Tsimbalist | Enable Intel WBNOINVD instruction. |
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2018-01-17 |
Jim Wilson | RISC-V: Fix bug in prior addi/c.nop patch. |
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2018-01-17 |
Igor Tsimbalist | Replace CET bit with IBT and SHSTK bits. |
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2018-01-16 |
Nick Clifton | Update translations for various binutils components. |
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2018-01-15 |
Jim Wilson | RISC-V: Add support for addi that compresses to c.nop. |
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2018-01-15 |
Nick Clifton | Update Ukranian translations for bfd, binutils, gas... |
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2018-01-13 |
Nick Clifton | Update pot files |
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2018-01-13 |
Nick Clifton | Bump version number to 2.30.51 |
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2018-01-13 |
Nick Clifton | Add note about 2.30 branch creation to changelogs |
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2018-01-11 |
Igor Tsimbalist | Remove VL variants for 4FMAPS and 4VNNIW insns. |
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2018-01-10 |
Jan Beulich | x86: fix Disp8 handling for scalar AVX512_4FMAPS insns |
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2018-01-10 |
Jan Beulich | x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants |
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2018-01-10 |
Jim Wilson | RISC-V: Disassemble x0 based addresses as 0. |
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2018-01-09 |
James Greenhalgh | [Arm] Add CSDB instruction |
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2018-01-09 |
James Greenhalgh | Add support for the AArch64's CSDB instruction. |
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2018-01-08 |
H.J. Lu | x86: Properly encode vmovd with 64-bit memeory |
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2018-01-06 |
Jim Wilson | RISC-V: Print symbol address for jalr w/ zero offset. |
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2018-01-03 |
Alan Modra | Update year range in copyright notice of binutils files |
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2018-01-03 |
Alan Modra | ChangeLog rotation |
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2018-01-02 |
Jan Beulich | x86: partial revert of 10c17abdd0 |
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2017-12-20 |
Jim Wilson | RISC-V: Add compressed instruction hints, and a few... |
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2017-12-19 |
Tamar Christina | Correct disassembly of dot product instructions. |
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2017-12-19 |
Tamar Christina | Add support for V_4B so we can properly reject it. |
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2017-12-18 |
Jan Beulich | x86: fold certain AVX and AVX2 templates |
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2017-12-18 |
Jan Beulich | x86: fold RegXMM/RegYMM/RegZMM into RegSIMD |
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2017-12-18 |
Jan Beulich | x86: drop FloatReg and FloatAcc |
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2017-12-18 |
Jan Beulich | x86: replace Reg8, Reg16, Reg32, and Reg64 |
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2017-12-15 |
Dimitar Dimitrov | Fix disassembly for PowerPC |
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2017-12-15 |
Jan Beulich | x86: drop stray CheckRegSize uses |
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2017-12-13 |
Jim Wilson | Add missing RISC-V fsrmi and fsflagsi instructions. |
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2017-12-13 |
Dimitar Dimitrov | This patch enables disassembler_needs_relocs for PRU... |
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2017-12-11 |
Renlin Li | [Binutils][Objdump]Check symbol section information... |
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2017-12-03 |
Alan Modra | Fix "FAIL: VLE relocations 3" |
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2017-12-01 |
Peter Bergner | Use consistent types for holding instructions, instruct... |
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2017-11-30 |
Jan Beulich | x86: derive DispN from BaseIndex |
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2017-11-30 |
Jan Beulich | x86: drop Vec_Disp8 |
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2017-11-29 |
Stefan Stroe | Support --localedir, --datarootdir and --datadir |
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2017-11-27 |
Nick Clifton | Update the simplified Chinese translation of the messag... |
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2017-11-24 |
Jan Beulich | x86: don't omit disambiguating suffixes from "fi*" |
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2017-11-23 |
Igor Tsimbalist | Add Disp8MemShift for AVX512 VAES instructions. |
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2017-11-23 |
Jan Beulich | x86: fix AVX-512 16-bit addressing |
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2017-11-23 |
Jan Beulich | x86: correct UDn |
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2017-11-22 |
Igor Tsimbalist | Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor. |
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2017-11-22 |
Igor Tsimbalist | Update ChangeLog |
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2017-11-22 |
claziss | [ARC] Fix handling of ARCv2 H-register class. |
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2017-11-21 |
claziss | [ARC] Improve printing of pc-relative instructions. |
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2017-11-16 |
Tamar Christina | Add new AArch64 FP16 FM{A|S} instructions. |
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2017-11-16 |
Tamar Christina | Add assembler and disassembler support for the new... |
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2017-11-16 |
Jan Beulich | x86: ignore high register select bit(s) in 32- and... |
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2017-11-15 |
Jan Beulich | x86: use correct register names |
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2017-11-15 |
Jan Beulich | x86: drop VEXI4_Fixup() |
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2017-11-15 |
Jan Beulich | x86-64: don't allow use of %axl as accumulator |
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2017-11-14 |
Jan Beulich | x86: add disassembler support for XOP VPCOM* pseudo-ops |
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2017-11-14 |
Jan Beulich | x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops |
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2017-11-14 |
Jan Beulich | x86: string insns don't allow displacements |
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2017-11-13 |
Jan Beulich | x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should... |
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2017-11-09 |
Tamar Christina | Add assembler and disassembler support for the new... |
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2017-11-09 |
Tamar Christina | Add the operand encoding types for the new Armv8.2... |
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2017-11-09 |
Tamar Christina | Adds the new Fields and Operand types for the new instr... |
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2017-11-09 |
Tamar Christina | Split the ARM Crypto ISA extensions for AES and SHA1... |
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2017-11-08 |
Nick Clifton | Split the AArch64 Crypto instructions for AES and SHA1... |
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2017-11-08 |
Jiong Wang | Adds command line support for Armv8.4-A, via the new... |
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2017-11-07 |
Andrew Burgess | opcodes/arc: Fix incorrect insn_class for some nps... |
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2017-11-07 |
Alan Modra | ngettext support |
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2017-11-03 |
claziss | [ARC] Force the disassam to use the hexadecimal number... |
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2017-11-03 |
claziss | [ARC] Sync opcode data base. |
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2017-10-25 |
Alan Modra | PR22348, conflicting global vars in crx and cr16 |
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2017-10-24 |
Andrew Waterman | RISC-V: Fix disassembly of c.addi4spn, c.addi16sp,... |
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2017-10-23 |
Igor Tsimbalist | Add missing ChangeLog entries |
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2017-10-23 |
Igor Tsimbalist | Fix the master due to bad regenerated files |
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2017-10-18 |
Eric Botcazou | [Visium] Disassemble the operands of the stop instruction. |
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2017-10-13 |
James Bowman | FT32: support for FT32B processor - part 1 |
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2017-10-09 |
Andreas Krebbel | S/390: Sync with latest POP - 3 new instructions |
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2017-10-09 |
Andreas Krebbel | S/390: Sync with IBM z14 POP - SI_RD format |
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2017-10-01 |
Alexander Fedotov | Add new mnemonics for VLE multiple load instructions |
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2017-09-27 |
Nick Clifton | Add support for the new names of the RISC-V fmv.x.s... |
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2017-09-26 |
Nick Clifton | Allow the macw and macl instructions to be used on... |
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2017-09-25 |
Sergio Durigan Junior | Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm... |
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2017-09-11 |
Kuan-Lin Chen | nds32: Rename __BIT() to N32_BIT(). |
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2017-09-09 |
H.J. Lu | x86: Remove restriction on NOTRACK prefix position |
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2017-08-31 |
Nick Clifton | Add updated French translations for opcodes and gprof |
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2017-08-31 |
James Bowman | FT32: improve disassembly readability |
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2017-08-24 |
Alexander Fedotov | [PowerPC VLE] Add SPE2 and EFS2 instructions support |
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2017-08-23 |
Alan Modra | ppc-opc.c formatting |
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2017-08-22 |
Palmer Dabbelt | RISC-V: Mark "c.nop" as an alias |
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2017-08-21 |
Alexander Fedotov | [PowerPC VLE] Add LSP (Lightweight Signal Processing... |
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2017-08-09 |
Jiong Wang | [ARM] Don't warn on REG_SP when used in CRC32 instructions |
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2017-08-07 |
H.J. Lu | Mark big and mach with ATTRIBUTE_UNUSED |
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2017-08-07 |
Maciej W. Rozycki | GDB/opcodes: Remove arch/mach/endian disassembler asser... |
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2017-07-25 |
Nick Clifton | Fix typos in error and option messages in OPCODES library. |
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2017-07-24 |
Jiong Wang | [AArch64] Fix the bit pattern order in the comments... |
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2017-07-21 |
Andreas Krebbel | S/390: Support z14 as CPU name. |
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