2019-03-12 |
Andreas Krebbel | Add missing changelogs for previous commits. |
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2019-02-08 |
Jim Wilson | Add missing ChangeLog files for previous patch. |
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2019-02-07 |
Tamar Christina | Arm: Backport hlt to all architectures. |
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2019-02-07 |
Tamar Christina | AArch64: Add verifier for By elem Single and Double... |
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2019-02-07 |
Nick Clifton | Updated Swedish translation for the opcodes sub-directory |
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2019-01-31 |
Andreas Krebbel | S/390: Implement instruction set extensions |
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2019-01-25 |
Tamar Christina | AArch64: Add missing changelog for Update encodings... |
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2019-01-25 |
Sudi Das | AArch64: Add new STZGM instruction for Armv8.5-A Memory... |
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2019-01-25 |
Sudi Das | AArch64: Remove ldgv and stgv instructions from Armv8... |
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2019-01-23 |
Nick Clifton | Updated translations for some of the binutils subdirectory. |
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2019-01-21 |
Nick Clifton | Updated translations for various binutils subdirectories. |
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2019-01-20 |
Chenghua Xu | [MIPS] fix typo in mips_arch_choices. |
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2019-01-19 |
Nick Clifton | Change version to 2.32.51 and regenerate configure... |
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2019-01-19 |
Nick Clifton | Add markers for 2.32 branch to NEWS and ChangeLog files. |
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2019-01-09 |
John Darrington | S12Z: Don't crash when disassembling invalid instructions. |
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2019-01-09 |
John Darrington | S12Z: Fix disassembly of indexed OPR operands with... |
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2019-01-09 |
Andrew Paprocki | Adjust bfd/warning.m4 egrep patterns |
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2019-01-07 |
Alan Modra | s12z regen |
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2019-01-03 |
John Darrington | S12Z: opcodes: Separate the decoding of operations... |
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2019-01-01 |
Alan Modra | Update year range in copyright notice of binutils files |
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2019-01-01 |
Alan Modra | ChangeLog rotation |
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2018-12-28 |
Alan Modra | PR24028, PPC_INT_FMT |
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2018-12-18 |
Alan Modra | Include bfd_stdint.h in bfd.h |
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2018-12-07 |
Jim Wilson | RISC-V: Fix 4-arg add parsing. |
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2018-12-06 |
Andrew Burgess | sim/opcodes: Allow use of out of tree cgen source directory |
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2018-12-06 |
Andrew Burgess | opcodes/riscv: Hide '.L0 ' fake symbols |
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2018-12-03 |
Jim Wilson | RISC-V: Accept version, supervisor ext and more than... |
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2018-12-03 |
Egeyar Bagcioglu | [aarch64] - Only use MOV for disassembly when shifter... |
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2018-11-29 |
Jim Wilson | RISC-V: Add missing c.unimp instruction. |
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2018-11-27 |
Jim Wilson | RISC-V: Add .insn CA support. |
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2018-11-21 |
John Darrington | S12Z opcodes: Fix bug disassembling certain shift instr... |
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2018-11-13 |
Francois H. Theron | opcodes/nfp: Fix disassembly of crc[] with swapped... |
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2018-11-12 |
Sudakshina Das | [BINUTILS, AARCH64, 8/8] Add data cache instructions... |
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2018-11-12 |
Sudakshina Das | [BINUTILS, AARCH64, 7/8] Add system registers for Memor... |
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2018-11-12 |
Sudakshina Das | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction... |
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2018-11-12 |
Sudakshina Das | [BINUTILS, AARCH64, 5/8] Add Tag getting instruction... |
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2018-11-12 |
Sudakshina Das | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions... |
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2018-11-12 |
Sudakshina Das | [BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instruc... |
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2018-11-12 |
Sudakshina Das | [BINUTILS, AARCH64, 2/8] Add Tag generation instruction... |
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2018-11-12 |
Sudakshina Das | [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging... |
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2018-11-06 |
Sudakshina Das | [BINUTILS, ARM] Add Armv8.5-A to select_arm_features... |
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2018-11-06 |
Alan Modra | PowerPC instruction mask checks |
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2018-11-06 |
Jan Beulich | x86: correctly handle VPBROADCASTD with EVEX.W set... |
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2018-11-06 |
Jan Beulich | x86: correctly handle VMOVD with EVEX.W set outside... |
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2018-11-06 |
Jan Beulich | x86: correctly handle KMOVD with VEX.W set outside... |
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2018-11-06 |
Jan Beulich | x86: adjust {,E}VEX.W handling for PEXTR* / PINSR* |
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2018-11-06 |
Jan Beulich | x86: adjust {,E}VEX.W handling outside of 64-bit mode |
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2018-11-06 |
Jan Beulich | x86: fix various non-LIG templates |
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2018-11-06 |
Jan Beulich | x86: allow {store} to select alternative {,}PEXTRW... |
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2018-11-06 |
Jan Beulich | x86: add more VexWIG |
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2018-11-06 |
Jan Beulich | x86: XOP VPHADD* / VPHSUB* are VEX.W0 |
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2018-10-22 |
John Darrington | S12Z: Disassembly: Fallback to show the address if... |
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2018-10-19 |
Tamar Christina | Arm: Fix disassembler crashing on -b binary when thumb... |
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2018-10-16 |
Matthew Malcomson | AArch64: Fix error checking for SIMD udot (by element) |
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2018-10-10 |
Jan Beulich | x86: fold Size{16,32,64} template attributes |
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2018-10-09 |
Sudakshina Das | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS |
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2018-10-09 |
Sudakshina Das | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and... |
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2018-10-09 |
Sudakshina Das | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction |
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2018-10-09 |
Sudakshina Das | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instr... |
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2018-10-09 |
Sudakshina Das | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction |
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2018-10-09 |
Sudakshina Das | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data... |
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2018-10-09 |
Sudakshina Das | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB... |
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2018-10-09 |
Sudakshina Das | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing... |
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2018-10-09 |
Sudakshina Das | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5... |
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2018-10-08 |
Tamar Christina | AArch64: Replace C initializers with memset |
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2018-10-05 |
H.J. Lu | x86: Add Intel ENCLV to assembler and disassembler |
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2018-10-05 |
Sudakshina Das | [Arm, 2/3] Add instruction SB for AArch32 |
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2018-10-05 |
Richard Henderson | or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns |
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2018-10-05 |
Stafford Horne | or1k: Add the l.adrp insn and supporting relocations |
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2018-10-05 |
Richard Henderson | or1k: Add relocations for high-signed and low-stores |
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2018-10-03 |
Tamar Christina | AArch64: Constraint disassembler and assembler changes. |
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2018-10-03 |
Tamar Christina | AArch64: Add SVE constraints verifier. |
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2018-10-03 |
Tamar Christina | AArch64: Refactor verifiers to make more general. |
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2018-10-03 |
Tamar Christina | AArch64: Refactor err_type. |
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2018-10-03 |
Tamar Christina | AArch64: Wire through instr_sequence |
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2018-10-03 |
Tamar Christina | AArch64: Mark sve instructions that require MOVPRFX... |
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2018-10-02 |
Palmer Dabbelt | RISC-V: Add fence.tso instruction |
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2018-09-23 |
Sandra Loosemore | Fix incorrect extraction of signed constants in nios2... |
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2018-09-21 |
Simon Marchi | csky-opc.h: Initialize fields of last array elements |
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2018-09-20 |
Maciej W. Rozycki | ARC: Fix build errors with large constants and C89 |
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2018-09-20 |
Nick Clifton | Andes Technology has good news for you, we plan to... |
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2018-09-17 |
Jim Wilson | RISC-V: bge[u] should get higher priority than ble[u]. |
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2018-09-17 |
H.J. Lu | x86: Set EVex=2 on EVEX.128 only vmovd and vmovq |
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2018-09-17 |
H.J. Lu | x86: Set Vex=1 on VEX.128 only vmovd and vmovq |
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2018-09-17 |
H.J. Lu | x86: Update disassembler for VexWIG |
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2018-09-17 |
H.J. Lu | x86: Replace VexW=3 with VexWIG |
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2018-09-16 |
H.J. Lu | x86: Set VexW=3 on AVX vrsqrtss |
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2018-09-15 |
H.J. Lu | x86: Set Vex=1 on VEX.128 only vmovq |
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2018-09-14 |
H.J. Lu | x86: Support VEX/EVEX WIG encoding |
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2018-09-14 |
H.J. Lu | x86: Handle unsupported static rounding in vcvt[u]si2sd... |
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2018-09-14 |
H.J. Lu | x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32... |
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2018-09-14 |
H.J. Lu | i386: Reformat OP_E_memory |
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2018-09-14 |
Jan Beulich | x86: fold CRC32 templates |
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2018-09-13 |
H.J. Lu | i386: Update VexW field for VEX instructions |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from a few further insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512_4* insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512DQ insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512BW insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512VL insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512ER insns |
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