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[external/binutils.git] / opcodes / ChangeLog

2018-02-20	Maciej W. Rozycki	MIPS16/opcodes: Free up `M' operand code	blob \| commitdiff
2018-02-19	Thomas Preud'homme	[ARM] Fix bxns mask	blob \| commitdiff \| diff to current
2018-02-13	Nick Clifton	Fix compile time warning messages from gcc version...	blob \| commitdiff \| diff to current
2018-02-13	Maciej W. Rozycki	WebAssembly: Correct an `index' global shadowing error...	blob \| commitdiff \| diff to current
2018-02-12	Henry Wong	MIPS: Fix encoding for MIPSr6 sigrie instruction.	blob \| commitdiff \| diff to current
2018-02-05	Nick Clifton	Updated Brazillian portuguese and Russian translation	blob \| commitdiff \| diff to current
2018-01-23	Igor Tsimbalist	Enable Intel PCONFIG instruction.	blob \| commitdiff \| diff to current
2018-01-23	Igor Tsimbalist	Enable Intel WBNOINVD instruction.	blob \| commitdiff \| diff to current
2018-01-17	Jim Wilson	RISC-V: Fix bug in prior addi/c.nop patch.	blob \| commitdiff \| diff to current
2018-01-17	Igor Tsimbalist	Replace CET bit with IBT and SHSTK bits.	blob \| commitdiff \| diff to current
2018-01-16	Nick Clifton	Update translations for various binutils components.	blob \| commitdiff \| diff to current
2018-01-15	Jim Wilson	RISC-V: Add support for addi that compresses to c.nop.	blob \| commitdiff \| diff to current
2018-01-15	Nick Clifton	Update Ukranian translations for bfd, binutils, gas...	blob \| commitdiff \| diff to current
2018-01-13	Nick Clifton	Update pot files	blob \| commitdiff \| diff to current
2018-01-13	Nick Clifton	Bump version number to 2.30.51	blob \| commitdiff \| diff to current
2018-01-13	Nick Clifton	Add note about 2.30 branch creation to changelogs	blob \| commitdiff \| diff to current
2018-01-11	Igor Tsimbalist	Remove VL variants for 4FMAPS and 4VNNIW insns.	blob \| commitdiff \| diff to current
2018-01-10	Jan Beulich	x86: fix Disp8 handling for scalar AVX512_4FMAPS insns	blob \| commitdiff \| diff to current
2018-01-10	Jan Beulich	x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants	blob \| commitdiff \| diff to current
2018-01-10	Jim Wilson	RISC-V: Disassemble x0 based addresses as 0.	blob \| commitdiff \| diff to current
2018-01-09	James Greenhalgh	[Arm] Add CSDB instruction	blob \| commitdiff \| diff to current
2018-01-09	James Greenhalgh	Add support for the AArch64's CSDB instruction.	blob \| commitdiff \| diff to current
2018-01-08	H.J. Lu	x86: Properly encode vmovd with 64-bit memeory	blob \| commitdiff \| diff to current
2018-01-06	Jim Wilson	RISC-V: Print symbol address for jalr w/ zero offset.	blob \| commitdiff \| diff to current
2018-01-03	Alan Modra	Update year range in copyright notice of binutils files	blob \| commitdiff \| diff to current
2018-01-03	Alan Modra	ChangeLog rotation	blob \| commitdiff \| diff to current
2018-01-02	Jan Beulich	x86: partial revert of 10c17abdd0	blob \| commitdiff \| diff to current
2017-12-20	Jim Wilson	RISC-V: Add compressed instruction hints, and a few...	blob \| commitdiff \| diff to current
2017-12-19	Tamar Christina	Correct disassembly of dot product instructions.	blob \| commitdiff \| diff to current
2017-12-19	Tamar Christina	Add support for V_4B so we can properly reject it.	blob \| commitdiff \| diff to current
2017-12-18	Jan Beulich	x86: fold certain AVX and AVX2 templates	blob \| commitdiff \| diff to current
2017-12-18	Jan Beulich	x86: fold RegXMM/RegYMM/RegZMM into RegSIMD	blob \| commitdiff \| diff to current
2017-12-18	Jan Beulich	x86: drop FloatReg and FloatAcc	blob \| commitdiff \| diff to current
2017-12-18	Jan Beulich	x86: replace Reg8, Reg16, Reg32, and Reg64	blob \| commitdiff \| diff to current
2017-12-15	Dimitar Dimitrov	Fix disassembly for PowerPC	blob \| commitdiff \| diff to current
2017-12-15	Jan Beulich	x86: drop stray CheckRegSize uses	blob \| commitdiff \| diff to current
2017-12-13	Jim Wilson	Add missing RISC-V fsrmi and fsflagsi instructions.	blob \| commitdiff \| diff to current
2017-12-13	Dimitar Dimitrov	This patch enables disassembler_needs_relocs for PRU...	blob \| commitdiff \| diff to current
2017-12-11	Renlin Li	[Binutils][Objdump]Check symbol section information...	blob \| commitdiff \| diff to current
2017-12-03	Alan Modra	Fix "FAIL: VLE relocations 3"	blob \| commitdiff \| diff to current
2017-12-01	Peter Bergner	Use consistent types for holding instructions, instruct...	blob \| commitdiff \| diff to current
2017-11-30	Jan Beulich	x86: derive DispN from BaseIndex	blob \| commitdiff \| diff to current
2017-11-30	Jan Beulich	x86: drop Vec_Disp8	blob \| commitdiff \| diff to current
2017-11-29	Stefan Stroe	Support --localedir, --datarootdir and --datadir	blob \| commitdiff \| diff to current
2017-11-27	Nick Clifton	Update the simplified Chinese translation of the messag...	blob \| commitdiff \| diff to current
2017-11-24	Jan Beulich	x86: don't omit disambiguating suffixes from "fi*"	blob \| commitdiff \| diff to current
2017-11-23	Igor Tsimbalist	Add Disp8MemShift for AVX512 VAES instructions.	blob \| commitdiff \| diff to current
2017-11-23	Jan Beulich	x86: fix AVX-512 16-bit addressing	blob \| commitdiff \| diff to current
2017-11-23	Jan Beulich	x86: correct UDn	blob \| commitdiff \| diff to current
2017-11-22	Igor Tsimbalist	Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.	blob \| commitdiff \| diff to current
2017-11-22	Igor Tsimbalist	Update ChangeLog	blob \| commitdiff \| diff to current
2017-11-22	claziss	[ARC] Fix handling of ARCv2 H-register class.	blob \| commitdiff \| diff to current
2017-11-21	claziss	[ARC] Improve printing of pc-relative instructions.	blob \| commitdiff \| diff to current
2017-11-16	Tamar Christina	Add new AArch64 FP16 FM{A\|S} instructions.	blob \| commitdiff \| diff to current
2017-11-16	Tamar Christina	Add assembler and disassembler support for the new...	blob \| commitdiff \| diff to current
2017-11-16	Jan Beulich	x86: ignore high register select bit(s) in 32- and...	blob \| commitdiff \| diff to current
2017-11-15	Jan Beulich	x86: use correct register names	blob \| commitdiff \| diff to current
2017-11-15	Jan Beulich	x86: drop VEXI4_Fixup()	blob \| commitdiff \| diff to current
2017-11-15	Jan Beulich	x86-64: don't allow use of %axl as accumulator	blob \| commitdiff \| diff to current
2017-11-14	Jan Beulich	x86: add disassembler support for XOP VPCOM* pseudo-ops	blob \| commitdiff \| diff to current
2017-11-14	Jan Beulich	x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops	blob \| commitdiff \| diff to current
2017-11-14	Jan Beulich	x86: string insns don't allow displacements	blob \| commitdiff \| diff to current
2017-11-13	Jan Beulich	x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should...	blob \| commitdiff \| diff to current
2017-11-09	Tamar Christina	Add assembler and disassembler support for the new...	blob \| commitdiff \| diff to current
2017-11-09	Tamar Christina	Add the operand encoding types for the new Armv8.2...	blob \| commitdiff \| diff to current
2017-11-09	Tamar Christina	Adds the new Fields and Operand types for the new instr...	blob \| commitdiff \| diff to current
2017-11-09	Tamar Christina	Split the ARM Crypto ISA extensions for AES and SHA1...	blob \| commitdiff \| diff to current
2017-11-08	Nick Clifton	Split the AArch64 Crypto instructions for AES and SHA1...	blob \| commitdiff \| diff to current
2017-11-08	Jiong Wang	Adds command line support for Armv8.4-A, via the new...	blob \| commitdiff \| diff to current
2017-11-07	Andrew Burgess	opcodes/arc: Fix incorrect insn_class for some nps...	blob \| commitdiff \| diff to current
2017-11-07	Alan Modra	ngettext support	blob \| commitdiff \| diff to current
2017-11-03	claziss	[ARC] Force the disassam to use the hexadecimal number...	blob \| commitdiff \| diff to current
2017-11-03	claziss	[ARC] Sync opcode data base.	blob \| commitdiff \| diff to current
2017-10-25	Alan Modra	PR22348, conflicting global vars in crx and cr16	blob \| commitdiff \| diff to current
2017-10-24	Andrew Waterman	RISC-V: Fix disassembly of c.addi4spn, c.addi16sp,...	blob \| commitdiff \| diff to current
2017-10-23	Igor Tsimbalist	Add missing ChangeLog entries	blob \| commitdiff \| diff to current
2017-10-23	Igor Tsimbalist	Fix the master due to bad regenerated files	blob \| commitdiff \| diff to current
2017-10-18	Eric Botcazou	[Visium] Disassemble the operands of the stop instruction.	blob \| commitdiff \| diff to current
2017-10-13	James Bowman	FT32: support for FT32B processor - part 1	blob \| commitdiff \| diff to current
2017-10-09	Andreas Krebbel	S/390: Sync with latest POP - 3 new instructions	blob \| commitdiff \| diff to current
2017-10-09	Andreas Krebbel	S/390: Sync with IBM z14 POP - SI_RD format	blob \| commitdiff \| diff to current
2017-10-01	Alexander Fedotov	Add new mnemonics for VLE multiple load instructions	blob \| commitdiff \| diff to current
2017-09-27	Nick Clifton	Add support for the new names of the RISC-V fmv.x.s...	blob \| commitdiff \| diff to current
2017-09-26	Nick Clifton	Allow the macw and macl instructions to be used on...	blob \| commitdiff \| diff to current
2017-09-25	Sergio Durigan Junior	Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm...	blob \| commitdiff \| diff to current
2017-09-11	Kuan-Lin Chen	nds32: Rename __BIT() to N32_BIT().	blob \| commitdiff \| diff to current
2017-09-09	H.J. Lu	x86: Remove restriction on NOTRACK prefix position	blob \| commitdiff \| diff to current
2017-08-31	Nick Clifton	Add updated French translations for opcodes and gprof	blob \| commitdiff \| diff to current
2017-08-31	James Bowman	FT32: improve disassembly readability	blob \| commitdiff \| diff to current
2017-08-24	Alexander Fedotov	[PowerPC VLE] Add SPE2 and EFS2 instructions support	blob \| commitdiff \| diff to current
2017-08-23	Alan Modra	ppc-opc.c formatting	blob \| commitdiff \| diff to current
2017-08-22	Palmer Dabbelt	RISC-V: Mark "c.nop" as an alias	blob \| commitdiff \| diff to current
2017-08-21	Alexander Fedotov	[PowerPC VLE] Add LSP (Lightweight Signal Processing...	blob \| commitdiff \| diff to current
2017-08-09	Jiong Wang	[ARM] Don't warn on REG_SP when used in CRC32 instructions	blob \| commitdiff \| diff to current
2017-08-07	H.J. Lu	Mark big and mach with ATTRIBUTE_UNUSED	blob \| commitdiff \| diff to current
2017-08-07	Maciej W. Rozycki	GDB/opcodes: Remove arch/mach/endian disassembler asser...	blob \| commitdiff \| diff to current
2017-07-25	Nick Clifton	Fix typos in error and option messages in OPCODES library.	blob \| commitdiff \| diff to current
2017-07-24	Jiong Wang	[AArch64] Fix the bit pattern order in the comments...	blob \| commitdiff \| diff to current
2017-07-21	Andreas Krebbel	S/390: Support z14 as CPU name.	blob \| commitdiff \| diff to current
2017-07-20	Nick Clifton	Update the German translation for the opcodes library.	blob \| commitdiff \| diff to current
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