gdb: Don't skip prologue for explicit line breakpoints in assembler
[external/binutils.git] / include / opcode /
2017-11-09 Tamar ChristinaEnable the Dot Product extension by default for Armv8...
2017-11-09 Tamar ChristinaAdds the new Fields and Operand types for the new instr...
2017-11-09 Tamar ChristinaSplit the ARM Crypto ISA extensions for AES and SHA1...
2017-11-09 Nick CliftonChange the type of the aarch64_feature_set typedef...
2017-11-08 Nick CliftonSplit the AArch64 Crypto instructions for AES and SHA1...
2017-11-08 Jiong WangAdds command line support for Armv8.4-A, via the new...
2017-11-07 Palmer DabbeltRISC-V: Add satp as an alias for sptbr
2017-11-07 Tamar ChristinaThis patch similarly to the AArch64 one enables Dot...
2017-11-02 Siddhesh Poyarekaraarch64: Remove AARCH64_FEATURE_F16 from AARCH64_ARCH_V8_2
2017-10-25 Alan ModraPR22348, conflicting global vars in crx and cr16
2017-10-24 Andrew WatermanRISC-V: Only relax to C.LUI when imm != 0 and rd !...
2017-10-13 James BowmanFT32: support for FT32B processor - part 1
2017-09-11 Kuan-Lin Chennds32: Rename __BIT() to N32_BIT().
2017-08-24 Alexander Fedotov[PowerPC VLE] Add SPE2 and EFS2 instructions support
2017-08-21 Alexander Fedotov[PowerPC VLE] Add LSP (Lightweight Signal Processing...
2017-07-19 Claudiu Zissulescu[ARC] Add SJLI instruction.
2017-07-19 John Eric Martin[ARC] Add JLI support.
2017-07-18 Yuri ChornovianFix spelling typos.
2017-06-30 Georg-Johann LayAdd support for a __gcc_isr pseudo isntruction to the...
2017-06-30 Maciej W. RozyckiMIPS: Fix XPA base and Virtualization ASE instruction...
2017-06-28 Tamar Christina[AArch64] Add dot product support for AArch64 to binutils
2017-06-28 Jiong Wang[ARM] Assembler and disassembler support Dot Product...
2017-06-28 Maciej W. RozyckiMIPS: Add Imagination interAptiv MR2 MIPS32r3 processor...
2017-06-24 Thomas Preud'homme[ARM] Add support for ARMv8-R in assembler and readelf
2017-06-24 Thomas Preud'homme[ARM] Remove ARMv6S-M special casing
2017-06-21 Thomas Preud'homme[ARM] Rework Tag_CPU_arch build attribute value selection
2017-05-30 Andreas KrebbelS/390: Improve error checking for optional operands
2017-05-30 Andreas KrebbelS/390: Remove optional operand flag.
2017-05-23 claziss[ARC] Update MAX_INSN_FLGS.
2017-05-22 H.J. Lux86: Add NOTRACK prefix support
2017-05-19 Jose E. Marchesibinutils: support for the SPARC M8 processor
2017-05-15 Maciej W. RozyckiMIPS16e2: Add MIPS16e2 ASE support
2017-05-14 John David AnglinFix match and mask for 64-bit bb opcode.
2017-05-10 Claudiu Zissulescu[ARC] Object attributes.
2017-04-10 Alan ModraReorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500
2017-04-10 Alan ModraBye bye PPC_OPCODE_HTM and -mhtm
2017-04-10 Alan ModraBye Bye PPC_OPCODE_VSX3
2017-04-10 Alan ModraBye bye PPC_OPCODE_ALTIVEC2
2017-03-31 Andrew WatermanRISC-V: Add physical memory protection CSRs
2017-03-30 Pip CetAdd support for the WebAssembly file format and the...
2017-03-29 Alan ModraPowerPC -Mraw disassembly
2017-03-27 Rinat ZeligImplement ARC NPS-400 Ultra Ip and Miscellaneous instru...
2017-03-21 Andreas KrebbelS/390: Remove vx2 facility flag
2017-03-21 Rinat Zeligarc/nps400: Add cp16/cp32 instructions to opcodes library
2017-02-24 Richard Sandiford[AArch64] Additional SVE instructions
2017-02-24 Richard Sandiford[AArch64] Add a "compnum" feature
2017-02-24 Andrew WatermanAdd new counter-enable CSRs
2017-02-23 Andreas KrebbelS/390: Add support for new cpu architecture - arch12.
2017-02-23 Sheldon Loboopcodes,gas: associate SPARC ASIs with an architecture...
2017-02-15 Andrew WatermanAdd SFENCE.VMA instruction
2017-02-14 Alan ModraPowerPC register expression checks
2017-02-06 Claudiu Zissulescu[ARC] Provide an interface to decode ARC instructions.
2017-01-25 Dimitar DimitrovClarify that include/opcode/ files are part of GNU...
2017-01-04 Szabolcs Nagy[AArch64] Add separate feature flag for weaker release...
2017-01-03 Kito ChengAdd support for the Q extension to the RISCV ISA.
2017-01-02 Alan ModraUpdate year range in copyright notice of all files.
2016-12-31 Dimitar DimitrovPRU BFD support
2016-12-23 Maciej W. RozyckiMIPS16: Add ASMACRO instruction support
2016-12-23 Maciej W. RozyckiMIPS16: Reassign `0' and `4' operand codes
2016-12-23 Maciej W. RozyckiMIPS16: Handle non-extensible instructions correctly
2016-12-21 Alan ModraRemove high bit set characters
2016-12-20 Maciej W. RozyckiMIPS16: Switch to 32-bit opcode table interpretation
2016-12-13 Renlin Li[Binutils][AARCH64]Remove Cn register for coprocessor...
2016-12-09 Maciej W. RozyckiMIPS16: Remove unused `>' operand code
2016-12-07 Maciej W. RozyckiMIPS/include: opcode/mips.h: Correct INSN_CHIP_MASK
2016-12-07 Maciej W. RozyckiMIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3
2016-12-05 Szabolcs Nagy[ARM] Add ARMv8.3 command line option and feature flag
2016-11-29 Claudiu Zissulescu[ARC] Add checking for LP_COUNT reg usage, improve...
2016-11-22 Jose E. Marchesigas,opcodes: fix hardware capabilities bumping in the...
2016-11-22 Alan ModraPR20744, Incorrect PowerPC VLE relocs
2016-11-18 Szabolcs Nagy[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
2016-11-18 Szabolcs Nagy[AArch64] Add ARMv8.3 combined pointer authentication...
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 PACGA instruction
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 command line option and feature...
2016-11-04 Thomas Preud'hommeAdd support for ARM Cortex-M33 processor
2016-11-03 Graham Markallarc: Implement NPS-400 dcmac instruction
2016-11-03 Andrew Burgessarc: Change max instruction length to 64-bits
2016-11-03 Graham Markallopcodes/arc: Make some macros 64-bit safe
2016-11-03 Graham Markallarc: Replace ARC_SHORT macro with arc_opcode_len function
2016-11-01 Nick CliftonAdd support for RISC-V architecture.
2016-10-14 Claudiu Zissulescu[ARC] Disassembler: fix LIMM detection for short instru...
2016-09-29 Alan ModraDisallow 3-operand cmp[l][i] for ppc64
2016-09-26 Claudiu Zissulescu[ARC] ISA alignment.
2016-09-21 Richard Sandiford[AArch64] Add SVE condition codes
2016-09-21 Richard Sandiford[AArch64][SVE 31/32] Add SVE instructions
2016-09-21 Richard Sandiford[AArch64][SVE 30/32] Add SVE instruction classes
2016-09-21 Richard Sandiford[AArch64][SVE 29/32] Add new SVE core & FP register...
2016-09-21 Richard Sandiford[AArch64][SVE 28/32] Add SVE FP immediate operands
2016-09-21 Richard Sandiford[AArch64][SVE 27/32] Add SVE integer immediate operands
2016-09-21 Richard Sandiford[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
2016-09-21 Richard Sandiford[AArch64][SVE 25/32] Add support for SVE addressing...
2016-09-21 Richard Sandiford[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
2016-09-21 Richard Sandiford[AArch64][SVE 23/32] Add SVE pattern and prfop operands
2016-09-21 Richard Sandiford[AArch64][SVE 22/32] Add qualifiers for merging and...
2016-09-21 Richard Sandiford[AArch64][SVE 21/32] Add Zn and Pn registers
2016-09-21 Richard Sandiford[AArch64][SVE 20/32] Add support for tied operands
2016-09-21 Richard Sandiford[AArch64][SVE 13/32] Add an F_STRICT flag
2016-09-07 Richard Earnshaw[arm] Automatically enable CRC instructions on supporte...
2016-08-26 Cupertino MirandaFixes to legacy ARC relocations.
2016-08-01 Andrew Jenner Fix some PowerPC VLE BFD issues and add some...
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