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RISC-V: Set insn info fields correctly when disassembling.
[external/binutils.git] / include / opcode / riscv.h
2018-07-30 Jim WilsonRISC-V: Set insn info fields correctly when disassembling. blob | commitdiff
2018-03-14 Jim WilsonRISC-V: Add .insn support. blob | commitdiff | diff to current
2018-01-03 Alan ModraUpdate year range in copyright notice of binutils files blob | commitdiff | diff to current
2017-10-24 Andrew WatermanRISC-V: Only relax to C.LUI when imm != 0 and rd !... blob | commitdiff | diff to current
2017-01-03 Kito ChengAdd support for the Q extension to the RISCV ISA. blob | commitdiff | diff to current
2017-01-02 Alan ModraUpdate year range in copyright notice of all files. blob | commitdiff | diff to current
2016-11-01 Nick CliftonAdd support for RISC-V architecture. blob | commitdiff | diff to current
Domain: System / Toolchain;