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[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS
[external/binutils.git] / include / opcode / riscv-opc.h
2018-10-02 Palmer DabbeltRISC-V: Add fence.tso instruction blob | commitdiff
2018-05-08 Jim WilsonRISC-V: Add missing hint instructions from RV128I. blob | commitdiff | diff to current
2018-01-04 Jim WilsonRISC-V: Add 2 missing privileged registers. blob | commitdiff | diff to current
2017-12-28 Jim WilsonRISC-V: Add missing privileged spec registers. blob | commitdiff | diff to current
2017-11-07 Palmer DabbeltRISC-V: Add satp as an alias for sptbr blob | commitdiff | diff to current
2017-03-31 Andrew WatermanRISC-V: Add physical memory protection CSRs blob | commitdiff | diff to current
2017-02-24 Andrew WatermanAdd new counter-enable CSRs blob | commitdiff | diff to current
2017-02-15 Andrew WatermanAdd SFENCE.VMA instruction blob | commitdiff | diff to current
2017-01-03 Kito ChengAdd support for the Q extension to the RISCV ISA. blob | commitdiff | diff to current
2016-11-01 Nick CliftonAdd support for RISC-V architecture. blob | commitdiff | diff to current
Domain: System / Toolchain;