analyzer: fix feasibility false +ve on jumps through function ptrs [PR107582]
[platform/upstream/gcc.git] / gcc / config /
2022-11-18 Philipp TomsichRISC-V: No extensions for SImode min/max against safe...
2022-11-18 Philipp TomsichRISC-V: Handle "(a & twobits) == singlebit" in branches...
2022-11-18 Philipp TomsichRISC-V: Use bseti/bclri/binvi to extend reach of ori...
2022-11-18 Philipp TomsichRISC-V: Optimize slli(.uw)? + addw + zext.w into sh...
2022-11-18 Philipp TomsichRISC-V: split to allow formation of sh[123]add before...
2022-11-18 Philipp TomsichRISC-V: Optimize branches testing a bit-range or a...
2022-11-18 Philipp TomsichRISC-V: allow bseti on SImode without sign-extension
2022-11-18 Kyrylo Tkachovaarch64: Fix LDAPURS assembly output
2022-11-18 Kyrylo Tkachovaarch64: Fix up LDAPR codegen
2022-11-18 Jinyang HeLoongArch: Fix atomic_exchange expanding [PR107713]
2022-11-17 Philipp TomsichRISC-V: Optimize masking with two clear bits not a...
2022-11-17 Philipp TomsichRISC-V: bitmanip: add splitter to use bexti for "(a...
2022-11-17 mtsamisEnable shrink wrapping for the RISC-V target.
2022-11-17 Kyrylo Tkachovaarch64: Add mode size check on LDAPR-extend patterns
2022-11-17 Lili Cuix86: Enable 256 move by pieces for ALDERLAKE machine.
2022-11-17 Jia-Wei ChenRISC-V: Optimize RVV epilogue logic.
2022-11-17 Jeff LawFix multiple recent sh3/sh3eb regressions
2022-11-16 Philipp TomsichRISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext...
2022-11-16 Philipp TomsichRISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext...
2022-11-16 Alexander Monakovi386: correct x87&SSE multiplication modeling in znver.md
2022-11-16 Alexander Monakovi386: correct x87&SSE division modeling in znver.md
2022-11-16 Tobias Burnusgcn: Add __builtin_gcn_kernarg_ptr
2022-11-16 Max Filippovgcc: m68k: fix PR target/107645
2022-11-16 Tobias Burnusnvptx/mkoffload.cc: Fix "$nohost" check
2022-11-15 Philipp TomsichRISC-V: Zihintpause: add __builtin_riscv_pause
2022-11-15 David Faustbpf: avoid possible use of uninitialized variable
2022-11-15 Andre Vieiraaarch64: Add support for widening LDAPR instructions
2022-11-15 Andre Vieiraaarch64: Enable the use of LDAPR for load-acquire semantics
2022-11-14 Philipp TomsichRevert "RISC-V: Add basic support for the Ventana-VT1...
2022-11-14 Philipp TomsichRevert "RISC-V: Add instruction fusion (for ventana...
2022-11-14 Philipp Tomsichriscv: bitmanip: add orc.b as an unspec
2022-11-14 Philipp TomsichRISC-V: Add instruction fusion (for ventana-vt1)
2022-11-14 Philipp TomsichRISC-V: Add basic support for the Ventana-VT1 core
2022-11-14 Kyrylo Tkachovaarch64: Add support for +cssc
2022-11-14 Tamar ChristinaAArch64: Add SVE2 implementation for pow2 bitmask division
2022-11-14 Tamar ChristinaAArch64: Add implementation for pow2 bitmask division.
2022-11-14 Srinath Parvathaneniarm: Add support for Cortex-X1C CPU.
2022-11-14 Srinath Parvathaneniaarch64: Add support for Cortex-X3 CPU.
2022-11-14 Philipp Tomsichaarch64: Add support for Ampere-1A (-mcpu=ampere1a...
2022-11-14 Martin LiskaRevert "avr: sphinx: port gen-avr-mmcu to RST"
2022-11-14 Hongyu WangEnable small loop unrolling for O2
2022-11-13 Philipp TomsichRISC-V: optimize '(a >= 0) ? b : 0' to srai + andn...
2022-11-13 Philipp TomsichRISC-V: costs: support shift-and-add in strength-reduction
2022-11-12 Xi RuoyaoLoongArch: Add flogb.{s,d} instructions and expand...
2022-11-12 Xi RuoyaoLoongArch: Add fscaleb.{s,d} instructions as ldexp...
2022-11-12 Xi RuoyaoLoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions
2022-11-12 Xi RuoyaoLoongArch: Rename frint_<fmt> to rint<mode>2
2022-11-11 Srinath Parvathaneniaarch64: Add support for Cortex-X1C CPU.
2022-11-11 Srinath Parvathaneniaarch64: Add support for Cortex-A715 CPU.
2022-11-11 Ju-Zhe ZhongRISC-V: Add RVV registers register spilling
2022-11-11 Haochen Jiangi386: Add ISA check for newly introduced prefetch builtins.
2022-11-10 Andrew PinskiRemove SLOW_SHORT_ACCESS from target headers
2022-11-10 Philipp TomsichRISC-V: Fix selection of pipeline model for sifive...
2022-11-10 Jakub Jelineki386: Fix up ix86_expand_int_sse_cmp [PR107585]
2022-11-09 Martin Liskaavr: sphinx: port gen-avr-mmcu to RST
2022-11-09 Philipp TomsichRISC-V: costs: handle BSWAP
2022-11-09 Xi RuoyaoLoongArch: fix signed overflow in loongarch_emit_int_co...
2022-11-09 liuhongtFix incorrect insn type to avoid ICE in memory attr...
2022-11-08 David Faustbpf: Use enum for resolved overloaded builtins
2022-11-08 Kwok Cheung Yeungamdgcn: Fix expansion of GCN_BUILTIN_LDEXPV builtin
2022-11-08 Kwok Cheung Yeungamdgcn: Add builtins for vectorized native versions...
2022-11-08 Jakub Jelineki386: Improve vector [GL]E{,U} comparison against vecto...
2022-11-08 konglin1Revert "i386: Prefer remote atomic insn for atomic_fetc...
2022-11-08 Haochen JiangAdd m_CORE_ATOM for atom cores
2022-11-07 David Faustbpf: cleanup missed refactor
2022-11-07 Hu, Lin1Initial Grand Ridge support
2022-11-07 konglin1i386: Prefer remote atomic insn for atomic_fetch{add...
2022-11-07 konglin1Support Intel RAO-INT
2022-11-07 Haochen JiangInitial Granite Rapids Support
2022-11-07 Haochen JiangSupport Intel prefetchit0/t1
2022-11-06 Xi RuoyaoLoongArch: Add fcopysign instructions
2022-11-04 Kyrylo Tkachovaarch64: Fix typo in aarch64-sve.md comment
2022-11-04 Thomas SchwingeRemove support for Intel MIC offloading
2022-11-04 Thomas SchwingeBetter integrate default 'sorry' 'TARGET_ASM_CONSTRUCTO...
2022-11-04 Thomas SchwingeRestore default 'sorry' 'TARGET_ASM_CONSTRUCTOR', ...
2022-11-04 Hongyu WangSupport Intel AMX-FP16 ISA
2022-11-04 Haochen JiangInitial Sierra Forest Support
2022-11-04 Haochen JiangSupport Intel CMPccXADD
2022-11-03 Kwok Cheung Yeungamdgcn: Fix instruction generation for exp2 and log2...
2022-11-03 Uros Bizjaki386: Fix uninitialized register after peephole2 conver...
2022-11-03 Andrew Stubbsamdgcn: Fix duplicate conditionals [PR107510]
2022-11-02 Christoph MüllnerRISC-V: Add Zawrs ISA extension support
2022-11-02 Xionghu Luors6000: Byte reverse V8HI on Power8 by vector rotation.
2022-11-01 Alexander Monakovi386: correct integer division modeling in znver.md
2022-11-01 liuhongtFix incorrect digit constraint
2022-11-01 liuhongtEnable more optimization for 32-bit/64-bit shrd/shld...
2022-10-31 Ju-Zhe ZhongRISC-V: Change constexpr back to CONSTEXPR
2022-10-31 Andrew Stubbsamdgcn: add fmin/fmax patterns
2022-10-31 Andrew Stubbsamdgcn: multi-size vector reductions
2022-10-31 Andrew Stubbsamdgcn: Silence unused parameter warning
2022-10-31 konglin1Support Intel AVX-NE-CONVERT
2022-10-31 konglin1i386:: using __bf16 for AVX512BF16 intrinsics
2022-10-31 liuhongtEnable V4BFmode and V2BFmode.
2022-10-29 Iain Buclawd: Make TARGET_D_MINFO_SECTION hooks in elfos.h the...
2022-10-29 Iain Buclawd: Remove D-specific version definitions from target...
2022-10-29 Jeff LawFix signed vs unsigned issue in H8 port
2022-10-28 Joseph Myersc: tree: target: C2x (...) function prototypes and...
2022-10-27 Eric BotcazouAarch64: Do not define DONT_USE_BUILTIN_SETJMP
2022-10-27 H.J. Lux86: Replace ne:CCC/ne:CCO with UNSPEC_CC_NE in neg...
2022-10-27 Richard Sandifordaarch64: Reinstate some uses of CONSTEXPR
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