gdb.base/breakpoint-in-ro-region.exp regression on sss targets (PR gdb/22583)
[external/binutils.git] / gas /
2018-01-11 Igor TsimbalistRemove VL variants for 4FMAPS and 4VNNIW insns.
2018-01-10 Alan Modragas tc-arm.c warning fix
2018-01-10 Jan Beulichx86: fix Disp8 handling for scalar AVX512_4FMAPS insns
2018-01-10 Jan Beulichx86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants
2018-01-10 Jim WilsonRISC-V: Disassemble x0 based addresses as 0.
2018-01-09 James Greenhalgh[Arm] Add CSDB instruction
2018-01-09 James GreenhalghAdd support for the AArch64's CSDB instruction.
2018-01-08 H.J. Lux86: Properly encode vmovd with 64-bit memeory
2018-01-08 Nick CliftonAdd a description of the X86_64 assembler's .largcomm...
2018-01-04 Jim WilsonRISC-V: Add 2 missing privileged registers.
2018-01-03 Alan ModraUpdate year range in copyright notice of binutils files
2018-01-03 Alan ModraChangeLog rotation
2018-01-02 Nick CliftonFix typo in do_mrs function in ARM assembler.
2017-12-28 Jim WilsonRISC-V: Add missing privileged spec registers.
2017-12-20 Jim WilsonRISC-V: Add compressed instruction hints, and a few...
2017-12-19 Tamar ChristinaCorrect disassembly of dot product instructions.
2017-12-19 Tamar ChristinaAdd support for V_4B so we can properly reject it.
2017-12-18 Nick CliftonResolve PR 22493 - the encoding to be used when pushing...
2017-12-18 Jan Beulichx86: fold certain AVX and AVX2 templates
2017-12-18 Jan Beulichx86: fold RegXMM/RegYMM/RegZMM into RegSIMD
2017-12-18 Jan Beulichx86: drop FloatReg and FloatAcc
2017-12-18 Jan Beulichx86: replace Reg8, Reg16, Reg32, and Reg64
2017-12-17 H.J. Lux86: Check pseudo prefix without instruction
2017-12-15 Jan Beulichx86: correct operand type checks
2017-12-15 Jan Beulichx86: correct abort check
2017-12-14 Nick CliftonUpdate the address of the FSF in the copyright notice...
2017-12-13 Jim WilsonAdd missing RISC-V fsrmi and fsflagsi instructions.
2017-12-13 Dimitar DimitrovThis patch enables disassembler_needs_relocs for PRU...
2017-12-12 Alan ModraDon't mask X_add_number containing a register number
2017-12-08 Max Filippovgas: xtensa: fix comparison of trampoline chain symbols
2017-12-04 Alan ModraDocumentation fix
2017-12-03 Alan ModraRun powerpc vle gas tests for all powerpc ELF targets
2017-12-03 Jim WilsonFix for texinfo 4.8.
2017-12-01 Jim WilsonUpdate and clean up RISC-V gas documentation.
2017-12-01 Peter BergnerUse consistent types for holding instructions, instruct...
2017-11-30 Jan Beulichx86: drop Vec_Disp8
2017-11-30 Jan Beulichx86/Intel: issue diagnostics for redundant segment...
2017-11-30 Jan BeulichRevert "x86: Update segment register check in Intel...
2017-11-29 Jim WilsonGive Palmer co-credit for last patch.
2017-11-29 Jim WilsonFix riscv malloc error on small alignment after norvc.
2017-11-29 Jim WilsonIn x86 -n docs, mention that you need an explicit nop...
2017-11-29 Renlin Li[GAS][AARCH64]Fix a typo for IP1 register alias.
2017-11-29 Stefan StroeSupport --localedir, --datarootdir and --datadir
2017-11-29 Nick CliftonUse the record_alignment function when creating a ...
2017-11-28 Jim WilsonCompress loads/stores with implicit 0 offset.
2017-11-27 Max Filippovgas: xtensa: speed up find_trampoline_seg
2017-11-27 Max Filippovgas: xtensa: implement trampoline coalescing
2017-11-27 Max Filippovgas: xtensa: reuse trampoline placement code
2017-11-27 Max Filippovgas: xtensa: rewrite xg_relax_trampoline
2017-11-27 Max Filippovgas: xtensa: merge trampoline_frag into xtensa_frag_type
2017-11-27 Max Filippovgas: xtensa: reuse find_trampoline_seg
2017-11-27 Max Filippovgas: xtensa: extract jump assembling for trampolines
2017-11-27 Max Filippovgas: extract xg_relax_trampoline from xtensa_relax_frag
2017-11-27 Nick CliftonWhen creating a .note section to contain a version...
2017-11-26 H.J. Lugas: Update x86 sse-noavx tests
2017-11-24 Jim WilsonAdd reference to implicit use in _bfd_elf_is_local_labe...
2017-11-24 Jan Beulichx86: reject further invalid AVX-512 masking constructs
2017-11-24 Jan Beulichx86: don't omit disambiguating suffixes from "fi*"
2017-11-23 Jim WilsonFix vax/ns32k/mmix gas testsuite regression.
2017-11-23 Jim WilsonFix build error with --enable-targets=all.
2017-11-23 Igor TsimbalistAdd Disp8MemShift for AVX512 VAES instructions.
2017-11-23 Jan Beulichx86: fix AVX-512 16-bit addressing
2017-11-23 Jan Beulichx86-64: always use unsigned 32-bit reloc for 32-bit...
2017-11-23 Jan Beulichx86: drop redundant VSIB handling code
2017-11-23 Jan Beulichx86: correct UDn
2017-11-23 Jan Beulichx86/Intel: don't report multiple errors for a single...
2017-11-22 Jim WilsonRiscv ld-elf/stab failure and fake label cleanup.
2017-11-22 Jim WilsonUpdate docs on filling text with nops.
2017-11-22 Thomas Preud'homme[GAS/ARM] Clarify relation between reg_expected_msgs...
2017-11-22 claziss[ARC] Fix handling of ARCv2 H-register class.
2017-11-22 H.J. Lux86: Add tests for -n option of x86 assembler
2017-11-21 claziss[ARC] Improve printing of pc-relative instructions.
2017-11-21 Alan Modraxtensa error message
2017-11-20 Alan Modramingw gas testsuite fix
2017-11-16 Tamar ChristinaAdd new AArch64 FP16 FM{A|S} instructions.
2017-11-16 Tamar ChristinaCorrect AArch64 crypto dependencies.
2017-11-16 Tamar ChristinaUpdate documentation for Arvm8.4-A changes to AArch64.
2017-11-16 Tamar ChristinaAdd assembler and disassembler support for the new...
2017-11-16 Jan Beulichx86: ignore high register select bit(s) in 32- and...
2017-11-16 Jan Beulichix86/Intel: don't require memory operand size specifier...
2017-11-16 H.J. Lui386: Replace .code64/.code32 with .byte
2017-11-15 Tamar ChristinaSeparate the new FP16 instructions backported from...
2017-11-15 Nick CliftonAdd support to readelf and objdump for following links...
2017-11-15 Jan Beulichx86: use correct register names
2017-11-15 Jan Beulichx86: drop VEXI4_Fixup()
2017-11-15 Jan Beulichx86-64: don't allow use of %axl as accumulator
2017-11-15 Jim WilsonFirst part of fix for riscv gas lns-common-1 failure.
2017-11-14 Jan Beulichx86: add disassembler support for XOP VPCOM* pseudo-ops
2017-11-14 Jan Beulichx86: add support for AVX-512 VPCMP*{B,W} pseudo-ops
2017-11-14 Jan Beulichx86: string insns don't allow displacements
2017-11-13 Jan Beulichgas/arm64: don't emit stack pointer symbol table entries
2017-11-13 Jan Beulichgas/ia64: fix testsuite failures
2017-11-13 Jan Beulichx86: don't default variable shift count insns to 8...
2017-11-13 Jan Beulichx86/Intel: don't mistake riz/eiz as base register
2017-11-13 Jan Beulichx86-64/Intel: issue diagnostic for out of range displac...
2017-11-09 Jim WilsonFix riscv dwarf2-10 gas testsuite failure.
2017-11-09 Tamar ChristinaEnable the Dot Product extension by default for Armv8...
2017-11-09 Tamar ChristinaAdd assembler and disassembler support for the new...
2017-11-09 Tamar ChristinaAdds the new Fields and Operand types for the new instr...
2017-11-09 Tamar ChristinaSplit the ARM Crypto ISA extensions for AES and SHA1...
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