Accept L and LL suffixes to integer constants.
[external/binutils.git] / gas / ChangeLog
2016-11-11 Nick CliftonAccept L and LL suffixes to integer constants.
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 combined pointer authentication...
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 PACGA instruction
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 single source PAC instructions
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 pointer authentication key registers
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 instructions which are in the...
2016-11-11 Szabolcs Nagy[AArch64] Add ARMv8.3 command line option and feature...
2016-11-11 Szabolcs Nagy[AArch64] Fix feature dependencies for +simd and +crypto
2016-11-09 H.J. LuX86: Remove the .s suffix from EVEX vpextrw
2016-11-09 H.J. LuX86: Update opcode-suffix.d
2016-11-07 H.J. LuX86: Properly handle bad FPU opcode
2016-11-05 Nathan SidwellFix gas crash with unreasonably long lines
2016-11-04 Andrew Burgessarc/nps400: Validate address type operands correctly
2016-11-04 Thomas Preud'hommeAdd support for ARM Cortex-M33 processor
2016-11-04 Thomas Preud'hommeAdd support for ARM Cortex-M23 processor
2016-11-04 Palmer DabbeltUpdate RISC-V documentation and make sure that it is...
2016-11-03 Graham Markall[ARC] Fix ldbit test on 32-bit systems
2016-11-03 Graham Markallarc: Implement NPS-400 dcmac instruction
2016-11-03 Andrew Burgessarc: Change max instruction length to 64-bits
2016-11-03 Graham Markallarc: Replace ARC_SHORT macro with arc_opcode_len function
2016-11-03 Graham Markallgas/arc: Replace short_insn flag with insn length field
2016-11-03 Siddhesh PoyarekarNew option falkor for Qualcomm server part
2016-11-03 H.J. LuX86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
2016-11-03 Jiong Wang[ARM] Allow MOV/MOV.W to accept all possible immediates
2016-11-02 Igor TsimbalistEnable Intel AVX512_4VNNIW instructions
2016-11-02 Igor TsimbalistEnable Intel AVX512_4FMAPS instructions
2016-11-01 Nick CliftonAdd support for RISC-V architecture.
2016-10-27 Andrew Burgessgas/arc: Don't rely on bfd list of cpu type for cpu...
2016-10-26 Alan ModraRevert "bison warning fixes"
2016-10-21 H.J. LuX86: Remove pcommit instruction
2016-10-20 H.J. LuCheck invalid mask registers
2016-10-19 Renlin Li[GAS][ARM]Generate unpredictable warning for pc used...
2016-10-17 Cupertino MirandaFixed matching in newly added test.
2016-10-17 Cupertino MirandaRemoved pseudo invalid instructions opcodes.
2016-10-14 Claudiu Zissulescu[ARC] Disassembler: fix LIMM detection for short instru...
2016-10-11 Nick CliftonEnhance objdump so that it will use .got, .plt and...
2016-10-11 Jiong Wang[AArch64] PR target/20666, fix wrong encoding of new...
2016-10-10 Andreas KrebbelMIPS64: Adjust cfi* testcases.
2016-10-08 Alan ModraAuto-generated dependencies for rx-parse.o and rl78...
2016-10-07 Jiong Wang[AArch64] PR target/20667, fix disassembler for the...
2016-10-06 Claudiu Zissulescu[ARC] Fix parsing leave_s and enter_s mnemonics.
2016-10-06 Alan Modra-Wimplicit-fallthrough dodgy fixes
2016-10-06 Matthew FortuneRefine .cfi_sections check to only consider compact...
2016-10-05 Alan Modra-Wimplicit-fallthrough warning fixes
2016-10-05 Alan Modra-Wimplicit-fallthrough noreturn fixes
2016-10-05 Alan Modra-Wimplicit-fallthrough error fixes
2016-10-05 Alan Modrabison warning fixes
2016-09-30 Jiong Wang[AArch64] PR target/20553, fix opcode mask for SIMD...
2016-09-29 Alan ModraDisallow 3-operand cmp[l][i] for ppc64
2016-09-26 Trevor Saunderstc-xtensa.c: fixup xg_reverse_shift_count typo
2016-09-26 Vlad ZakharovWhen building target binaries, ensure that the warning...
2016-09-26 Alan ModraPowerPC .gnu.attributes
2016-09-22 Thomas Preud'hommeRemove legacy basepri_mask MRS/MSR special reg
2016-09-21 Richard Sandiford[AArch64] Print spaces after commas in addresses
2016-09-21 Richard Sandiford[AArch64] Use "must" rather than "should" in error...
2016-09-21 Richard Sandiford[AArch64] Add SVE condition codes
2016-09-21 Richard SandifordFix misplaced ChangeLog
2016-09-21 Richard Sandiford[AArch64][SVE 31/32] Add SVE instructions
2016-09-21 Richard Sandiford[AArch64][SVE 29/32] Add new SVE core & FP register...
2016-09-21 Richard Sandiford[AArch64][SVE 28/32] Add SVE FP immediate operands
2016-09-21 Richard Sandiford[AArch64][SVE 27/32] Add SVE integer immediate operands
2016-09-21 Richard Sandiford[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
2016-09-21 Richard Sandiford[AArch64][SVE 25/32] Add support for SVE addressing...
2016-09-21 Richard Sandiford[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
2016-09-21 Richard Sandiford[AArch64][SVE 23/32] Add SVE pattern and prfop operands
2016-09-21 Richard Sandiford[AArch64][SVE 22/32] Add qualifiers for merging and...
2016-09-21 Richard Sandiford[AArch64][SVE 21/32] Add Zn and Pn registers
2016-09-21 Richard Sandiford[AArch64][SVE 20/32] Add support for tied operands
2016-09-21 Richard Sandiford[AArch64][SVE 13/32] Add an F_STRICT flag
2016-09-21 Richard Sandiford[AArch64][SVE 12/32] Remove boolean parameters from...
2016-09-21 Richard Sandiford[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64...
2016-09-21 Richard Sandiford[AArch64][SVE 10/32] Move range check out of parse_aarc...
2016-09-21 Richard Sandiford[AArch64][SVE 09/32] Improve error messages for invalid...
2016-09-21 Richard Sandiford[AArch64][SVE 08/32] Generalise aarch64_double_precisio...
2016-09-21 Richard Sandiford[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYP...
2016-09-21 Richard Sandiford[AArch64][SVE 06/32] Generalise parse_neon_reg_list
2016-09-21 Richard Sandiford[AArch64][SVE 05/32] Rename parse_neon_type_for_operand
2016-09-21 Richard Sandiford[AArch64][SVE 04/32] Rename neon_type_el to vector_type_el
2016-09-21 Richard Sandiford[AArch64][SVE 03/32] Rename neon_el_type to vector_el_type
2016-09-21 Richard Sandiford[AArch64][SVE 01/32] Remove parse_neon_operand_type
2016-09-16 Claudiu Zissulescu[ARC] Disassemble correctly extension instructions.
2016-09-15 Jose E. Marchesigas: run the sparc test dcti-couples-v9 only in ELF...
2016-09-15 Peter BergnerModify POWER9 support to match final ISA 3.0 documentation.
2016-09-14 Jose E. Marchesigas: improve architecture mismatch diagnostics in sparc
2016-09-14 Jose E. Marchesigas: detect DCTI couples in sparc
2016-09-14 Claudiu Zissulescu[ARC] Fix parsing dtpoff relocation expression.
2016-09-12 Andreas KrebbelS/390: Add alternate processor names.
2016-09-12 Andreas KrebbelS/390: Fix facility bit default.
2016-09-12 Patrick SteuerS/390: Fix kmctr instruction type.
2016-09-08 H.J. LuAllow PROCESSOR_IAMCU for Intel MCU
2016-09-07 H.J. LuX86: Allow additional ISAs for IAMCU in assembler
2016-09-07 Richard Earnshaw[arm] Automatically enable CRC instructions on supporte...
2016-08-31 Alan ModraPowerPC VLE sh_flags and p_flags
2016-08-26 Jose E. Marchesiopcodes, gas: fix mnemonic of sparc camellia_fl
2016-08-26 Thomas Preud'hommeAdd missing ARMv8-M special registers
2016-08-25 Thomas Preud'hommeRemove _S version of ARM MSR/MRS special registers
2016-08-24 H.J. LuX86: Add ptwrite instruction
2016-08-19 Tamar ChristinaARM: Issue a warning when the MRRC and MRRC2 instructio...
2016-08-19 Nick CliftonPlace .shstrtab section after .symtab and .strtab,...
2016-08-11 Richard Sandiford[AArch64] Reject -0.0 as an 8-bit FP immediate
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