From: Jaehoon Chung Date: Tue, 25 Apr 2023 04:34:31 +0000 (+0900) Subject: riscv: jh7110: Fix build error during backporting X-Git-Tag: accepted/tizen/unified/20230703.143011~24 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=refs%2Fchanges%2F67%2F291967%2F1;p=platform%2Fkernel%2Fu-boot.git riscv: jh7110: Fix build error during backporting Fix build error during backporting baed on latest version. This patch is for only v2022.10. Change-Id: I2dd22cdf1672d3c397c16f546d87496a15b7f61d Signed-off-by: Jaehoon Chung --- diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index 2ad3f2044a..482f1f7cef 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -21,7 +21,7 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -phys_size_t board_get_usable_ram_top(phys_size_t total_size) +ulong board_get_usable_ram_top(ulong total_size) { /* * Ensure that we run from first 4GB so that all diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig index 2186a93964..f9a373d66c 100644 --- a/board/starfive/visionfive2/Kconfig +++ b/board/starfive/visionfive2/Kconfig @@ -12,7 +12,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "starfive-visionfive2" -config TEXT_BASE +config SYS_TEXT_BASE default 0x40200000 if SPL default 0x40000000 if !RISCV_SMODE default 0x40200000 if RISCV_SMODE