From: Joonyoung Shim <jy0922.shim@samsung.com>
Date: Wed, 1 Jul 2015 04:14:57 +0000 (+0900)
Subject: drm/exynos: fix vsync interrupt clear rountine of mixer
X-Git-Tag: submit/tizen/20150701.072642^0
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=refs%2Fchanges%2F38%2F42638%2F1;p=platform%2Fkernel%2Flinux-exynos.git

drm/exynos: fix vsync interrupt clear rountine of mixer

INT_EN_VSYNC bit is not used when we clear vsync interrupt but
INT_STATUS_VSYNC bit should be related.

Also, if we want to enable vsync interrupt, we should write 1 in
INT_CLEAR_VSYNC bit before we set INT_EN_VSYNC bit. It will clear prior
vsync interrupt. You can check it from exynos mixer user manual.

Change-Id: Ide955d5cb966e49883c51d8fab0eba51897bac7a
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
---

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 8c55ec580f36..4def1460d18c 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -765,15 +765,14 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
 			atomic_set(&ctx->wait_vsync_event, 0);
 			wake_up(&ctx->wait_vsync_queue);
 		}
-	}
 
 out:
-	/* clear interrupts */
-	if (~val & MXR_INT_EN_VSYNC) {
 		/* vsync interrupt use different bit for read and clear */
-		val &= ~MXR_INT_EN_VSYNC;
+		val &= ~MXR_INT_STATUS_VSYNC;
 		val |= MXR_INT_CLEAR_VSYNC;
 	}
+
+	/* clear interrupts */
 	mixer_reg_write(res, MXR_INT_STATUS, val);
 
 	spin_unlock(&res->reg_slock);
@@ -931,6 +930,7 @@ static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
 	}
 
 	/* enable vsync interrupt */
+	mixer_reg_write(res, MXR_INT_STATUS, MXR_INT_CLEAR_VSYNC);
 	mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
 			MXR_INT_EN_VSYNC);