From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Date: Mon, 14 Sep 2020 16:05:00 +0000 (+0200)
Subject: MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
X-Git-Tag: v4.9.237~13
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=ffb5d74b3e03fded94572b2a0f160cd61089571b;p=platform%2Fkernel%2Flinux-amlogic.git

MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT

[ Upstream commit 564c836fd945a94b5dd46597d6b7adb464092650 ]

Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f8a529c85279..24eb7fe7922e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -848,6 +848,7 @@ config SNI_RM
 	select I8253
 	select I8259
 	select ISA
+	select MIPS_L1_CACHE_SHIFT_6
 	select SWAP_IO_SPACE if CPU_BIG_ENDIAN
 	select SYS_HAS_CPU_R4X00
 	select SYS_HAS_CPU_R5000