From: Joseph Lo <josephl@nvidia.com>
Date: Wed, 31 Oct 2012 09:41:18 +0000 (+0800)
Subject: ARM: tegra30: common: enable csite clock
X-Git-Tag: v3.8-rc1~143^2~23^2~4
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fe508d776908b8512c6d936eb29e40bef1f4b8fc;p=platform%2Fkernel%2Flinux-exynos.git

ARM: tegra30: common: enable csite clock

Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gating low power state.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 3e03e5f..203a8b9 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -108,6 +108,7 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
 	{ "sclk",	"pll_p_out4",	102000000,	true },
 	{ "hclk",	"sclk",		102000000,	true },
 	{ "pclk",	"hclk",		51000000,	true },
+	{ "csite",	NULL,		0,		true },
 	{ NULL,		NULL,		0,		0},
 };
 #endif