From: Samin Guo <samin.guo@starfivetech.com>
Date: Thu, 8 Jun 2023 08:01:33 +0000 (+0800)
Subject: riscv: dts: starfive: jh7110: Add vpu/jpu nodes
X-Git-Tag: accepted/tizen/unified/riscv/20231013.094029~5
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fdab41d2cec76e75fc65dbddb31ee32e022c8078;p=platform%2Fkernel%2Flinux-starfive.git

riscv: dts: starfive: jh7110: Add vpu/jpu nodes

Add vpu/jpu nodes for jh7110 SOC

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>

[sw0312.kim: port the commit e2d1cdfe5ff5 from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel
 - Port upstream jh7110 clk and sys-reset controller macro name]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

Change-Id: Iae673d805d9549ba96f3c08ee93ea69148f68e1e
---

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index b3fa383..c66f130 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -996,6 +996,70 @@
 			status = "disabled";
 		};
 
+		jpu: jpu@13090000 {
+			compatible = "starfive,jpu";
+			reg = <0x0 0x13090000 0x0 0x300>;
+			interrupts = <14>;
+			clocks = <&syscrg JH7110_SYSCLK_CODAJ12_AXI>,
+				 <&syscrg JH7110_SYSCLK_CODAJ12_CORE>,
+				 <&syscrg JH7110_SYSCLK_CODAJ12_APB>,
+				 <&syscrg JH7110_SYSCLK_NOC_BUS_VDEC_AXI>;
+			clock-names = "axi_clk", "core_clk",
+				      "apb_clk", "noc_bus";
+			resets = <&syscrg JH7110_SYSRST_CODAJ12_AXI>,
+				 <&syscrg JH7110_SYSRST_CODAJ12_CORE>,
+				 <&syscrg JH7110_SYSRST_CODAJ12_APB>;
+			reset-names = "rst_axi", "rst_core", "rst_apb";
+			power-domains = <&pwrc JH7110_PD_VDEC>;
+			status = "disabled";
+		};
+
+		vpu_dec: vpu_dec@130A0000 {
+			compatible = "starfive,vdec";
+			reg = <0x0 0x130A0000 0x0 0x10000>;
+			interrupts = <13>;
+			clocks = <&syscrg JH7110_SYSCLK_WAVE511_AXI>,
+				 <&syscrg JH7110_SYSCLK_WAVE511_BPU>,
+				 <&syscrg JH7110_SYSCLK_WAVE511_VCE>,
+				 <&syscrg JH7110_SYSCLK_WAVE511_APB>,
+				 <&syscrg JH7110_SYSCLK_NOC_BUS_VDEC_AXI>;
+			clock-names = "axi_clk", "bpu_clk", "vce_clk",
+				      "apb_clk", "noc_bus";
+			resets = <&syscrg JH7110_SYSRST_WAVE511_AXI>,
+				 <&syscrg JH7110_SYSRST_WAVE511_BPU>,
+				 <&syscrg JH7110_SYSRST_WAVE511_VCE>,
+				 <&syscrg JH7110_SYSRST_WAVE511_APB>,
+				 <&syscrg JH7110_SYSRST_AXIMEM0_AXI>;
+			reset-names = "rst_axi", "rst_bpu", "rst_vce",
+				      "rst_apb", "rst_sram";
+			starfive,vdec_noc_ctrl;
+			power-domains = <&pwrc JH7110_PD_VDEC>;
+			status = "disabled";
+		};
+
+		vpu_enc: vpu_enc@130B0000 {
+			compatible = "starfive,venc";
+			reg = <0x0 0x130B0000 0x0 0x10000>;
+			interrupts = <15>;
+			clocks = <&syscrg JH7110_SYSCLK_VENC_AXI>,
+				 <&syscrg JH7110_SYSCLK_WAVE420L_BPU>,
+				 <&syscrg JH7110_SYSCLK_WAVE420L_VCE>,
+				 <&syscrg JH7110_SYSCLK_WAVE420L_APB>,
+				 <&syscrg JH7110_SYSCLK_NOC_BUS_VENC_AXI>;
+			clock-names = "axi_clk", "bpu_clk", "vce_clk",
+				      "apb_clk", "noc_bus";
+			resets = <&syscrg JH7110_SYSRST_WAVE420L_AXI>,
+				 <&syscrg JH7110_SYSRST_WAVE420L_BPU>,
+				 <&syscrg JH7110_SYSRST_WAVE420L_VCE>,
+				 <&syscrg JH7110_SYSRST_WAVE420L_APB>,
+				 <&syscrg JH7110_SYSRST_AXIMEM1_AXI>;
+			reset-names = "rst_axi", "rst_bpu", "rst_vce",
+				      "rst_apb", "rst_sram";
+			starfive,venc_noc_ctrl;
+			power-domains = <&pwrc JH7110_PD_VENC>;
+			status = "disabled";
+		};
+
 		dma: dma-controller@16050000 {
 			compatible = "starfive,jh7110-axi-dma";
 			reg = <0x0 0x16050000 0x0 0x10000>;