From: Christoph Hellwig Date: Wed, 18 Oct 2023 05:26:52 +0000 (+0200) Subject: riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT X-Git-Tag: v6.6.17~3691^2^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fd962781270e6452dd5b30c8aa0b3b0fbee06244;p=platform%2Fkernel%2Flinux-rpi.git riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT RISCV_NONSTANDARD_CACHE_OPS is also used for the pmem cache maintenance helpers, which are built into the kernel unconditionally. Signed-off-by: Christoph Hellwig Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20231018052654.50074-2-hch@lst.de Signed-off-by: Geert Uytterhoeven --- diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d607ab0..0ac0b53 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -277,7 +277,6 @@ config RISCV_DMA_NONCOHERENT config RISCV_NONSTANDARD_CACHE_OPS bool - depends on RISCV_DMA_NONCOHERENT help This enables function pointer support for non-standard noncoherent systems to handle cache management. diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index a57677f..d6e5e3a 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -3,7 +3,7 @@ menu "Cache Drivers" config AX45MP_L2_CACHE bool "Andes Technology AX45MP L2 Cache controller" - depends on RISCV_DMA_NONCOHERENT + depends on RISCV select RISCV_NONSTANDARD_CACHE_OPS help Support for the L2 cache controller on Andes Technology AX45MP platforms.